Abstract: A process system adapted for processing of or with a material therein. The process system includes: a sampling region for the material; an infrared photometric monitor constructed and arranged to transmit infrared radiation through the sampling region and to responsively generate an output signal correlative of the material in the sampling region, based on its interaction with the infrared radiation; and process control means arranged to receive the output of the infrared photometric monitor and to responsively control one or more process conditions in and/or affecting the process system.

Abstract: A method of manufacturing a semiconductor device includes measuring the reflectance at the surface of a semiconductor substrate provided with concave portions and deciding a deposition parameter that represents a deposition condition corresponding to the measured reflectance. Then, a metal film is formed on the semiconductor substrate under a condition corresponding to the deposition parameter.

Abstract: Methods for processing semiconductor materials and substrates with a focused or collimated light beam. Light may be directed on a sample to alter material properties at a depth below the surface. The focused light beam has a peak power density positioned at a selected depth, and absorption of light energy, resulting from selection of wavelength and optical characteristics of the substrate as a function of depth, results in process effects taking place over a preferred limited range of depth. For example, process effects such as curing, annealing, implant activation, selective melting, deposition and chemical reaction may be achieved at dimensions limited by the light beam density in the vicinity of the focused beam spot. The wavelength may be selected to be appropriate for the process effect chosen. The beam may be scanned over the substrate to selectively provide processing effects.

Abstract: A method of forming a monitor mark includes forming an insulating film on a semiconductor substrate, and forming a first repetitive line pattern group and a second repetitive line pattern group by patterning the insulating film on the semiconductor substrate, such that the first repetitive line pattern group and the second repetitive line pattern group face each other with a predetermined space therebetween.

Abstract: Methods and apparatus for assessing a constituent in a semiconductor substrate. Several embodiments of the invention are directed toward non-contact methods and systems for identifying an atom specie of a dopant implanted into the semiconductor substrate using techniques that do not mechanically contact the substrate with electrical leads or other types of mechanical measuring instruments. For example, one embodiment of a non-contact method of assessing a constituent in a semiconductor substrate in accordance with the invention comprises obtaining an actual reflectance spectrum of infrared radiation reflected from the semiconductor substrate, and ascertaining a plasma frequency value (?p) and a collision frequency value (?) for the semiconductor substrate based on the actual reflectance spectrum. This method can further include identifying a dopant type based on a relationship between dopant types and (a) plasma frequency values and (b) collision frequency values.

Abstract: The present invention generally provides methods and apparatus for monitoring ion dosage during a plasma process. One embodiment of the present invention provides a method for processing a substrate comprising generating a correlation between the at least one attribute of the plasma and a dosage quantity.

Abstract: In crystallization of a silicon film by annealing with a linear-shaped laser beam having an ununiform width of the short axis of the beam, the profile (intensity distribution) of the laser beam is evaluated, and the result is fed back to an oscillating condition of the laser beam or an optical condition which projects this onto the silicon film, whereby a display device comprising a high-quality crystalline silicon film is produced.

Abstract: A method for determining a polishing endpoint includes obtaining spectra from different zones on a substrate during different times in a polishing sequence, matching the spectra with indexes in a library and using the indexes to determining a polishing rate for each of the different zones from the indexes. An adjusted polishing rate can be determined for one of the zones, which causes the substrate to have a desired profile when the polishing end time is reached.

Abstract: There is provided a substrate processing method and apparatus which can measure and monitor thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate having a metal and an insulating material exposed on its surface in such a manner that a film thickness of the metal, with an exposed surface of the metal as a reference plane, is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal during and/or immediately after processing, and monitoring processing and adjusting processing conditions based on results of this measurement.

Abstract: A semiconductor manufacturing apparatus and substrate processing method is provided with which the film formed on a substrate can be controlled in thickness and quality.

Abstract: A CMOS image sensor and a method for manufacturing the same are disclosed, in which a blue photodiode is imparted with a greater thickness to improve sensitivity of blue light. The blue photodiode of a CMOS image sensor includes a first lightly doped P-type epitaxial layer formed on a heavily doped P-type semiconductor substrate; a gate electrode of a transfer transistor formed on the first epitaxial layer; a first N-type blue photodiode region formed on the first epitaxial layer; and a second N-type blue photodiode region formed on the first epitaxial layer corresponding to the first blue photodiode region.

Abstract: Bright and dark field imaging operations in an optical inspection system occur along substantially the same optical path using the same light source by producing either a circular or an annular laser beam. Multiple beam splitting is achieved through the use of a diffractive optical element having uniform diffraction efficiency. A confocal arrangement for bright field and dark field imaging can be applied with multiple beam scanning for suppressing the signal from under-layers. A scan direction not perpendicular to the direction of movement of a target provides for improved die-to-die comparisons.

Abstract: A method of controlling a recess etch process for a multilayered substrate having a trench therein and a column of material deposited in the trench includes determining a first dimension from a surface of the substrate to a reference point in the substrate by obtaining a measured net reflectance of at least a portion of the substrate including the trench, computing a modeled net reflectance of the portion of the substrate as a weighted incoherent sum of reflectances from n?1 different regions constituting the portion of the substrate, determining a set of parameters that provides a close match between the measured net reflectance and the modeled net reflectance, and extracting the first dimension from the set of parameters; computing an endpoint of the process as a function of the first dimension and a desired recess depth measured from the reference point; and etching down from a surface of the column of material until the endpoint is reached.

Abstract: A semiconductor manufacturing apparatus includes: an ion source and a beam line for introducing an ion beam into a target film which is formed over a wafer with an insulating film interposed therebetween; a flood gun for supplying the target film with electrons for neutralizing charges contained in the ion beam; a rotating disk for subjecting the target film to mechanical scanning of the ion beam in two directions composed of r-? directions; a rear Faraday cage for measuring the current density produced by the ion beam; a disk-rotational-speed controller and a disk-scanning-speed controller for changing the scanning speed of the target film; and a beam current/current density measuring instrument for controlling, according to the current density, the scanning speed of the target film.

Abstract: The invention regards a method and a system for establishing correspondence between wafers and solar cells produced from said wafers. The method comprises for each wafer and each solar cell, providing an image of the wafer, providing an image of the cell, comparing the wafer image to the cell image, upon match between a cell image and a wafer image, assigning the current cell to the current wafer. The system comprises at least one imaging device for providing images of the wafers and the cells, a processing unit for comparing a wafer image to a cell image, and upon match between a cell image and a wafer image, assigning the current cell to the current wafer, and a memory unit.

Abstract: A method wherein a substrate is provided, wherein, in a scanning step, structures already applied to the substrate are detected by at least one scanning provision of a processing head, wherein the processing head is provided with at least one lighting provision, which lighting provision locally lights the applied lacquer structure in a lighting step by using the information obtained with the scanning step. Further, the invention discloses an apparatus for carrying out the method is described, which apparatus is provided with a processing head which is movable relative to a substrate carrier, wherein the processing head comprises at least one scanning provision and at least one lighting provision.

Abstract: When a design diagram of the semiconductor device by a conventional CAD tool is used, a pattern which can be formed with the ink-jet apparatus is limited; therefore, there is a possibility that some circuits of the desired semiconductor device cannot be formed as they are designed. A plurality of basic patterns which can be obtained by discharging with the ink-jet apparatus are prepared, and layout of a desired integrated circuit is performed by combining the patterns. A light-exposure mask is formed based on the layout obtained. Light exposure is performed using the light-exposure mask. Then, development is performed, and the resist film remains in the light-exposed region of which width is narrower than the diameter of the droplet landed. Liquid repellent treatment is performed to an exposed portion on the surface, and then the material droplet is dropped over the resist film.

Abstract: In the present invention, the position of a substrate on a thermal plate is detected when baking after exposure is performed in a first round of patterning. In a second round of patterning, the setting position of the substrate is adjusted based on a detection result of the position before the substrate is mounted on the thermal plate in the baking after exposure. In the baking after exposure in the second round of patterning, the substrate is mounted at the same position with respect to the thermal plate as that in the baking after exposure in the first round of patterning. In performing a plurality of rounds of patterning on a film to be processed, a pattern with a desired dimension is finally formed above the substrate, and the uniformity of the pattern dimension within the substrate is ensured.

Abstract: A method is disclosed for forming right-angle contact/via holes for semiconductor devices. A device is provided on a substrate and covered with a first dielectric layer. A second dielectric layer having an etch rate different from that of the first layer is provided over the first layer. A first photoresist pattern is provided over the second layer to define an X or Y dimension of the contact/via hole. A second photoresist pattern is provided over the second layer to define an opposite dimension of the contact/via hole. First and second pattern dimensions are measured prior to etching to ensure appropriate dimensioning of the etched cavity. A second dry etch is then performed to form the contact/via hole. If the photoresist pattern is not within a desired tolerance, the etching process may be adjusted to ensure the cavity will have the desired dimensions.

Abstract: Methods and systems are provided of fabricating a compound nitride semiconductor structure. A substrate is disposed within a processing chamber into which a group-III precursor and a nitrogen precursor are flowed. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process using the precursors. The substrate is transferred to a transfer chamber where a temperature and a curvature of the layer are measured. The substrate is then transferred to a second processing chamber where a second layer is deposited.

Abstract: A processing termination detection method capable of accurately performing changeover of etch rates when a residual film thickness of a to-be-processed layer decreases to a predetermined value. A substrate processing apparatus starts first etching to form a through-hole in a single crystal silicon layer of a wafer. A processing termination detection apparatus irradiates laser light comprised of red to near-infrared light onto the wafer and performs a frequency analysis of reflected light received from the wafer. When the intensity, represented in a result of the frequency analysis, in a frequency band corresponding to residual layer interference light has exceeded a threshold value, second etching is started to remove a through hole formation portion of the single crystal silicon layer to cause a silicon oxide layer to be exposed.

Abstract: Disclosed are a semiconductor wafer (10) having a front side laser scribe (22) and the methods for manufacturing the same. The methods of the invention include the formation of a scribe foundation (12) on the front side of the semiconductor wafer (10) designed to accept laser scribing (22), and laser scribing the scribe foundation (12). Disclosed embodiments include a semiconductor wafer (10) having a scribe foundation (12) of layered dielectric (30) and metal (34) on the front side. According to disclosed embodiments of the invention, the formation of a scribe foundation (12) is performed in combination with the formation of a top level metal layer (34) on the semiconductor wafer (10) methods for manufacturing.

Abstract: The present invention attracts a wafer 6, placed on a susceptor 5, toward the susceptor 5 by the electrostatic attractive power of an electrostatic chuck electrode 7, varies the output voltage of a variable direct current power source 23 for the electrostatic chuck electrode 7 while measuring the temperature of the wafer 6 by a temperature detection sensor 21; and detects the potential of the wafer 6 based on the output voltage of the variable direct current power source 23 at a time when the temperature of the wafer 6 peaks.

Abstract: Methods and systems for monitoring a parameter of a measurement device during polishing, damage to a specimen during polishing, a characteristic of a polishing pad, or a characteristic of a polishing tool are provided. One method includes scanning a specimen with a measurement device during polishing of a specimen to generate output signals at measurement spots on the specimen. The method also includes determining if the output signals are outside of a range of output signals. Output signals outside of the range may indicate that a parameter of the measurement device is out of control limits. In a different embodiment, output signals outside of the range may indicate damage to the specimen. Another method includes scanning a polishing pad with a measurement device to generate output signals at measurement spots on the polishing pad. The method also includes determining a characteristic of the polishing pad from the output signals.

Abstract: A semiconductor wafer has a front side, a rear side and an edge which runs along the circumference of the semiconductor wafer and which connects the front side and the rear side of the edge having a defined edge profile, the edge profile being substantially constant over the entire circumference of the semiconductor wafer. A method for producing such a wafer allows for production of a multiplicity of semiconductor wafers, the edge profile being substantially constant from semiconductor wafer to semiconductor wafer.

Abstract: Provided are a light emitting diode (LED) module and a method of manufacturing the same. The LED module may include a package housing including an inner space, a light-emitting chip in the inner space of the package housing, a phosphor layer including a fluorescent material and converting light emitted from the light-emitting chip to light having a longer wavelength than that of the light emitted from the light-emitting chip. The concentration of the fluorescent material of the phosphor layer may be inhomogeneous. The method of manufacturing the LED module may include providing or forming a package housing having an inner space and including a light-emitting chip in the inner space, measuring a radiation pattern of light emitted from the light-emitting chip, and forming a phosphor layer including a fluorescent material on the light-emitting chip and having characteristics that may be determined according to the radiation pattern.

Abstract: Aspects of the invention can provide a method of effectively observing the photodecomposition process of a monolayer in real time. The invention can provide a method of observing the decomposition process of a monolayer when the monolayer is irradiated with UV rays, where the structure of the constituent molecule of the monolayer in an ultrahigh vacuum atmosphere and an oxygen-containing atmosphere respectively can be measured by a molecular structure measuring device during the UV irradiation. The invention can also provide a method of controlling the degree of surface decomposition of the monolayer that controls the ozone concentration accompanying the UV irradiation based on observation results obtained by using the observation method. The invention can further provide a method of patterning the monolayer that employs the control method.

Abstract: By incorporating an etch control material after the formation of a material layer to be patterned, an appropriate material having a highly distinctive radiation wavelength may be used for generating a distinctive endpoint detection signal during an etch process. Advantageously, the material may be incorporated by ion implantation which provides reduced non-uniformity compared to etch non-uniformities, while the implantation process provides the potential for introducing even very “exotic” implantation species. In some embodiments, the substrate-to-substrate uniformity of the patterning of dual damascene structures may be increased.

Abstract: A computer implemented method for development profile simulation in accordance with an embodiment of the present invention includes calculating optical intensities in a photosensitive resist, calculating a spatial average value of the optical intensities, reading a measured changing ratio of a dissolution rate of the photosensitive resist relating to an alkaline concentration changed by at least one of exposure dose on the photosensitive resist, a position in the thickness direction of the photosensitive resist and an alkaline concentration of developer for the photosensitive resist, obtaining a calculated dissolution rate by using the spatial average value and the measured changing ratio, and predicting a pattern shape of the photosensitive resist from the calculated dissolution rate.

Abstract: A system for personalizing one or more electrical circuits having plurality of layers with electrical characteristics. The layers being produced by an electrical characteristic determination process (ECDP). The system for personalizing includes a wafer stage for receiving a wafer in order to produce a plurality of electrical circuits. The system is configured to apply a personalization process during production of the layers. The personalization process includes using a first ECDP in the layer to produce identical electrical characteristics on the wafer in each of the plurality of electrical circuits, and using a second ECDP in the layer to modify one or more electrical characteristics in selected electrical circuits so as to incorporate in the selected circuits an individualized digital number, giving rise to the desired personalizing of one or more of the specified electrical circuits. Related apparatus and methods are also provided.

Abstract: An embodiment of the present invention is a technique to control carbon nanotubes (CNTs). A laser beam is focused to a carbon nanotube (CNT) in a fluid. The CNT is responsive to a trapping frequency. The CNT is manipulated by controlling the focused laser beam.

Abstract: Aspects of the present invention include methods and apparatuses that may be used for monitoring and adjusting plasma in a substrate processing system by using a plasma data monitoring assembly. For example, an optical instrument adapted to measure properties of light over a specific portion of the electromagnetic spectrum may be used to detect one or more wavelength intensities from the plasma. Then, an electronic device, for example a computer software may analyze the wavelength intensities and a match circuit may then be adjusted. In this way, consistent plasma may be obtained. In other embodiments, the present invention may utilize the relationship between chamber pressure, substrate temperature, coil currents and/or the plasma in order to adjust and maintain a repeatable plasma process.

Abstract: A treatment method of a semiconductor wafer includes treating the semiconductor wafer in a first solution having at least one kind of an oxidative acid and an oxidizing agent and treating the semiconductor wafer in a second solution having at least one of HF and NH4F.

Abstract: Various embodiments include a method for providing instructions to a process tool. The method includes emitting an incident light beam at a substrate, receiving a reflected light beam from the substrate and determining a spectrum of the reflected light beam. The method further includes determining a first property of a first layer of the substrate and a second property of a second layer of the substrate, based on the spectrum determination. The method further includes comparing the first property of the first layer to a first reference property and comparing the second property of the second layer to a second reference property. The method further includes determining the instructions based on the first property comparison and the second property comparison; and providing the instructions to the process tool.

Abstract: A positioning apparatus for positioning a substrate. The positioning apparatus includes a setting system which selectively sets one of a center of the substrate and a specific portion of an edge of the substrate as a positioning reference in accordance with information inputted to the positioning apparatus, and a positioning system which positions the substrate based on a position of the positioning reference set by the setting system.

Abstract: Embodiments of the invention provide a method, structure, service, etc. for variable overlap of dummy shapes for improved rapid thermal anneal uniformity. A method of providing uniform temperatures across a limited region of a wafer during a rapid thermal anneal process comprises determining a first reflectivity in a first portion of the limited region by measuring a density of first structures in the first portion. Next, the method determines a second reflectivity in a second portion of the limited region by measuring a density of second structures in the second portion. Specifically, the first structures comprise diffusion fill shapes and polysilicon conductor fill shapes (non-active dummy structures); and, the second structures comprise active circuit structures.

Abstract: This disclosure concerns methods for fabrication of integrated high speed optoelectronic devices. In one example of such a method, a device region that includes a top surface and a bottom surface is formed on a top surface of a substrate. The device region may take the form of an optical emitter, such as a VCSEL, or a detector, such as a photodiode. Next, an isolation region is formed that is configured such that the device region is surrounded by the isolation region. A superstrate is then disposed on the top surface of the device region. Finally, a micro-optical device, such as a lens, is placed on a top surface of the superstrate.

Abstract: In determining an endpoint of etching a substrate, light that is directed toward the substrate is reflected from the substrate. A wavelength of the light is selected to locally maximize the intensity of the reflected light at an initial time point of the etching process. The reflected light is detected to determine an endpoint of the substrate etching process.

Abstract: A sensor on a semiconductor wafer is used as a process monitor and a capacitor is employed as a power supply for the sensor. The capacitor can be formed by stacking a poly-silicon layer and a silicon nitride layer on the wafer. A timer can be used to specify an operation time or an operation timing, etc. Furthermore, unauthorized use is prevented by storing a keyword in an ROM of the process monitor.

Abstract: An apparatus and method for detection of a feature etch completion within an etching reactor. The method includes determining a correlation matrix by recording first measured data regarding a first etch process over successive time intervals to form a first recorded data matrix, assembling a first endpoint signal matrix using target endpoint data for a specific etch process, performing a partial least squares analysis on the recorded data matrix and the first endpoint signal matrix to refine the recorded data matrix, and computing a correlation matrix based upon the refined recorded data matrix and the first endpoint signal matrix. The method further includes performing a second etch process to form a second recorded data matrix. The correlation matrix and the second recorded data matrix are analyzed to determine whether an endpoint of the second etch process has been achieved.

Abstract: The present invention is generally directed to various methods and systems for dynamically controlling metrology work in progress. In one illustrative embodiment, the method comprises providing a metrology control unit that is adapted to control metrology work flow to at least one metrology tool, identifying a plurality of wafer lots that are in a metrology queue wherein the wafer lots are intended to be processed in at least one metrology tool, and wherein the metrology control unit selects at least one of the wafer lots for metrology processing in the at least one metrology tool and selects at least one other of the plurality of wafer lots to be removed from the metrology queue based upon the metrology processing of the selected at least one wafer lot in the at least one metrology tool.

Abstract: The present invention provides a method and apparatus for comparing device and non-device structures. The method includes determining at least one characteristic parameter associated with at least one non-device structure on at least one workpiece and determining at least one characteristic parameter associated with at least one device structure on the at least one workpiece. The method also includes comparing the at least one characteristic parameter associated with the at least one non-device structure and the at least one characteristic parameter associated with at least one device structure.

Abstract: A method includes measuring a gate leakage current of a plurality of transistors. A single stress bias voltage is applied to the plurality of transistors. The stress bias voltage causes a 10% degradation in a drive current of each transistor within a respective stress period t. One or more relationships are determined, between the measured gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors, respectively. A negative bias temperature instability (NBTI) lifetime ? of the plurality of transistors is estimated, based on the measured gate leakage current and the one or more relationships.

Abstract: A substrate can efficiently be manufactured by separating the alignment and the actual processing when an alignment mark is provided, which is fixed with respect to the substrate and when position information on a position of a process area on the substrate is retrieved with respect to the alignment mark before the substrate is processed. During the processing alignment can then be performed by redetermining the position of the alignment mark only once and by using the stored position information on the position of the process area.

Abstract: A method of manufacturing a plurality of microlenses on a substrate comprises forming a grid having raised ridges defining a plurality of openings on the substrate and forming a plurality of patterned photoresist features each disposed within one of the plurality of openings. The plurality of patterned photoresist features can then be reflowed inside the grid.

Abstract: This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light from top of the wafer.

Abstract: A test structure includes a first plurality of lines and a second plurality of lines intersecting the first plurality of lines. The first and second pluralities of lines defining a grid having openings. A method for determining grid dimensions includes providing a wafer having a test structure comprising a plurality of intersecting lines that define a grid having openings; illuminating at least a portion of the grid with a light source; measuring light reflected from the illuminated portion of the grid to generate a reflection profile; and determining a dimension of the grid based on the reflection profile. A metrology tool is adapted to receive a wafer having a test structure comprising a plurality of intersecting lines that define a grid having openings. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the grid.

Abstract: A solid state nanopore device including two or more materials and a method for fabricating the same. The device includes a solid state insulating membrane having an exposed surface, a conductive material disposed on at least a portion of the exposed surface of the solid state membrane, and a nanopore penetrating an area of the conductive material and at least a portion of the solid state membrane. During fabrication a conductive material is applied on a portion of a solid state membrane surface, and a nanopore of a first diameter is formed. When the surface is exposed to an ion beam, material from the membrane and conductive material flows to reduce the diameter of the nanopore. A method for evaluating a polymer molecule using the solid state nanopore device is also described. The device is contacted with the polymer molecule and the molecule is passed through the nanopore, allowing each monomer of the polymer molecule to be monitored.

Abstract: Methods for producing phosphor based light sources are disclosed. One method includes measuring an excitation light output of an LED, forming a plurality of phosphor film articles, measuring an optical characteristic of each of the plurality of phosphor film articles, selecting one of the plurality of phosphor film articles based on the LED excitation light output and measured optical characteristic of the one of the plurality of phosphor film articles to obtain a desired emission light output from the phosphor film article when the phosphor film article is positioned to receive the excitation light, and positioning the phosphor film article to receive the excitation light.

Abstract: A method for determining metrology sampling rates for workpieces in a process flow includes determining a current status of the process flow. Future processing of the workpieces in the process flow is simulated based on the current status of the process flow over a predetermined time horizon to predict sampling rates for the workpieces. During the simulating, sampling rules are implemented that consider capacity constraints of a metrology resource in the process flow. Actual workpieces in the process flow are sampled based on the predicted metrology sampling rates.