Abstract: A method for controlling etch processes during fabrication of semiconductor devices comprises tests and measurements performed on non-product and product substrates to define an N-parameter CD control graph that is used to calculate a process time for trimming a patterned mask to a pre-determined width. An apparatus for performing such a method.

Abstract: The present invention is generally directed to an advanced process control of the manufacture of memory devices, and a system for accomplishing same. In one illustrative embodiment, the method comprises performing at least one process operation to form at least one layer of an oxide-nitride-oxide stack of a memory cell, the stack being comprised of a first layer of oxide positioned above a first layer of polysilicon, a layer of silicon nitride positioned above the first layer of oxide, and a second layer of oxide positioned above the layer of silicon nitride. The method further comprises measuring at least one characteristic of at least one of the first layer of polysilicon, the first oxide layer, the layer of silicon nitride, and the second layer of oxide and adjusting at least one parameter of at least one process operation used to form at least one of the first oxide layer, the layer of silicon nitride and the second oxide layer if the measured at least one characteristic is not within acceptable limits.

Abstract: An apparatus and method for etching a feature in a wafer with improved depth control and reproducibility is described. The feature is etched at a first etching rate and then at a second etching rate, which is slower than the first etching rate. An optical end point device is used to determine the etching depth and etching is stopped so that the feature has the desired depth. Two different etching rates provides high throughput with good depth control and reproducibility. The apparatus includes an etching tool in which a chuck holds the wafer to be etched. An optical end point device is positioned to measure the feature etch depth. An electronic controller communicates with the optical end point device and the etching tool to control the tool to reduce the etch rate part way through etching the feature and to stop the etching tool, so that that the feature is etched to the desired depth.

Abstract: CMP process control array groups are fabricated upon the surface of the wafer for viewing through an optical microscope. The array groups include a plurality of test arrays, where each array includes a plurality of projecting test features. Each of the projecting test features are formed with the same projecting height and have a hard upper surface layer, such as diamond-like-carbon (DLC). All of the projecting test features within an array are formed with the same diameter, and the diameter of projecting test features of a particular array differs from the diameter of projecting test features in another array. The diameters are chosen such that the DLC surface is removed in specifically designed time increments, such as 5 seconds, from array to array, where projecting test features with the DLC surface removed appear as bright white, while the arrays with test features that retain some DLC surface are significantly darker.

Abstract: A method for automated monitoring and controlling of a semiconductor wafer plasma process including performing a plasma process in a plasma processing system to treat a semiconductor process wafer according to a first plasma process recipe; collecting plasma process parameters including at least an RF power and a plasma process time at pre-determined time intervals; and, storing the plasma process parameters including pre-process plasma processing system parameters according to a selectively queryable database to create a plasma process history such that upon abortion of the plasma process the plasma process history may be selectively retrieved to determine a second plasma process recipe to complete the plasma process.

Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing CD microloading variation. OCD metrology is used to inspect a wafer to determine pre-etch CD microloading, by measuring the CD of dense and isolated photoresist lines. Other parameters can also be measured or otherwise determined, such as sidewall profile, photoresist layer thickness, underlying layer thickness, photoresist pattern density, open area, etc. The inspection results are fed forward to the etcher to determine process parameters, such as resist trim time and/or etch conditions, thereby achieving the desired post-etch CD microloading. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.

Abstract: A method for preparing a semiconductor wafer for whole wafer backside inspection is disclosed. The frontside of the wafer is covered with a protective frontside substrate and the backside portion of the wafer is thinned using conventional techniques. The whole wafer backside is then polished and a backside substrate, preferably of transparent material is juxtaposed to the backside of the wafer, such as with an adhesive or with a frame. The frontside substrate is then removed, exposing electronic devices for device inspection. The backside of the wafer is maintained open or available to backside inspection such as emission microscopy techniques used to detect defects which emit light.

Abstract: A sidewall or other feature in a semiconductor wafer is evaluated by illuminating the wafer with at least one beam of electromagnetic radiation, and measuring intensity of a portion of the beam reflected by the wafer. Change in reflectance between measurements provides a measure of a property of the feature. The change may be either a decrease in reflectance or an increase in reflectance, depending on the embodiment. A single beam may be used if it is polarized in a direction substantially perpendicular to a longitudinal direction of the sidewall. A portion of the energy of the beam is absorbed by the sidewall, thereby to cause a decrease in reflectance when compared to reflectance by a flat region. Alternatively, two beams may be used, of which a first beam applies heat to the feature itself or to a region adjacent to the feature, and a second beam is used to measure an increase in reflectance caused by an elevation in temperature due to heat transfer through the feature.

Abstract: A method for detecting surface or near surface metal contamination in a semiconductor or silicon structure is described in which the structure or a part thereof is exposed to an excitation beam of predetermined wavelength and collecting luminescence from the structure in as the form of PL map having a substantially uniform PL intensity level provided by the semiconductor; and inspecting the map for one or more regions of enhanced PL intensity identifying characteristic surface or near surface metal contamination. In particular, the method is applied as an in-process quality control or as a quality control of processed structures such as interconnects.

Abstract: A process system adapted for processing of or with a material therein. The process system includes: a sampling region for the material; an infrared photometric monitor constructed and arranged to transmit infrared radiation through the sampling region and to responsively generate an output signal correlative of the material in the sampling region, based on its interaction with the infrared radiation; and process control means arranged to receive the output of the infrared photometric monitor and to responsively control one or more process conditions in and/or affecting the process system.

Abstract: Under the first embodiment of the invention, back-end etching is applied to the specimen that needs to be inspected. Its surface is cleaned and mounted on a glass surface with the surface of the poly gate silicide that needs to be inspected being in contact with the surface of the glass. The exposed surface of the sample that is to be examined contains silicon, this silicon is removed. The gate oxide is then removed followed by the removal of the remaining poly of the gate structure. The second embodiment of the invention addresses poly gate inspection by enhanced (top surface of the gate electrode) gas etching of the gate electrode to remove gate oxide and silicon remains from the environment of the silicide. The specimen is etched back to the contact layer using a conventional Chemical Mechanical Polishing (CMP) process. The polished surface of the specimen is next exposed to XeF2, which selectively removes the oxide while the silicide remains in place.

Abstract: A method and an apparatus for predicting excursions based upon tool state variables. At least one semiconductor wafer is processed in a processing tool. Tool state data relating to the processing tool is acquired. The tool state data comprises at least one tool state variable. A determination is made whether an excursion of the tool health related to the processing tool has occurred based upon the tool state data. The tool state variable is modified to reduce the excursion of the tool health in response to the determination that the excursion of the tool health has occurred.

Abstract: A method for controlling a photolithography process includes forming a first layer on a selected wafer. A first overlay error associated with the first layer is measured. At least one parameter in an operating recipe for performing a photolithography process on a second layer formed on the first wafer is determined based on at least the first overlay error measurement. A processing line includes a photolithography stepper, and overlay metrology tool, and a controller. The photolithography stepper is configured to process wafers in accordance with an operating recipe. The overlay metrology tool is configured to measure overlay errors associated with the processing of the wafers in the photolithography stepper.

Abstract: A test method provides a sample of wafer level defects most likely to cause yield loss on a semiconductor wafer subdivided into a plurality of integrated circuits (ICs). Defect size and location data from an inspection tool is manipulated in an algorithm based on defect sizes and geometry parameters. The defects are classified by defect size to form size based populations. The contribution of each size range of defect population to yield loss is calculated and random samples for review are selected from each defect size population. The number of samples from each size defect population is proportional to the predicted yield impact of each sample. The method is rapid and permits on-line process modification to reduce yield losses.

Abstract: A method for exposing a semiconductor wafer compensates for the effects of process inhomogeneities, e.g. in semiconductor etching or deposition processes, by individually adjusting sets of exposure parameters of an exposure tool for any exposure field. The exposure parameters are preferably the dose and the focus, which are varied across the semiconductor wafer.

Abstract: The invention relates to a device and method for automatically determining the surface quality of a bonding interface between two wafers. The device includes a detector for automatically detecting a bonding wave at a predetermined measuring site to determine when bonding occurs at the measuring site, and a processing unit for automatically calculating the bonding speed based on a location of the measuring site and at least one other predetermined site.

Abstract: A method of manufacturing a light emitting semiconductor package, the method comprising the steps of: obtaining a semiconductor wafer 252 which includes a plurality of light emitting devices 254 residing on or in a surface of the semiconductor wafer 252; forming at least one first hollow cap 256, each first hollow cap 256 formed to provide: a central portion 260 and first perimeter walls extending from the perimeter edge of the central portion with the free edges of the first perimeter walls adapted to be bonded to the surface of the semiconductor wafer 252 to provide a first cavity; at least one region 258 of the central portion 260 which is substantially transparent or translucent to electromagnetic radiation; bonding the at least one first hollow cap 256 to the semiconductor wafer 252, the central portion overlying at least one of the plurality of light emitting devices 254; and, separating the semiconductor wafer 252 with bonded caps 256 into light emitting semiconductor packages 250.

Abstract: A method is provided wherein a temperature reading error of a pyrometer is avoided. An upper pyrometer is used to detect infrared radiation from a test layer formed on a test substrate under standard processing conditions. The infrared radiation from the test layer has a period having a length which is indicative of growth rate of the layer. The period is generally inversely proportional to the growth rate. The growth rate is directly related to the temperature.

Abstract: Deviations from optimum values of the exposure light quantity and focus of test and product circuit patterns are predicted from the dimensions of the patterns, illumination conditions and the wave aberration of an exposure lens. A signal waveform of scatterometry of the test pattern is linked to the deviations from the optimum values of the exposure light quantity and focus to form a library. The test pattern after exposed and developed in actual steps is collated with the signal waveform in the library measured by the scatterometry to find deviations from the optimum values of the exposure light quantity and focus of the test pattern. Deviations of the optimum values of a product circuit pattern from the deviations of the test pattern are acquired on the basis of the deviations, and the acquired deviations are fed back to subsequent exposure steps.

Abstract: A method for enhancing the fabrication process of a self-aligned contact (SAC) structure is provided. The method includes forming a transistor structure on a surface of a substrate. The method also includes forming a dielectric layer directly over the surface of the substrate without forming an etch stop layer on the surface of the substrate. Also included in the method is plasma etching a contact hole through the dielectric layer in a plasma processing chamber. The method also includes monitoring a bias compensation voltage of the plasma processing chamber during the plasma etching process and discontinuing the plasma etching process upon detecting an endpoint signaling change in the bias compensation voltage.

Abstract: The present invention provides a method for optimizing the overlay adjustment of two mask planes in a photolithographic process for the production of an integrated circuit having the following steps: provision of a substrate (S) with at least one first mask plane (ME), which has been patterned by exposure of a first mask using a first exposure device; orientation of a second mask (M), which is provided for the patterning of a second mask plane using a second exposure device, with respect to the first mask plane (ME); measurement of the overlay between the first mask plane (ME) and the second mask (M); analysis of the measured overlay taking account of error data (FAD, FXD, FBD, FYD) provided, in advance regarding errors (FA, FX, FB, FY) of the first and second masks and/or errors of the first and second exposure devices; carrying out of a correction of the orientation of the second mask (M) depending on the result of the analysis.

Abstract: A mounting system for mounting an electronic component on a substrate includes a component identifying apparatus that identifies an electronic component to be mounted on the substrate. The component identifying apparatus includes a holding mechanism that holds the electronic component, a color-perceptive sensor that perceives a color of a predetermined region on the electronic component, and a data processor that identifies the electronic component on the basis of the color perceived by the color-perceptive sensor. The mounting system also includes a controller that controls an electronic component mounting operation on the basis of a result of identification obtained by the component identifying apparatus.

Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile to adjust the next process the inspected wafer will undergo (e.g., a photoresist trim process). After the processing step, dimensions of a structure formed by the process, such as the CD of a gate formed by the process, are measured, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. By taking into account photoresist CD and profile variation when choosing a resist trim recipe, post-etch CD is decoupled from pre-etch CD and profile. With automatic compensation for pre-etch CD, a very tight distribution of post-etch CD is achieved. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment.

Abstract: An optical semiconductor module having a large endothermic amount of an electronic cooling element can be provided, even if the area of the bottom plate of a package is the same. A package 11 includes two or more units of electronic cooling element 16 mounted therein. Each unit of the electronic cooling element is inserted through the space between inner juts 14a of ceramic feedthrough of the package 11 and a bottom plate 13, and is fixed to the bottom plate. The plural units of electronic cooling element are connected in series by one or more copper piece. The total area of junction between the two or more units of electronic cooling element and the bottom plate area of the package 11 occupies 75% or more of the area of the bottom plate. Thus, the ratio of the area of junction between the bottom plate and the electronic cooling element as a whole to the area of the bottom plate of the package can be increased.

Abstract: A method of forming a ferroelectric film includes the steps of forming a layer by a material that takes a metal state in a reducing ambient and an oxide state in an oxidizing ambient, and depositing a ferroelectric film on a surface of the layer by supplying gaseous sources of the ferroelectric film and an oxidizing gas and causing a decomposition of the gaseous sources at the surface of said layer, wherein the step of depositing the ferroelectric film is started with a preparation step in which the state of the surface of said layer is controlled substantially to a critical point in which the layer changes from the metal state to the oxide state and from the oxide state to the metal state.

Abstract: A substrate is placed in a process zone and an energized process gas is maintained in the process zone to process the substrate. A light beam is reflectively diffracted from a pattern of features of the substrate being processed, the reflected beam is monitored, and a signal is generated in relation to the monitored beam. During processing, a width of the features of the substrate can change. The generated signal is evaluated to detect the occurrence of a change in the width of the features.

Abstract: Real-time analysis and control of a semiconductor silicidation process. The architecture includes system and methods for monitor and control of a silicidation process during rapid thermal anneal. An FTIR system analyzes selected and/or random regions where silicidation is occurring, and signals the process control system to control the process according to the status of the analyzed silicide formations.

Abstract: A device manufacturing method capable of imaging structures on both sides of a substrate, is presented herein. One embodiment of the present invention comprises a device manufacturing method that etches reversed alignment markers on a first side of a substrate to a depth of 10 ?m, the substrate is flipped over, and bonded to a carrier wafer and then lapped or ground to a thickness of 10 ?m to reveal the reversed alignment markers as normal alignment markers. The reversed alignment markers may comprise normal alignment patterns overlaid with mirror imaged alignment patterns.

Abstract: A system and/or method are disclosed for measuring and/or controlling refractive index (n) and/or lithographic constant (k) of an immersion medium utilized in connection with immersion lithography. A known grating structure is built upon a substrate. A refractive index monitoring component facilitates measuring and/or controlling the immersion medium by utilizing detected light scattered from the known grating structure.

Abstract: A system detects the clearing of a dielectric at a plurality of contact sites by measuring the surface voltage of the dielectric and comparing the surface voltage to a reference voltage set to a value that relates to the cleared contact sites. Another system detects the clearing of a dielectric at a plurality of contact sites on a substrate by measuring the rate of change of a substrate current during an etch process and ending the etch process when the rate of change is approximately zero. Another system detects the clearing of a dielectric at a contact site by measuring a substrate current during an etch process and ends the etch process when the measured substrate current exceeds a predetermined value.

Abstract: The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

Abstract: A profile parameter value is determined in integrated circuit metrology by: a) determining a diffraction signal difference based on a measured diffraction signal and a previously generated diffraction signal; b) determining a first profile parameter value based on the previously generated diffraction signal; c) determining a first profile parameter value change based on the diffraction signal difference; d) determining a second profile parameter value based on the first profile parameter value change; e) determining a second profile parameter value change between the first and second profile parameter values; f) determining if the second profile parameter value change meets one or more preset criteria; and g) when the second profile parameter value change fails to meet the one or more preset criteria, iterating c) to g) using as the diffraction signal difference in the iteration of step c), a diffraction signal difference determined based on the measured diffraction signal and a diffraction signal for the sec

Abstract: In a system and a method for controlling critical dimensions of features to be formed on a substrate, a measurement device is coupled to an etch tool to form a feedback loop to control the critical dimensions on a wafer basis instead of a lot basis. In a further embodiment, the etch tool is in communication with a control unit that allows controlling of the etch tool and/or of the photolithography tool on the basis of an etch model. Thus, variations within a lot may be compensated by a software implementation of the etch model. The control unit may be implemented in the etch tool or an external device.

Abstract: A mirror device having an optical system of an exposure apparatus for transferring a reticle pattern onto a wafer includes a mirror, a mirror holding portion, a temperature adjustment unit, a control management database, and a timing control unit. The mirror reflects exposure light, and the mirror holding portion holds the mirror. The temperature adjustment unit adjusts a temperature of the mirror and the mirror holding portion. The control management database stores data corresponding to a controlling rule of the temperature adjustment unit necessary to keep the mirror figure constant for an incidence condition of the reflected exposure light. The timing control unit controls the temperature adjustment unit corresponding to the incidence condition of the exposure light. The timing control unit controls the temperature adjustment unit based on the stored data of the control management database to keep the mirror figure constant.

Abstract: A method and an apparatus for precisely exposing a predetermined width of a peripheral area of a wafer coated with a layer of photoresist material with light from a light source, wherein the wafer is moved when the light is radiated onto the wafer to expose the photoresist layer at the peripheral area of the wafer, an inspection section inspecting whether the light is radiated onto a precise position of the peripheral area of the wafer, whereby by adjusting the position of the light source if the light is not radiated at the precise position of the peripheral area of the wafer requiring exposure while inspecting the light radiated onto the peripheral area of the wafer, the predetermined width of the peripheral area of the wafer is precisely exposed.

Abstract: When determining the presence of foreign particles in a processing chamber by radiating a laser beam inside a processing chamber and detecting scattered light from foreign particles within the processing chamber, the detection of scattered light is performed using a detecting lens having a wide field angle and deep focal depth. Accordingly, the detection of foreign particles floating in the processing chamber can be performed across a wide range, and with uniform sensitivity, with a detecting optical system having a simple constitution.

Abstract: A system and method for determining endpoint detection in semiconductor wafer planarization is provided. The system and method provide a flexible solution that can compensate for baseline variability induced errors that may otherwise occur in endpoint detection. The system uses an endpoint detection signal that monitors the optical characteristics of the wafer being planarized. The system and method continue to monitor the detection signal during planarization until it meets endpoint criterion that indicates endpoint completion. When the endpoint criterion is reached, a new snapshot is taken from a previous time period and a new baseline is calculated. The endpoint detection signal is then recalculated based upon the new baseline and the recalculated detection signal is again compared to the endpoint criterion. If the recalculated endpoint detection signal again substantially meets the endpoint criterion then the detection of endpoint is confirmed.

Abstract: The present invention is generally directed to various control methodologies using optical emission spectroscopy derived data, and a system for performing same. In one illustrative embodiment, the method comprises performing an etching process within an etch tool to define at least one feature above a semiconducting substrate, obtaining optical emission spectroscopy data for the etching process, and controlling at least one parameter of the etching process based upon a comparison of the obtained optical emission spectroscopy data and target optical emission spectroscopy data associated with at least one of a target profile and a target critical dimension for the at least one feature.

Abstract: The present invention provides a process for producing a polycrystal silicon film which comprises a step of forming a polycrystal silicon film by light irraditation of a silicon film set on a substrate, and a step of selecting substrate samples having an average grain size in a plane of the sample of 500 nm or more. According to the present invention, stable production of a high-performance poly-silicon TFT liquid crystal display becomes possible.

Abstract: It is an object to provide a laser apparatus, a laser irradiating method and a manufacturing method of a semiconductor device that can perform uniform a process with a laser beam to an object uniformly. The present invention provides a laser apparatus comprising an optical system for sampling a part of a laser beam emitted from an oscillator, a sensor for generating an electric signal including fluctuation in energy of the laser beam as a data from the part of the laser beam, a means for performing signal processing to the electrical signal to grasp a state of the fluctuation in energy of the laser beam, and controlling a relative speed of an beam spot of the laser beam to an object in order to change in phase with the fluctuation in energy of the laser beam.

Abstract: An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the subsequent fast scan speed so as to compensate for the effect of any variation in beam current on dose uniformity in the slow scan direction. The scanning may produce a raster of non-intersecting uniformly spaced parallel scan lines and the spacing between the lines is selected to ensure appropriate dose uniformity.

Abstract: The present invention is directed to a system, method and software program product for calculating metrological data (e.g. layer thicknesses and depths of recesses and trenches) on a surface or structure, such as a semiconductor wafer. The present method does not require knowledge of the reflectivity or transmissivity of the surface or structure, but only a quantity related to the reflectivity or transmissivity linear transformation needs to be known. Initially, a simplified optical model for the process is constructed using as many parameters as necessary for calculating the surface reflectivity of the discrete regions on the wafer. Reflectivity data are collected from the surface of a wafer using, for instance, in-situ monitoring, and nominal reflectivity is determined from the ratio of the current spectrum to a reference spectrum. The reference spectrum is taken from a reference wafer consisting entirely of a material in which the reflection properties are well characterized.

Abstract: A substrate alignment apparatus which aligns and fixes a substrate on a substrate stage includes a chucking pad fixed on the substrate stage to chuck and fix the substrate, a moving unit which moves the substrate with respect to the substrate stage such that a mark on the substrate stage and a mark on the substrate coincide with each other, and a determination unit which manages a relative position between the chucking pad and the substrate after movement by the moving unit and determines whether the chucking pad can normally chuck the substrate.

Abstract: One aspect of the present invention relates to a system for determining and controlling a microloading effect in order to achieve desired feature depth on a wafer. The system includes a semiconductor structure having one or more layers formed over a substrate, a fabrication process assembly for forming features on the semiconductor structure, a microloading characterization system for monitoring the fabrication process, measuring feature depth, and for processing the measurements in order to ascertain the microloading effect, a detection apparatus operatively coupled to the microloading characterization system to facilitate monitoring the fabrication process and measuring feature depth, and a control system for regulating the fabrication process based on the output from the microloading characterization system.

Abstract: A wafer bumping method comprising the following steps of. A wafer having fields is provided. The wafer having at least one wafer identification character formed thereon within one or more of the fields. A dry film resist is formed over the wafer. Portions of the dry film resist are selectively exposed field by field using a mask whereby the mask is shifted over the one or more fields containing the at least one wafer identification character so that the one or more fields containing the at least one wafer identification character is double exposed after the mask shift so that all of the one or more fields containing the at least one wafer identification character is completely exposed. The selectively exposed dry film resist is developed to remove the non-exposed portions of the dry film resist.

Abstract: A method of efficiently testing optical chips while still on the wafer is presented. One or more gutters for each chip on the wafer is provided, and either (1) a test signal is applied to the gutter to generate a response from the chip; or (2) a test signal is applied to the chip to generate a response from the gutter, where the gutter is in optical communication with the chip, and can reflect light incident or outgoing light at substantially a ninety degree angle.

Abstract: A method of processing a semiconductor device is provided with several steps, including the step of generating plasma in a processing chamber to form or process a thin firm on a semiconductor device. The step of scanning, through a window, intensity modulated laser beam, which is modulated at a desired frequency inside the processing chamber where the semiconductor device is being processed. The step of receiving by a sensor through the window a back scattered light being scattered from fine particles suspended in the processing chamber by the scanning laser and detecting the desired frequency component from a signal outputted from the sensor. From the detected frequency component information relating to quantity, size, and distribution of the fine particles illuminated by the laser beam inside the processing chamber is obtained. This information is then outputted.

Abstract: A method includes providing a wafer having a first grating structure and a second grating structure formed in a photoresist layer. At least a portion of the first and second grating structures is illuminated with a light source. Light reflected from the illuminated portion of the first and second grating structures is measured to generate a reflection profile. Misregistration between the first and second grating structures is determined based on the reflection profile. A processing line includes a photolithography stepper, a metrology tool, and a controller. The photolithography stepper is adapted to process wafers in accordance with an operating recipe. The metrology tool is adapted to receive a wafer processed in the stepper. The wafer has a first grating structure and a second grating structure formed in a photoresist layer. The metrology tool includes a light source, a detector, and a data processing unit.

Abstract: A correlation between develop inspect (DI) and final inspect (FI) profile parameters are established empirically with test wafers. During production, a wafer is measured at DI phase to obtain DI profile parameters and FI phase profile parameters are predicted according to the DI profile parameters and the established correlation. Each wafer is subsequently measured at FI phase to obtain actual FI profile parameters and the correlation is updated with actual DI and FI profile parameters.

Abstract: The invention relates to a device comprising a process chamber which is arranged in a reaction housing and which can be heated especially by supplying heat to a substrate holder, comprising a gas inlet for the admission of gaseous starting material, whereby the decomposition products thereof are deposited on a substrate maintained by a substrate holder to form a layer, also comprising at least one sensor acting upon the inside of the process chamber for determining layer properties further comprising an electronic control unit for controlling the heating of the process chamber, mass controllers for controlling the flow of the starting materials and a pump for controlling the pressure of the process chamber, characterized in that the electronic control unit forms modified process parameters from deviation values obtained upon growth of the calibrating layer with the aid of stored calibrating parameters, thereby controlling the heating of the process chamber, the flow controllers and the pump upon growth of the