Optical Characteristic Sensed Patents (Class 438/7)
  • Publication number: 20090148964
    Abstract: A method for determining conditions for forming a dielectric SiOCH film, includes: (i) forming a dielectric SiOCH film on a substrate under conditions; (ii) evaluating the conditions using a ratio of Si—CH3 bonding strength to Si—O bonding strength of the film as formed in step (i); (iii) if the ratio is 2.50 % or higher, confirming the conditions, and if the ratio is less than 2.50 %, changing the conditions by changing at least one of the susceptor temperature, the distance between upper and lower electrodes, the RF power, and the curing time; and (iv) repeating steps (i) to (iii) until the ratio is 2.50 % or higher.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 11, 2009
    Applicant: ASM JAPAN K.K.
    Inventors: Naoto Tsuji, Kiyohiro Matsushita, Manabu Kato, Noboru Takamure
  • Patent number: 7544619
    Abstract: An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate layer, an anti-reflection film and an upper layer resist film are formed on the conductive film. A focal point at a time of exposure is detected by detecting a height of the upper layer resist film. In detecting the focal point at the time of exposure, a focal point detection light is radiated on the upper layer resist film. After detecting the focal point, the upper layer resist film is exposed and developed thereby to form a resist pattern. With the resist pattern as a mask, the intermediate layer and the anti-reflection film are patterned, and the lower layer resist film is developed. With these patterns as a mask, the conductive film is etched thereby to form a gate electrode.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: June 9, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Takeo Ishibashi
  • Patent number: 7541201
    Abstract: Disclosed are overlay targets having flexible symmetry characteristics and metrology techniques for measuring the overlay error between two or more successive layers of such targets. In one embodiment, a target includes structures for measuring overlay error (or a shift) in both the x and y direction, wherein the x structures have a different center of symmetry (COS) than the y structures. In another embodiment, one of the x and y structures is invariant with a 180° rotation and the other one of the x and y structures has a mirror symmetry. In one aspect, the x and y structures together are variant with a 180° rotation. In yet another example, a target for measuring overlay in the x and/or y direction includes structures on a first layer having a 180 symmetry and structures on a second layer having mirror symmetry.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: June 2, 2009
    Assignee: KLA-Tencor Technologies Corporation
    Inventor: Mark Ghinovker
  • Patent number: 7541230
    Abstract: Laser beams emitted by a plurality of laser sources are divided into a plurality of sub-beams, which are irradiated onto selected portions of an amorphous semiconductor on a substrate to crystallize the amorphous semiconductor. A difference in diverging angles between the laser beams is corrected by a beam expander. The apparatus includes a sub-beam selective irradiating system including a sub-beam dividing assembly and a sub-beam focussing assembly. Also, the apparatus includes laser sources, a focussing optical system, and a combining optical system. A stage for supporting a substrate includes a plurality of first stage members, a second stage member disposed above the first stage members, and a third stage member 38C, rotatably disposed above the second stage to support an amorphous semiconductor.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: June 2, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Nobuo Sasaki, Koichi Ohki
  • Patent number: 7537941
    Abstract: Embodiments of the invention provide a method, structure, service, etc. for variable overlap of dummy shapes for improved rapid thermal anneal uniformity. A method of providing uniform temperatures across a limited region of a wafer during a rapid thermal anneal process comprises determining a first reflectivity in a first portion of the limited region by measuring a density of first structures in the first portion. Next, the method determines a second reflectivity in a second portion of the limited region by measuring a density of second structures in the second portion. Specifically, the first structures comprise diffusion fill shapes and polysilicon conductor fill shapes (non-active dummy structures); and, the second structures comprise active circuit structures.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: May 26, 2009
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Howard S. Landis, Edward J. Nowak
  • Publication number: 20090117672
    Abstract: A method of fabricating a light emitting device having a specific target color, CIE xy, of emitted light is described. The device comprises a light emitting diode that is operable to emit light of a first wavelength range and at least one phosphor material which converts at least a part of the light into light of a second wavelength range wherein light emitted by the device comprises the combined light of the first and second wavelength ranges. The method comprises: depositing a pre-selected quantity of the at least one phosphor material on a light emitting surface of the light emitting diode; operating the light emitting diode; measuring the color of light emitted by the device; comparing the measured color with the specific target color; and depositing and/or removing phosphor material to attain the desired target color.
    Type: Application
    Filed: October 1, 2007
    Publication date: May 7, 2009
    Applicant: Intematix Corporation
    Inventors: James Caruso, Charles O. Edwards
  • Publication number: 20090104719
    Abstract: A method of in-situ monitoring of a plasma doping process includes generating a plasma comprising dopant ions in a chamber proximate to a platen supporting a substrate. A platen is biased with a bias voltage waveform having a negative potential that attracts ions in the plasma to the substrate for plasma doping. A dose of ions attracted to the substrate is measured. At least one sensor measurement is performed to determine the condition of the plasma chamber. In addition, at least one plasma process parameter is modified in response to the measured dose and in response to the at least one sensor measurement.
    Type: Application
    Filed: October 23, 2007
    Publication date: April 23, 2009
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Atul Gupta, Timothy Miller, Harold M. Persing, Daniel Distaso, Vikram Singh
  • Publication number: 20090104720
    Abstract: Provided are a photoresist coating apparatus and a method of coating photoresist using the same. The apparatus includes a photoresist supply line through which photoresist is supplied. A fluid control valve is connected to the photoresist supply line to control the flow of the photoresist. A nozzle assembly is connected to the photoresist supply line at a rear end of the fluid control valve. The nozzle assembly includes a nozzle located above the center of a semiconductor wafer loaded in a photoresist coating unit to spray the photoresist. A camera is located outside the photoresist coating unit to monitor the shape or spraying amount of the nozzle located at the tip of the nozzle assembly. A controller converts data monitored by the camera into an electric signal and processes the electric signal.
    Type: Application
    Filed: March 30, 2007
    Publication date: April 23, 2009
    Applicant: Nanofa Co., Ltd
    Inventors: Young-Joon Seo, Young-Jong Kwon
  • Publication number: 20090098665
    Abstract: Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.
    Type: Application
    Filed: October 15, 2007
    Publication date: April 16, 2009
    Inventors: Haowen BU, Scott Gregory Bushman, Periannan Chidambaram
  • Patent number: 7517705
    Abstract: The invention relates to a phosphorus-containing polymer for coating dielectric materials, to processes for its preparation and to its use, as well as to an optical signal transducer having a coating of the polymer and to its use.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: April 14, 2009
    Assignee: Bayer Aktiengesellschaft
    Inventors: Ingmar Dorn, Burkhard Kohler
  • Publication number: 20090093071
    Abstract: A thermal treatment apparatus having a first light source emitting a first light having light diffusion property, a reflectance measuring unit irradiating a treatment target with the light from plural directions by the first light source and determining a light reflectance of the treatment target, a light irradiation controller adjusting an intensity of a second light of a second light source on the basis of the light reflectance, the second light has diffusion property, and a thermal treatment unit irradiating the treatment target with the second light having adjusted the intensity of the second light by the light irradiation controller.
    Type: Application
    Filed: October 6, 2008
    Publication date: April 9, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Tomohiro KUBO
  • Patent number: 7514940
    Abstract: A system and method are disclosed for determining the effective channel width (Weff) and the effective channel length (Leff) of metal oxide semiconductor devices. One advantageous embodiment of the method provides a plurality of metal oxide semiconductor field effect transistor capacitors in which each capacitor has a same value of drawn channel length but a different value of drawn channel width. A value of Fowler-Nordheim tunneling current is measured from each capacitor. Channel width offset is the difference between the drawn channel width and the effective channel width. A value of channel width offset is obtained from the measured values of the Fowler-Nordheim tunneling currents and used to determine the value of effective channel width. A similar method is used to determine the value of the effective channel length.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: April 7, 2009
    Assignee: National Semiconductor Corporation
    Inventor: Jiankang Bu
  • Patent number: 7514277
    Abstract: An etching method capable of controlling the film thickness of a hard mask layer uniformly is provided. A plasma etching is performed on a native oxide film by using an etching gas containing, for example, CF4 and Ar while a thickness of a silicon nitride film is being monitored and the etching is finished when the thickness of the silicon nitride film reaches a predetermined value. Then, a plasma etching is performed on a silicon substrate by employing an etching gas containing, for example, Cl2, HBr and Ar and using the silicon nitride film as a mask while a depth of a trench is being monitored and the etching is finished when the depth of the trench reaches a specified value.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: April 7, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Susumu Saito, Akitaka Shimizu
  • Publication number: 20090087928
    Abstract: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventors: Jay Sanford Burnham, Joseph Kerry Vaughn Comeau, Leslie Peter Crane, James Randall Elliott, Scott Alan Estes, James Spiros Nakos, Eric Jeffrey White
  • Publication number: 20090081813
    Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on the substrate, each diffraction mirror array of the set of at least three diffraction mirror arrays comprising a single row of mirrors, all mirrors in any particular diffraction mirror array spaced apart a same distance, mirrors in different diffraction mirror arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Inventors: Axel Aguado Granados, Benjamin Aaron Fox, Nathaniel James Gibbs, Andrew Benson Maki, Trevor Joseph Timpane
  • Publication number: 20090081814
    Abstract: An integrated manufacturing system comprising: providing a substrate; forming a gate over the substrate; measuring a gate length of the gate; forming a first spacer adjacent the gate; measuring a spacer critical dimension of the spacer; and adjusting a dose of an implant based on the gate length and the spacer critical dimension for a source/drain region.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Ming Lei, Ricky Seet, Young Tai Kim, Lieyong Yang, Chee Kong Leong, Sean Lian
  • Publication number: 20090075402
    Abstract: A method, system or the like which may, for example, be exploited as part of known methods, systems and/or apparatii which manipulate (i.e. tune, modify, change, create, etc.) the impedance of (integrated) semiconductor components or devices by exploiting a focused heating source. The method, system or the like exploits in situ optical measurements for the modification of the energy output of a focused heating source, such as for example of a (pulsed) laser heat source. The energy input to the focused heating source may be manipulated as a function of an optical measurement so as to obtain a desired or necessary energy output (e.g. target energy output) from the focused heating source.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 19, 2009
    Inventors: Michel Meunier, Stephane Laforte
  • Publication number: 20090072144
    Abstract: Exemplary embodiments provide an infrared (IR) retinal system and method for making and using the IR retinal system. The IR retinal system can include adaptive sensor elements, whose properties including, e.g., spectral response, signal-to-noise ratio, polarization, or amplitude can be tailored at pixel level by changing the applied bias voltage across the detector. “Color” imagery can be obtained from the IR retinal system by using a single focal plane array. The IR sensor elements can be spectrally, spatially and temporally adaptive using quantum-confined transitions in nanoscale quantum dots. The IR sensor elements can be used as building blocks of an infrared retina, similar to cones of human retina, and can be designed to work in the long-wave infrared portion of the electromagnetic spectrum ranging from about 8 ?m to about 12 ?m as well as the mid-wave portion ranging from about 3 ?m to about 5 ?m.
    Type: Application
    Filed: August 1, 2008
    Publication date: March 19, 2009
    Inventors: Sanjay Krishna, Majeed M. Hayat, J. Scott Tyo, Woo-Yong Jang
  • Publication number: 20090075403
    Abstract: The present invention relates to monitoring chemicals in a process chamber using a spectrometer having a plasma generator, based on patterns over time of chemical consumption. The relevant patterns may include a change in consumption, reaching a consumption plateau, absence of consumption, or presence of consumption. In some embodiments, advancing to a next step in forming structures on the workpiece depends on the pattern of consumption meeting a process criteria. In other embodiments, a processing time standard is established, based on analysis of the relevant patterns. Yet other embodiments relate to controlling work on a workpiece, based on analysis of the relevant patterns. The invention may be either a process or a device including logic and resources to carry out a process.
    Type: Application
    Filed: November 24, 2008
    Publication date: March 19, 2009
    Applicant: Lightwind Corporation
    Inventors: Gary B. Powell, Herbert E. Litvak
  • Patent number: 7498106
    Abstract: A method for controlling etch processes during fabrication of semiconductor devices comprises tests and measurements performed on non-product and product substrates to define an N-parameter CD control graph that is used to calculate a process time for trimming a patterned mask to a pre-determined width. An apparatus for performing such a method.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: March 3, 2009
    Assignee: Applied Materials, Inc.
    Inventors: David S L Mui, Wei Liu, Hiroki Sasano
  • Publication number: 20090053834
    Abstract: One embodiment of the present invention relates to a method of forming an integrated circuit, comprising forming an STI structure in a semiconductor body, the STI structure having a divot characteristic, performing scatterometry on the STI structure and obtaining signature spectra associated therewith, and continuing fabrication of the integrated circuit when the obtained signature spectra satisfies a predetermined performance specification.
    Type: Application
    Filed: August 23, 2007
    Publication date: February 26, 2009
    Inventor: Vladimir Alexeevich Ukraintsev
  • Patent number: 7493713
    Abstract: An image sensor and related method of fabrication are disclosed. The image sensor comprises a plurality of photoelectric conversion regions disposed in a predetermined field of a semiconductor substrate, color filters arranged on the photoelectric conversion regions, and a reflection protection structure disposed between the photoelectric conversion regions and the color filters. The reflection protection structure comprises portions having different thicknesses in relation to the color filters.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: February 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Hoon Park
  • Publication number: 20090033362
    Abstract: In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 5, 2009
    Inventors: Dirk Manger, Stephan Wege, Rolf Weis, Christoph Noelscher
  • Publication number: 20090035878
    Abstract: There are provided a plasma doping method and apparatus which is excellent in a repeatability and a controllability of an implanting depth of an impurity to be introduced into a sample or a depth of an amorphous layer. A plasma doping method of generating a plasma in a vacuum chamber and colliding an ion in the plasma with a surface of a sample to modify a surface of a crystal sample to be amorphous, includes the steps of carrying out a plasma irradiation over a dummy sample to perform an amorphizing treatment together with a predetermined number of samples, irradiating a light on a surface of the dummy sample subjected to the plasma irradiation, thereby measuring an optical characteristic of the surface of the dummy sample, and controlling a condition for treating the sample in such a manner that the optical characteristic obtained at the measuring step has a desirable value.
    Type: Application
    Filed: March 30, 2006
    Publication date: February 5, 2009
    Inventors: Yuichiro Sasaki, Tomohiro Okumura, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno
  • Publication number: 20090035879
    Abstract: An object is to provide a laser dicing apparatus and a laser dicing method capable of speedily performing high-quality dicing without causing any working defect even in a case where wafers varying in thickness are supplied. The laser dicing apparatus is provided with a measuring device which measures thickness of a wafer W, a recording device which stores a database in which modified region forming conditions associated with different thicknesses of the wafer W are described, and a control device which controls the laser dicing apparatus by automatically selecting, from the database, on the basis of the thickness of the wafer measured by the measuring device, the modified region forming conditions corresponding to the measured thickness of the wafer W. The optimum modified region forming conditions are thereby automatically set, so that even in a case where wafers W differing in thickness are supplied, high-quality dicing can be speedily performed without causing a working defect.
    Type: Application
    Filed: September 26, 2006
    Publication date: February 5, 2009
    Applicant: TOKYO SEIMITSU CO., LTD.
    Inventor: Yasuyuki Sakaya
  • Publication number: 20090035880
    Abstract: There is disclosed a manufacturing method for exposure mask, which comprises acquiring a first information showing surface shape of surface of each of a plurality of mask substrates, and a second information showing the flatness of the surface of each of mask substrates before and after chucked on a mask stage of an exposure apparatus, forming a corresponding relation of each mask substrate, the first information and the second information, selecting the second information showing a desired flatness among the second information of the corresponding relation, and preparing another mask substrate having the same surface shape as the surface shape indicated by the first information in the corresponding relation with the selected second information, and forming a desired pattern on the above-mentioned another mask substrate.
    Type: Application
    Filed: September 19, 2008
    Publication date: February 5, 2009
    Inventor: Masamitsu Itoh
  • Patent number: 7482177
    Abstract: A method for manufacturing an optical device includes the steps of: forming a first multilayer film, including forming a first mirror above a substrate, forming an active layer above the first mirror, forming a second mirror above the active layer, forming a semiconductor layer on the second mirror, and forming a sacrificial layer on the semiconductor layer; conducting a first examination step of conducting a reflectance examination on the first multilayer film; forming a second multilayer film by removing the sacrificial layer from the first multilayer film; conducting a second examination step of conducting a reflection coefficient examination on the second multilayer film; and patterning the second multilayer film to form a surface-emitting laser section having the first mirror, the active layer and the second mirror, and a diode section having the semiconductor layer, wherein the sacrificial layer is formed to have an optical film thickness of an odd multiple of ?/4, where ? is a design wavelength of ligh
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: January 27, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Yasutaka Imai
  • Publication number: 20090020773
    Abstract: A method of manufacturing a semiconductor light emitting device. The method includes: mounting a semiconductor light emitting element on a flat substrate; covering the semiconductor light emitting element on the flat substrate by a cover layer in a domed shape to form a light emitting device, the cover layer including at least a phosphor layer and a coating resin layer that are laminated in order, so as to fill around the semiconductor light emitting element; measuring an emission condition of the light emitting device; and forming a convex lens unit on the outermost of the coating resin layer using a liquid droplet discharging apparatus to adjust an emission distribution of the light emitting device based on the measured emission condition.
    Type: Application
    Filed: May 16, 2008
    Publication date: January 22, 2009
    Inventors: Yuko NOMURA, Kenichi Mori, Isao Takasu, Keiji Sugi, Isao Amemiya, Miho Yoda
  • Publication number: 20090023229
    Abstract: A method for managing UV irradiation for curing a semiconductor substrate, includes: passing UV light through a transmission glass window provided in a chamber for curing a semiconductor substrate placed in the chamber; monitoring an illuminance upstream of the transmission glass window and an illuminance downstream of the transmission glass window; determining a timing and/or duration of cleaning of the transmission glass window, a timing of replacing the transmission glass window, a timing of replacing a UV lamp, and/or an output of the UV light based on the monitored illuminances.
    Type: Application
    Filed: July 19, 2007
    Publication date: January 22, 2009
    Applicant: ASM JAPAN K.K.
    Inventors: Kiyohiro MATSUSHITA, Kenichi KAGAMI
  • Publication number: 20090011524
    Abstract: In one disclosed embodiment, the present method for determining resist suitability for semiconductor wafer fabrication comprises forming a layer of resist over a semiconductor wafer, exposing the layer of resist to patterned radiation, and determining resist suitability by using a scatterometry process prior to developing a lithographic pattern on the layer of resist. In one embodiment, the semiconductor wafer is heated in a post exposure bake process after scatterometry is performed. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source in a lithographic process. In other embodiments, patterned radiation is provided by an electron beam, or ion beam, for example. In one embodiment, the present method determines out-gassing of a layer of resist during exposure to patterned radiation.
    Type: Application
    Filed: July 6, 2007
    Publication date: January 8, 2009
    Inventors: Thomas Wallow, Bruno M. LaFontaine
  • Publication number: 20090011525
    Abstract: An arithmetic processing part in a controller detects a position of a defect such as a chip or a crack that occurs at an outer periphery of a semiconductor wafer, and then a memory in the controller stores position information of the defect. The controller reads the position information of the defect through a network in each process. On the basis of this position information, the controller determines a direction of joining a dicing tape to the semiconductor wafer or a direction of separating a protective tape from a front face of the semiconductor wafer.
    Type: Application
    Filed: July 1, 2008
    Publication date: January 8, 2009
    Inventors: Masayuki Yamamoto, Satoshi Ikeda
  • Publication number: 20090004763
    Abstract: The present invention discloses a laser crystallization method and crystallization apparatus using a high-accuracy substrate height control mechanism. There is provided a laser crystallization method includes obtaining a first pulse laser beam having an inverse-peak-pattern light intensity distribution formed by a phase shifter, and irradiating a thin film disposed on a substrate with the first pulse laser beam, thereby melting and crystallizing the thin film, the method includes selecting a desired one of reflected light components of a second laser beam by using a polarizing element disposed on an optical path of the second laser beam when illuminating, with the second laser beam, an first pulse laser beam irradiation position of the thin film, correcting a height of the substrate to a predetermined height by detecting the selected reflected light component, and irradiating the first pulse laser beam to the thin film having the corrected height.
    Type: Application
    Filed: June 25, 2008
    Publication date: January 1, 2009
    Inventors: Takashi Ono, Masakiyo Matsumura, Kazurumi Azuma, Tomoya Kato
  • Publication number: 20080318345
    Abstract: An approach that determines an ion implantation processing characteristic in a plasma ion implantation of a substrate is described. In one embodiment, there is a light source configured to direct radiation onto the substrate. A detector is configured to measure radiation reflected from the substrate. A processor is configured to correlate the measured radiation reflected from the substrate to an ion implantation processing characteristic.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Inventors: Harold M. Persing, Vikram Singh, Edwin Arevalo
  • Publication number: 20080318346
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 25, 2008
    Inventors: Hiroshi Maki, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Publication number: 20080311686
    Abstract: A method of making a semiconductor thin film bonded to a handle substrate includes implanting a semiconductor substrate with a light ion species while cooling the semiconductor substrate, bonding the implanted semiconductor substrate to the handle substrate to form a bonded structure, and annealing the bonded structure, such that the semiconductor thin film is transferred from the semiconductor substrate to the handle substrate.
    Type: Application
    Filed: August 2, 2006
    Publication date: December 18, 2008
    Inventors: Anna Fontcuberta i Morral, Sean M. Olson
  • Publication number: 20080305561
    Abstract: Methods of manufacturing semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a method of forming a material layer. The method includes providing a semiconductor wafer, forming a first portion of a material layer over the semiconductor wafer at a first pressure, and forming a second portion of the material layer over the first portion of the material layer at a second pressure, the second pressure being less than the first pressure.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Inventor: Shrinivas Govindarajan
  • Publication number: 20080305562
    Abstract: A fixturing system and microscope/video camera setup enables an operator to manipulate a photodiode into position optically using known good targets for the X and Y location and using microscope focus/defocus/refocus for locating the active area of the avalanche photodiode exactly at the focal point of the lens.
    Type: Application
    Filed: June 11, 2007
    Publication date: December 11, 2008
    Inventor: David J. Savoia
  • Publication number: 20080293166
    Abstract: A solution to an interference effect problem associated with laser processing of target structures entails adjusting laser pulse energy or other laser beam parameter, such as laser pulse temporal shape, based on light reflection information of the target structure and passivation layers stacked across a wafer surface or among multiple wafers in a group of wafers. Laser beam reflection measurements on a target link measurement structure and in a neighboring passivation layer area unoccupied by a link enable calculation of the laser pulse energy adjustment for a more consistent processing result without causing damage to the wafer. For thin film trimming on a wafer, similar reflection measurement information of the laser beam incident on the thin film structure and the passivation layer structure with no thin film present can also deliver the needed information for laser parameter selection to ensure better processing quality.
    Type: Application
    Filed: May 25, 2007
    Publication date: November 27, 2008
    Applicant: Electro Scientific Industries, Inc.
    Inventors: Yunlong Sun, Steve Harris
  • Patent number: 7457736
    Abstract: An automated metrology recipe set up process is described for a manufacturing process, in which patterns to be formed on a device are defined using a design database. The design database is processed to produce a simulated image of a feature for use in a metrology tool for a measurement of the feature. The simulated image is supplied to the metrology tool, where it is used as a basis for alignment of the tool for the measurement. Other recipe data is combined with the simulated image to provide a fully automated metrology set up process.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: November 25, 2008
    Assignee: Synopsys, Inc.
    Inventor: Fang-Cheng Chang
  • Publication number: 20080286885
    Abstract: Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one lot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.
    Type: Application
    Filed: April 22, 2008
    Publication date: November 20, 2008
    Inventors: Pavel Izikson, John Robinson, Mike Adel, Amir Widmann, Dongsub Choi, Anat Marchelli
  • Patent number: 7449348
    Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: November 11, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Bhanwar Singh, Ramkumar Subramanian, Khoi A. Phan
  • Patent number: 7446868
    Abstract: The invention relates to a method and apparatus for detecting defects in a semiconductor or silicon structure at room temperature, and in an efficient time, using photoluminescence. The invention employs the use of a high intensity beam of light preferably having a spot size between 0.1 mm 0.5 microns and a peak or average power density of 104-109 w/cm2 with a view to generating a high concentration of charge carriers, which charge characters detect defects in a semiconductor by interacting with same. These defects are visible by producing a photoluminescence image of the semiconductor. Several wavelengths may be selected to identify defects at a selective depth as well as confocal optics may be used.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: November 4, 2008
    Assignee: Nanometrics Incorporated
    Inventors: Victor Higgs, Ian Mayes, Freddie Yun Heng Chin, Michael Sweeney
  • Publication number: 20080265244
    Abstract: A method is provided for fabricating a multilayer electronic device on a flexible substrate including at least a first and a second patterned layer, wherein the first patterned layer is defined with a linewidth that is smaller than the linewidth of the second patterned layer, and the second patterned layer is defined by a patterning technique which is capable of correcting for local distortions of the pattern of said first layer on top of the flexible substrate and wherein the first patterned layer is laid-out in such a way that the geometric overlap between a portion of the second layer and a portion of the first layer is insensitive against small variations of the position of the second patterned layer.
    Type: Application
    Filed: December 2, 2005
    Publication date: October 30, 2008
    Inventors: Henning Sirringhaus, Seamus Burns
  • Publication number: 20080261334
    Abstract: A method of processing semiconductor waters comprises forming a pattern of recesses in an exposed surface of each water in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is determined prior to the epitaxy step, then a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step is measured. A deviation between the dimension of the recessed test structure and the dimension of the epitaxial structure is determined and, from the deviation, the process temperature at which the epitaxy step was performed is determined. In case the deviation exceeds a predetermined limit, the temperature in the process chamber is adjusted for a subsequent lot of waters to be processed.
    Type: Application
    Filed: April 22, 2008
    Publication date: October 23, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gernot Biese, Ulrich Clement
  • Publication number: 20080254554
    Abstract: A method for producing an optical coupling element of the present invention includes the steps of: determining the mounting position of a light-emitting element and a light-receiving element on the front surface of the header portion of each lead frame based on the current amplification factor of the light-receiving element to be mounted; determining the bending angle of each header portion and a distance between the two elements after being bent by calculation such that a predetermined current transfer ratio and an internal insulation distance required by the optical coupling element to be produced are obtained; detecting the determined mounting position by detecting intersections of V-shaped grooves in a grid pattern formed on the front surface of each header portion; mounting each element onto the detected position of the front surface of each header portion while detecting the concave-convex shape; and bending each header portion after mounting each element at the bending angle determined by calculation.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 16, 2008
    Inventor: Takeshi KITAMURA
  • Publication number: 20080254553
    Abstract: Methods and systems for in situ process control, monitoring, optimization and fabrication of devices and components on semiconductor and related material substrates includes a light illumination system and electrical probe circuitry. The light illumination system may include a light source and detectors to measure optical properties of the in situ substrate while the electrical probe circuitry causes one or more process steps due to applied levels of voltage or current signals. The electrical probe circuitry may measure changes in electrical properties of the substrate due to the light illumination, the applied voltages and/or currents or other processes. The in situ process may be controlled on the basis of the optical and electrical measurements.
    Type: Application
    Filed: April 11, 2007
    Publication date: October 16, 2008
    Inventors: Woo Sik Yoo, Kitaek Kang
  • Publication number: 20080241972
    Abstract: A method of manufacturing a semiconductor device includes measuring a first width of a first mask pattern formed in a photomask and a second width of a second mask pattern formed in the photomask, and deciding a temperature of heat treatment of a thickening material over a resist film based on measured results.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Tomohiko YAMAMOTO
  • Publication number: 20080233661
    Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.
    Type: Application
    Filed: March 14, 2007
    Publication date: September 25, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tzu Lu, Hung Chang Hsieh, Kuei Shun Chen, Hsueh-Hung Fu, Ching-Hua Hsieh, Shau-Lin Shue
  • Patent number: 7427518
    Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: September 23, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Seiji Inumiya, Motoyuki Sato, Akio Kaneko, Kazuhiro Eguchi
  • Patent number: 7427764
    Abstract: A laser crystallization apparatus which capable of correcting both shift in imaging position caused by thermal lens effect of the imaging optical system and shift due to flatness of the substrate comprises an crystallization optical system which irradiates laser light to a thin film disposed on the substrate to melt and crystallize an irradiated region of the thin film, the apparatus includes a measurement light source which is disposed outside a light path of the laser light, and which emits measurement light being illuminated the irradiated region of the thin film, and a substrate height correction system which illuminates the thin film with the measurement light through an imaging optical system in the crystallization optical system, and which detects the reflected measurement light from the thin film.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: September 23, 2008
    Assignee: Advanced LCD Technologies DEvelopmet Center Co., Ltd.
    Inventor: Yoshio Takami