Abstract: Embodiments of the invention generally provide methods for end point detection at predetermined dopant concentrations during plasma doping processes. In one embodiment, a method includes positioning a substrate within a process chamber, generating a plasma above the substrate and transmitting a light generated by the plasma through the substrate, wherein the light enters the topside and exits the backside of the substrate, and receiving the light by a sensor positioned below the substrate. The method further provides generating a signal proportional to the light received by the sensor, implanting the substrate with a dopant during a doping process, generating multiple light signals proportional to a decreasing amount of the light received by the sensor during the doping process, generating an end point signal proportional to the light received by the sensor once the substrate has a final dopant concentration, and ceasing the doping process.

Abstract: Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.

Abstract: A method for manufacturing an optical device, the method includes the steps of: forming a multilayer film, including forming a first mirror above a substrate, forming an active layer above the first mirror, forming a second mirror above the active layer, forming a semiconductor layer on the second mirror, and forming a sacrificial layer on the semiconductor layer; conducting a reflection coefficient examination on the multilayer film; patterning the multilayer film to form a surface-emitting laser section having the first mirror, the active layer and the second mirror, and a diode section having the semiconductor layer; and removing at least a portion of the sacrificial layer to expose at least a portion of an upper surface of the semiconductor layer, wherein an optical film thickness of the semiconductor layer is formed to be an odd multiple or an even multiple of ?/4, where ? is a design wavelength of light emitted by the surface-emitting laser section, and an optical film thickness of the sacrificial layer

Abstract: An embodiment of the invention provides a laser annealing method, including the steps of radiating a laser beam to an amorphous film on a substrate while scanning the laser beam for the amorphous film, crystallizing the amorphous film, detecting a light quantity of laser beam reflected from the substrate and a scanning speed of the laser beam while the radiation and the scanning of the laser beam are carried out for the amorphous film, and controlling a radiation level and the scanning speed of the laser beam based on results of comparison of the light quantity of laser beam reflected from the substrate, and the scanning speed of the laser beam with respective preset references.

Abstract: When annealing of a semiconductor film is conducted using a plurality of lasers, each of the distances between laser irradiation regions is different. When a lithography step is conducted in accordance with a marker which is formed over a substrate in advance after the step, light-exposure is not correctly conducted to a portion crystallized by laser. By using a laser irradiation region obtained on a laser irradiation step as a marker, light-exposure is conducted by making a light-exposure position of a stepper coincide with a large grain size region in the laser irradiation region. A large grain size region and a poorly crystalline region are detected by utilizing a thing that scattering intensity of light is different between the large grain size region and the poorly crystalline region, thereby determining a light-exposure position.

Abstract: Disclosed herein is a method for manufacturing a feed thru for use in an electrolytic capacitor case. First, an electrode is inserted into a liquid injection mold. Liquid elastomer is then injected into the mold to surround a portion of the electrode. The elastomer is cured, and the resulting electrode and feed thru combination is inserted into a machined hole in a capacitor case. The machined hole may be located on either the base or the lid of the capacitor case. In other embodiments, a ferrule may also be placed in the liquid injection mold prior to injecting liquid elastomer. When a ferrule is used, the assembly may be welded into a machined hole in a capacitor case.

Abstract: Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web.

Abstract: Improved methods and apparatus for forming thin film layers of chalcogenide on a substrate web. According to the present teachings, a feedback control system may be employed to measure one or more properties of the web and/or the chalcogenide layer, and to adjust one or more parameters of the system or buffer layer deposition method in response to the measurement.

Abstract: Methods of forming a light emitting device include selectively forming a wavelength conversion structure on a light emitting element using stereolithography. Selectively forming the wavelength conversion structure may include covering the light emitting element with a photo-curable liquid polymer containing a luminescent material, and exposing the liquid polymer to light for a time sufficient to at least partially cure the liquid polymer. Multiple layers of polymer can be selectively built up to form a wavelength conversion structure having a custom shape on the light emitting element.

Abstract: A microelectromechanical device and method of fabricating the same, including a layer of patterned and deposited metal or mechanical-quality, doped polysilicon inserted between the appropriate device element layers, which provides a conductive layer to prevent the microelectromechanical device's output from drifting. The conductive layer may encapsulate of the device's sensing or active elements, or may selectively cover only certain of the device's elements. Further, coupling the metal or mechanical-quality, doped polysilicon to the same voltage source as the device's substrate contact may place the conductive layer at the voltage of the substrate, which may function as a Faraday shield, attracting undesired, migrating ions from interfering with the output of the device.

Abstract: A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.

Abstract: A silicon substrate processing method for reducing the thickness of an area of a silicon substrate on which a metal layer is formed to implement a semiconductor integrated circuit is disclosed. The method includes: (A) a process which evenly reduces the thickness of the backside of a silicon substrate to an extent where mechanical strength is maintained and the metal layer on the silicon substrate remains intact; (B) a process which detects defects from the backside of the silicon substrate after the process (A); (C) a process which further reduces the thickness of a defect-containing area of the silicon substrate by processing the backside of the silicon substrate; and (D) a process which measures the thickness of the area of the silicon substrate which is reduced in the process (C).

Abstract: The invention includes a lithographic system having a first source for generating radiation with a first wavelength and an alignment system with a second source for generating radiation with a second wavelength. The second wavelength is larger than the first wavelength. A marker structure is provided having a first layer and a second layer. The second layer is present either directly or indirectly on top of said first layer. The first layer has a first periodic structure and the second layer has a second periodic structure. At least one of the periodic structures has a plurality of features in at least one direction with a dimension smaller than 400 nm. Additionally, a combination of the first and second periodic structure forms a diffractive structure arranged to be illuminated by radiation with the second wavelength.

Abstract: A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.

Abstract: Exemplary embodiments of the selective laser repair apparatus and method may allow the repair of metal bumps in a semiconductor device stack by applying a laser beam to a damaged and/or defective bump. Metal bumps may be repaired and individual chips and/or packages forming a device stack need not be separated. The operation of a control unit and a driving unit may position a laser unit such that a laser beam may be irradiated at the damaged and/or defective metal bump. An X-ray inspection unit may obtain information about the damaged and/or defective metal bump.

Abstract: An apparatus and method for preventing the peeling of electroplated metal from a wafer, is disclosed. The apparatus includes a seed layer detector system having a light source and a reflectivity detector. According to the method, the light source emits a beam of light onto a wafer and the reflectivity detector receives the light reflected from the wafer. The reflectivity of the wafer surface is measured to determine the presence or absence of a seed layer on the wafer, as well as whether the seed layer has a minimum thickness for optimum electroplating of a metal onto the seed layer.

Abstract: A surface emitting laser which is configured by laminating on a substrate a lower reflection mirror, an active layer, and an upper reflection mirror, which includes, in a light emitting section of the upper reflection mirror, a structure for controlling reflectance that is configured by a low reflectance region and a concave high reflectance region formed in the central portion of the low reflectance region, and which oscillates at a wavelength of ?, wherein the upper reflection mirror is configured by a multilayer film reflection mirror based on a laminated structure formed by laminating a plurality of layers, the multilayer film reflection mirror includes a phase adjusting layer which has an optical thickness in the range of ?/8 to 3?/8 inclusive in a light emitting peripheral portion on the multilayer film reflection mirror, and an absorption layer causing band-to-band absorption is provided in the phase adjusting layer.

Abstract: A surface emitting laser configured by laminating on a substrate a lower reflection mirror, an active layer and an upper reflection mirror includes, in a light emitting section of the upper reflection mirror, a structure for controlling reflectance that is configured by a low reflectance region and a convex high reflectance region formed in the central portion of the low reflectance region, and which oscillates at a wavelength of ?, wherein the upper reflection mirror is configured by a multilayer film reflection mirror based on a laminated structure formed by laminating a plurality of layers, and an absorption layer causing band-to-band absorption is provided in the laminated structure.

Abstract: A computer program product that determines a polishing endpoint includes obtaining spectra from different zones on a substrate during different times in a polishing sequence, matches the spectra with indexes in a library and uses the indexes to determining a polishing rate for each of the different zones from the indexes. An adjusted polishing rate can be determined for one of the zones, which causes the substrate to have a desired profile when the polishing end time is reached.

Abstract: During a plasma discharging process, a laser beam having a certain exciting wavelength is applied to a surface of a process substrate, so as to measure, using scattered light, an impurity density and a crystal state on the surface of the process substrate.

Abstract: By using powerful data analysis techniques, such as PCR, PLS, CLS and the like, in combination with measurement techniques providing structural information, gradually varying material characteristics may be determined during semiconductor fabrication, thereby also enabling the monitoring of complex manufacturing sequences. For instance, the material characteristics of sensitive dielectric materials, such as ULK material, may be detected, for instance with respect to an extension of a damage zone, in order to monitor the quality of metallization systems of sophisticated semiconductor devices. The inline measurement data may be obtained on the basis of infrared spectroscopy, for instance using FTIR and the like, which may even allow directly obtaining the measurement data at process chambers, substantially without affecting the overall process throughput.

Abstract: A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).

Abstract: A trench isolation method of a semiconductor device includes forming polishing prevention film patterns on a semiconductor substrate, etching the semiconductor device by using the polishing prevention film patterns as masks and forming trenches, and forming conformal insulation films on the semiconductor substrate and the polishing prevention film patterns by burying the trenches. The conformal insulation films are first polished using a first polishing pad by using a slurry including an abrasive having a polishing selection ratio with respect to the polishing prevention film patterns. The first polished conformal insulation films are second polished using a second polishing pad including an abrasive and by using the polishing prevention film patterns as polishing prevention films.

Abstract: A method for polishing a substrate having a metal film thereon is described. The substrate has metal interconnects formed from part of the metal film. The polishing method includes performing a first polishing process of removing the metal film, after the first polishing process, performing a second polishing process of removing the barrier film, after the second polishing process, performing a third polishing process of polishing the insulating film, during the second polishing process and the third polishing process, monitoring a polishing state of the substrate with an eddy current sensor, and terminating the third polishing process when an output signal of the eddy current sensor reaches a predetermined threshold.

Abstract: In one embodiment a method is provided for maintaining a substrate processing surface. The method generally includes performing a set of measurements on the substrate processing surface, wherein the set of measurements are taken using a displacement sensor coupled to a processing surface conditioning arm, determining a processing surface profile based on the set of measurements, comparing the processing surface profile to a minimum profile threshold, and communicating a result of the profile comparison.

Abstract: A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface of the work under the conditions causing a multiple photon absorption and with a condensed point aligned to the inside of the work, and a modified area is formed inside the work along the predetermined determined cut line by moving the condensed point along the predetermined cut line, whereby the work can be cut with a rather small force by cracking the work along the predetermined cut line starting from the modified area and, because the pulse laser beam radiated is not almost absorbed onto the surface of the work, the surface is not fused even if the modified area is formed.

Abstract: An exposure apparatus including a projection optical system for projecting a pattern of a reticle onto a plate to be exposed, via a liquid that is filled in a space between the projection optical system and the plate, a supply pipe for supplying the liquid to the space between a final surface in the projection optical system and the plate, a recovery pipe for recovering the liquid from the space between the final surface in the projection optical system and the plate, and a measuring apparatus for measuring a refractive index of the liquid. The measuring apparatus includes (i) a cell for accommodating the liquid and transmitting light, wherein the cell is connected to one of the supply pipe and the recovery pipe, and (ii) a detector for detecting an incident position of the light refracted by the liquid in the cell.

Abstract: An apparatus and a method for semiconductor wafer bonding provide in-situ and real time monitoring of semiconductor wafer bonding time. Deflection of the wafer edges during the last phase of the direct bonding process indicates the end of the bonding process. The apparatus utilizes a distance sensor to measure the deflection of the wafer edges and the bonding time is measured as the time between applying the force (bonding initiation) and completion of the bonding process. The bonding time is used as a real-time quality control parameter for the wafer bonding process.

Abstract: An alignment method of chips that are formed on a surface of a semiconductor wafer with alignment marks corresponding to the chips includes the steps of irradiating an alignment mark corresponding to a predetermined alignment chip in a predetermined area including the chips with a laser light; detecting reflected waves from the alignment mark of the predetermined alignment chip to obtain a position of the alignment mark of the predetermined alignment chip; irradiating an alignment mark of an alternative chip different from the predetermined alignment chip with the laser light in case of not being able to obtain the position of the alignment mark of the predetermined alignment chip; obtaining a position of the alignment mark of the alternative chip by detecting the reflected waves from the alignment mark of the alternative chip; and aligning the chips in the predetermined area based on positions of alignment marks including the position of the alignment mark of the alternative chip.

Abstract: In a semiconductor manufacturing method, a metal film is formed on a substrate and heat treated. The relationship between substrate warping and the heat treatment temperature during suicide formation is acquired (S1). A silicide film is formed by forming a metal film on a substrate and heat treating, including substrate measurement during heat treatment (S2). The relationship between substrate warping at heat treatment temperature is determined from the relationship between the warping of the substrate and the temperature for heat treatment and the temperature for heat treatment carried out on the substrate when the warping of the substrate is measured. The difference between found warping and the measured warping is calculated (S4). Whether the difference exceeds a predetermined value is determined (S5). If the difference exceeds a predetermined value, heat treatment conditions are adjusted (S8), but they not adjusted if the difference is no greater than the predetermined value.

Abstract: A method and apparatus for igniting a gas mixture into plasma using capacitive coupling techniques, shielding the plasma and other contents of the plasma reactor from the capacitively-coupled electric field, and maintaining the plasma using inductive coupling are provided. For some embodiments, the amount of capacitive coupling may be controlled after ignition of the plasma. Such techniques are employed in an effort to prevent damage to the surface of a substrate from excessive ion bombardment caused by the highly energized ions and electrons accelerated towards and perpendicular to the substrate surface by the electric field of capacitively-coupled plasma.

Abstract: A method of processing semiconductor wafers comprises forming a pattern of recesses in an exposed surface of each wafer in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is determined prior to the epitaxy step, then a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step is measured. A deviation between the dimension of the recessed test structure and the dimension of the epitaxial structure is determined and, from the deviation, the process temperature at which the epitaxy step was performed is determined. In case the deviation exceeds a predetermined limit, the temperature in the process chamber is adjusted for a subsequent lot of wafers to be processed.

Abstract: The aim of the invention is to create a simple monitoring or testing method for monitoring a reduction in thickness as material is removed from a bonded semiconductor wafer pair, which prevents failure effects as material is removed from wafers (polishing, grinding or lapping). In addition, the costs of the material removal process should be reduced by minimizing the complexity of monitoring, as well as by reducing the amount of resulting refuse. To this end, the invention provides a test structure (4, 5, 6, 7, 8, 9) comprised of a systematic row of a number of different depth trenches that are made in the (active) wafer (2). A thickness (h6; h7) of the active wafer (2) desired during material removal, particularly during a polishing, corresponds to the depth (t6; t7) of a reference trench (6; 7) of the trenches of the test structure, said reference trench (6) being surrounded by flatter and deeper trenches (5, 7).

Abstract: Methods of manufacturing a semiconductor device and an apparatus for the manufacturing of semiconductor devices are provided. An embodiment regards providing a process which changes the volume of at least one layer of a semiconductor substrate or of at least one layer deposited on the semiconductor substrate, and measuring a change in volume of such at least one layer using fluorescence. In another embodiment, a change in volume of such at least one layer is measured using reflection of electromagnetic waves.

Abstract: The present invention is a method for producing a bonded wafer, comprising at least: bonding a base wafer serving as a support substrate to a bond wafer made of a silicon single crystal via an insulator film or directly bonding the wafers to provide a bonded wafer; and reducing a thickness of the bond wafer to form a thin film made of the silicon single crystal on the base wafer, wherein the thickness of the bonded wafer is reduced based on at least surface grinding while measuring the thickness of the bond wafer, and surface grinding with respect to the bond wafer is stopped when the thickness of the bond wafer reaches a target thickness. As a result, the method for producing a bonded wafer enabling a silicon single crystal thin film to precisely have a desired film thickness, a bonded wafer, and a surface grinding machine enabling a silicon single crystal thin film to precisely have a desired film thickness are provided.

Abstract: It is intended to provide a plasma doping method and apparatus which are superior in the controllability of the concentration of an impurity that is introduced into a surface layer of a sample. A prescribed gas is introduced into a vacuum container 1 from a gas supply apparatus 2 while being exhausted by a turbomolecular pump 3 as an exhaust apparatus. The pressure in the vacuum container 1 is kept at a prescribed value by a pressure regulating valve 4. High-frequency electric power of 13.56 MHz is supplied from a high-frequency power source 5 to a coil 8 disposed close to a dielectric window 7 which is opposed to a sample electrode 6, whereby induction-coupled plasma is generated in the vacuum container 1. A high-frequency power source 10 for supplying high-frequency electric power to the sample electrode 6 is provided. Every time a prescribed number of samples have been processed, a dummy sample is subjected to plasma doping and then to heating.

Abstract: Embodiments of the invention generally provide methods for end point detection at predetermined dopant concentrations during plasma doping processes. In one embodiment, a method includes positioning a substrate within a process chamber, generating a plasma above the substrate and transmitting a light generated by the plasma through the substrate, wherein the light enters the topside and exits the backside of the substrate, and receiving the light by a sensor positioned below the substrate. The method further provides generating a signal proportional to the light received by the sensor, implanting the substrate with a dopant during a doping process, generating multiple light signals proportional to a decreasing amount of the light received by the sensor during the doping process, generating an end point signal proportional to the light received by the sensor once the substrate has a final dopant concentration, and ceasing the doping process.

Abstract: An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate layer, an anti-reflection film and an upper layer resist film are formed on the conductive film. A focal point at a time of exposure is detected by detecting a height of the upper layer resist film. In detecting the focal point at the time of exposure, a focal point detection light is radiated on the upper layer resist film. After detecting the focal point, the upper layer resist film is exposed and developed thereby to form a resist pattern. With the resist pattern as a mask, the intermediate layer and the anti-reflection film are patterned, and the lower layer resist film is developed. With these patterns as a mask, the conductive film is etched thereby to form a gate electrode.

Abstract: This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light from top of the wafer.

Abstract: A cubic element of photonic crystal is integrally formed on the surface of a photo-detection element, and a portion of the photonic crystal cubic element is irradiated with ultraviolet rays thereby to change the refractive index of the portion of the cubic element that has been irradiated with ultraviolet rays. Alternatively, by causing globular particles having different refractive indices to eject on the surface of the photo-detection element from an ink-jet apparatus having a nozzle provided with a temperature control part by controlling temperature of the nozzle to form a laminate of globular particle layers having different refractive indices, a photonic crystal lens is integrally formed on the surface of the photo-detection element.

Abstract: The method for measuring the porosity of an element is performed by means of a measuring device comprising a measuring chamber in which the element is disposed, a solvent tank associated with an adsorption valve, and a pump associated with a desorption valve. The measuring method comprises measurement of the pressure in the chamber by means of a pressure sensor, and a cycle for measuring the porosity by ellipsometry at different predetermined pressure. During this measuring cycle, a pressure controller controls opening of the adsorption and desorption valves according to the measured pressure. The relative pressure in the chamber is successively regulated at different predetermined values, while maintaining a continuous flow of solvent in the chamber between the tank and the pump.

Abstract: In semiconductor processing, the critical dimensions of structures formed on a wafer are controlled by first developing photoresist on top of a film layer on a wafer using a developer tool, the photoresist development being a function of developer tool process variables including temperature and length of time of development. After developing the photoresist, one or more etching steps are performed on the film layer on the wafer using an etch tool. After the one or more etching steps are performed, critical dimensions of structures at a plurality of locations on the wafer are measured using an optical metrology tool. After the critical dimensions are measured, one or more of the developer tool process variables are adjusted based on the critical dimensions of structures measured at the plurality of locations on the wafer.

Abstract: A photovoltaic device having a high conversion efficiency is produced in a stable manner. The conditions for film deposition of a microcrystalline silicon photovoltaic layer (4) in a photovoltaic device are set based on the Raman peak ratio within a Raman spectrum obtained at the substrate (1) side of the microcrystalline silicon layer (4), and the Raman peak ratio within a Raman spectrum obtained at the opposite side to the substrate (1).

Abstract: A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is forcibly brought into a state free from undulation by the suction to the supporting face (11a), so that the rear face (1b) becomes a reference face for planarization of a front face (1a). In this state, a tool (10) is used to cut surface layers of Au projections (2) and a resist mask (12) on the front face (1a), thereby planarizing the Au projections (2) and the resist mask (12) so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.

Abstract: A manufacturing method of a CMOS image sensor including at least one of the following steps. Forming an under-structure including a photodiode, a metal wire, and an interlayer insulation film for insulation between a metal pad and the metal wire. Forming a passivation layer on and/or over the under-structure. Selectively etching the passivation layer and the interlayer insulation film below the passivation layer to form a color filter region and a metal pad exposure region. Simultaneously etching the color filter region and the metal pad exposure region. Sequentially forming a plurality of color filters and a plurality of micro lenses on the interlayer insulation film etched to form the color filters.

Abstract: Methods are disclosed including applying a layer of binder material onto an LED structure. A luminescent solution including an optical material suspended in a solution is atomized using a flow of pressurized gas, and the atomized luminescent solution is sprayed onto the LED structure including the layer of binder material using the flow of pressurized gas.

Abstract: Processes and apparatuses are disclosed for detecting and characterizing SiCOH-based dielectric materials during integrated circuit fabrication. The processes generally include chromatographically analyzing a fluid stream generated during a process employed for device fabrication, e.g., during a wet strip, a chemical mechanical planarization process and the like.

Abstract: A method for semiconductor processing is provided, wherein a semiconductor wafer having undergone polishing is provided. The semiconductor wafer has an active region positioned between one or more moat regions, wherein the one or more moat regions have an oxide disposed therein. A top surface of the active region is recessed from a top surface of the moat region, therein defining a step having a step height associated therewith. A step height is measured, and a photoresist is formed over the semiconductor wafer. A modeled step height is further determined, wherein the modeled step height is based on the measured step height and a desired critical dimension of the photoresist. A dosage of energy is determined for patterning the photoresist, wherein the determination of the dosage of energy is based, at least in part, on the modeled step height. The photoresist is then patterned using the determined dosage of energy.

Abstract: A method for detecting semiconductor-manufacturing conditions includes providing a photomask with a plurality of pattern areas each having a plurality of test lines with different pitches, exposing a plurality of wafer with the photomask in different manufacturing conditions, measuring the critical dimensions of the plurality of pattern areas, generating a library of relationships between the pitches and the critical dimension of the pattern areas, exposing a test wafer in an unknown manufacturing condition, finding out a relationships between the pitches and the critical dimension of the pattern areas of the test wafer, searching for a most similar relationship in the library, and detecting a set of manufacturing parameters used to expose the test wafer.

Abstract: A method for determining conditions for forming a dielectric SiOCH film, includes: (i) forming a dielectric SiOCH film on a substrate under conditions; (ii) evaluating the conditions using a ratio of Si—CH3 bonding strength to Si—O bonding strength of the film as formed in step (i); (iii) if the ratio is 2.50 % or higher, confirming the conditions, and if the ratio is less than 2.50 %, changing the conditions by changing at least one of the susceptor temperature, the distance between upper and lower electrodes, the RF power, and the curing time; and (iv) repeating steps (i) to (iii) until the ratio is 2.50 % or higher.