Heterojunction Patents (Class 438/94)
  • Patent number: 9741901
    Abstract: Two-terminal electronic devices, such as photodetectors, photovoltaic devices and electroluminescent devices, are provided. The devices include a first electrode residing on a substrate, wherein the first electrode comprises a layer of metal; an I-layer comprising an inorganic insulating or broad band semiconducting material residing on top of the first electrode, and aligned with the first electrode, wherein the inorganic insulating or broad band semiconducting material is a compound of the metal of the first electrode; a semiconductor layer, preferably comprising a p-type semiconductor, residing over the I-layer; and a second electrode residing over the semiconductor layer, the electrode comprising a layer of a conductive material. The band gap of the material of the semiconductor layer, is preferably smaller than the band gap of the I-layer material. The band gap of the material of the I-layer is preferably greater than 2.5 eV.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: August 22, 2017
    Assignee: CBRITE Inc.
    Inventors: Gang Yu, Chan-Long Shieh, Zhao Chen
  • Patent number: 9691921
    Abstract: Embodiments of the invention generally relate to device fabrication of thin films used as solar devices or other electronic devices, and include textured back reflectors utilized in solar applications. In one embodiment, a method for forming a textured metallic back reflector which includes depositing a metallic layer on a gallium arsenide material within a thin film stack, forming an array of metallic islands from the metallic layer during an annealing process, removing or etching material from the gallium arsenide material to form apertures between the metallic islands, and depositing a metallic reflector layer to fill the apertures and cover the metallic islands.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: June 27, 2017
    Assignee: ALTA DEVICES, INC.
    Inventors: Harry Atwater, Brendan Kayes, Isik C. Kizilyalli, Hui Nie
  • Patent number: 9520530
    Abstract: A method includes: forming a buffer layer over an absorber layer of a photovoltaic device; and extrinsically doping the buffer layer after the forming step.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: December 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jyh-Lih Wu
  • Patent number: 9514936
    Abstract: Manufacturing a particle may include inserting a supporting body into a receiving groove on a first substrate to accommodate a first surface of the supporting body into the receiving groove and to expose a second surface of the supporting body to outside; forming a first coating layer on the second surface; attaching a second substrate to the supporting body on which the first coating layer is formed; exposing the first surface of the supporting body on which the first coating layer is formed to outside, by separating the supporting body on which the first coating layer is formed and which is attached to the second substrate from the first substrate; forming a second coating layer on the first surface of the supporting body; and separating the supporting body, on which the first coating layer and the second coating layer are formed, from the second substrate.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: December 6, 2016
    Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION SOGANG UNIVERSITY
    Inventors: Kyung Byung Yoon, Phil Kook Son, Hye Ryeong Park
  • Patent number: 9476143
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: October 25, 2016
    Assignee: IMEC
    Inventors: Benjamin Vincent, Voon Yew Thean, Liesbeth Witters
  • Patent number: 9209325
    Abstract: A method for forming contacts on a photovoltaic device includes forming a heterojunction cell including a substrate, a passivation layer and a doped layer and forming a transparent conductor on the cell. A patterned barrier layer is formed on the transparent conductor and has openings therein wherein the transparent conductor is exposed through the openings in the barrier layer. A conductive contact is grown through the openings in the patterned barrier layer by a selective plating process.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: December 8, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Warren S. Rieutort-Louis
  • Patent number: 9153730
    Abstract: A method of doping solar cell front contact can improve the efficiency of CdTe-based or other kinds of solar cells.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: October 6, 2015
    Assignee: First Solar, Inc.
    Inventors: Benyamin Buller, Markus Gloeckler, Rui Shao
  • Patent number: 9147792
    Abstract: A method of manufacturing a photovoltaic device including depositing a cadmium telluride layer onto a substrate; treating the cadmium telluride layer with a compound comprising chlorine and an element from Groups 1-11, zinc, mercury, or copernicium or a combination thereof; and annealing the cadmium telluride layer. A chloride-treated photovoltaic device.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: September 29, 2015
    Assignee: First Solar, Inc.
    Inventors: Scott Christensen, Rick C. Powell, Gang Xiong
  • Patent number: 9129808
    Abstract: Provided are an epitaxial wafer, a photodiode, and the like that include an antimony-containing layer and can be efficiently produced such that protruding surface defects causing a decrease in the yield can be reduced and impurity contamination causing degradation of the performance can be suppressed. The production method includes a step of growing an antimony (Sb)-containing layer on a substrate 1 by metal-organic vapor phase epitaxy using only metal-organic sources; and a step of growing, on the antimony-containing layer, an antimony-free layer including a window layer 5, wherein, from the growth of the antimony-containing layer to completion of the growth of the window layer, the growth is performed at a growth temperature of 425° C. or more and 525° C. or less.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: September 8, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Katsushi Akita, Takashi Ishizuka
  • Patent number: 9087941
    Abstract: A method for forming contacts on a photovoltaic device includes forming a heterojunction cell including a substrate, a passivation layer and a doped layer and forming a transparent conductor on the cell. A patterned barrier layer is formed on the transparent conductor and has openings therein wherein the transparent conductor is exposed through the openings in the barrier layer. A conductive contact is grown through the openings in the patterned barrier layer by a selective plating process.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Warren S. Rieutort-Louis
  • Patent number: 9040955
    Abstract: Provided are a semiconductor device and an optical sensor device, each having reduced dark current, and detectivity extended toward longer wavelengths in the near-infrared. Further, a method for manufacturing the semiconductor device is provided. The semiconductor device 50 includes an absorption layer 3 of a type II (GaAsSb/InGaAs) MQW structure located on an InP substrate 1, and an InP contact layer 5 located on the MQW structure. In the MQW structure, a composition x (%) of GaAsSb is not smaller than 44%, a thickness z (nm) thereof is not smaller than 3 nm, and z??0.4x+24.6 is satisfied.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: May 26, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei Fujii, Katsushi Akita, Takashi Ishizuka, Hideaki Nakahata, Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai
  • Publication number: 20150136220
    Abstract: Conventionally, CdTe solar cells are grown in superstrate configuration where the light enters the photovoltaic device through a transparent substrate. Still, efficiencies of CdTe solar cells grown in substrate configuration have so far been considerably lower than those grown in superstrate configuration. This invention discloses a photovoltaic device (0) in substrate configuration and a process of making thereof with which efficiencies approaching those of superstrate devices can be reproducibly achieved. Furthermore, long term stability is expected to be better than in state of the art devices. This method is advantageous because the growth in substrate configuration offers several advantages like the growth on metal foils and a more precise control of the junction.
    Type: Application
    Filed: May 31, 2013
    Publication date: May 21, 2015
    Applicant: EMPA EIDG. MATERIALPRÜFUNGS-UND FORSCHUNGSANSTALT
    Inventors: Lukas Kranz, Christina Gretener, Julian Perrenoud, Stephan Buecheler, Ayodhya N. Tiwari
  • Publication number: 20150129838
    Abstract: Manipulation of the passivation ligands of colloidal quantum dots and use in QD electronics. A multi-step electrostatic process is described which creates bare QDs, followed by the formation of QD superlattice via electric and thermal stimulus. Colloidal QDs with original long ligands (i.e. oleic acid) are atomized, and loaded into a special designed tank to be washed, followed by another atomization step before entering the doping station. The final step is the deposition of bare QDs onto substrate and growth of QD superlattice. The method permits the formation of various photonic devices, such as single junction and tandem solar cells based on bare QD superlattice, photodetectors, and LEDs. The devices include a piezoelectric substrate with an electrode, and at least one layer of bare quantum dots comprising group IV-VI elements on the electrode, where the bare quantum dots have been stripped of outer-layer ligands.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: University of South Florida
    Inventors: Jason E. Lewis, Xiaomei Jiang
  • Patent number: 9023681
    Abstract: The present invention discloses a method of fabricating a heterojunction battery, comprising the steps of: depositing a first amorphous silicon intrinsic layer on the front of an n-type silicon wafer, wherein the n-type silicon wafer may be a monocrystal or polycrystal silicon wafer; depositing an amorphous silicon p layer on the first amorphous silicon intrinsic layer; depositing a first boron doped zinc oxide thin film on the amorphous silicon p layer; forming a back electrode and an Al-back surface field on the back of the n-type silicon wafer; and forming a positive electrode on the front of the silicon wafer. In addition, the present invention further discloses a method of fabricating a double-sided heterojunction battery. In the present invention, the boron doped zinc oxide is used as an anti-reflection film in place of an ITO thin film; due to the special nature, especially the light trapping effect of the boron doped zinc oxide, the boron doped zinc oxide can achieve good anti-reflection.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Chint Solar (Zhejiang) Co., Ltd.
    Inventors: Xinwei Niu, Cao Yu, Lan Ding, Junmei Rong, Shiyong Liu, Minghua Wang, Jinyan Hu, Weizhi Han, Yongmin Zhu, Hua Zhang, Tao Feng, Jianbo Jin, Zhanwei Qiu, Liyou Yang
  • Patent number: 9018517
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20150101665
    Abstract: A method for formulating a CIGS nanoparticle-based ink, which can be processed to form a thin film with a crack-free limit (CFL) of 500 nm or greater, comprises: dissolving or dispersing Cu(In,Ga)S2 and Cu(In,Ga)Se2 nanoparticles; mixing the nanoparticle solutions/dispersions and adding oleic acid to form an ink; depositing the ink on a substrate; annealing to remove the organic components of the ink formulation; forming a film with a CFL ?500 nm; and, repeating the deposition and annealing process to form a CIGS film having a thickness ?1 ?m. The film so produced may be incorporated into a thin film photovoltaic device.
    Type: Application
    Filed: October 13, 2014
    Publication date: April 16, 2015
    Inventors: Zugang Liu, Christopher Newman
  • Publication number: 20150101657
    Abstract: An improved multiple quantum well solar cell can be achieved by ensuring the bandgap of each quantum well thin layer is not uniform compared with other such layers. Gradation of the bandgap by varying the content of at least two group II to VI elements, and/or varying the thickness of consecutive quantum well layers, within consecutively formed quantum wells provides for an increase in absorption across a greater range of the available solar spectrum.
    Type: Application
    Filed: September 21, 2012
    Publication date: April 16, 2015
    Inventor: Satyanarayan Barik
  • Publication number: 20150083206
    Abstract: This invention relates to cells and devices for harvesting light. Specifically the cell comprises at least one electrode which comprises graphene or modified graphene and layer of a transition metal dichalcogenide in a vertical heterostructure. The cell may be part of a light harvesting device. The invention also relates to materials and methods for making such cells and devices.
    Type: Application
    Filed: March 22, 2013
    Publication date: March 26, 2015
    Applicant: THE UNIVERSITY OF MANCHESTER
    Inventors: Konstantin Novoselov, Liam Britnell
  • Patent number: 8987724
    Abstract: A photodiode including at least one active zone located between a first electrode and a second electrode, the active zone including elongated conducting or semiconducting elements extending between the electrodes and configured to promote collection and transport of charge carriers in the active zone.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: March 24, 2015
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, ISORG
    Inventor: Mohammed Benwadih
  • Patent number: 8987042
    Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° C. or less and having a contact resistance of less than 5×10?4 ohms-cm2.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: March 24, 2015
    Assignee: SolAero Technologies Corp.
    Inventors: Tansen Varghese, Arthur Cornfeld
  • Patent number: 8987028
    Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
  • Publication number: 20150075598
    Abstract: A method for forming contacts on a photovoltaic device includes forming a heterojunction cell including a substrate, a passivation layer and a doped layer and forming a transparent conductor on the cell. A patterned barrier layer is formed on the transparent conductor and has openings therein wherein the transparent conductor is exposed through the openings in the barrier layer. A conductive contact is grown through the openings in the patterned barrier layer by a selective plating process.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Warren S. Rieutort-Louis
  • Patent number: 8980681
    Abstract: The disclosure provides a method for fabricating a solar cell, including: providing a first substrate; forming a light absorption precursor layer on the first substrate; conducting a thermal process to the light absorption precursor layer to form a light absorption layer, wherein the light absorption layer includes a first light absorption layer and a second light absorption layer, and the first absorption layer is formed on the first substrate; forming a second substrate on the second light absorption layer; removing the first substrate to expose a surface of the first light absorption layer; forming a zinc sulfide (ZnS) layer on the surface of the first light absorption layer; and forming a transparent conducting oxide (TCO) layer on the zinc sulfide (ZnS) layer.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 17, 2015
    Assignee: Industrial Technology Research Institute
    Inventor: Wei-Tse Hsu
  • Patent number: 8980680
    Abstract: A method for fabricating a solar cell element, the method comprising a step (a) of preparing a laminate and a chamber, a step (b) of bringing the laminate into contact with the aqueous solution in such a manner that the second surface is immersed in the aqueous solution after the step (a); a step (c) of applying a voltage difference between an anode electrode and the laminate under an atmosphere of the inert gas to form a Zn layer on the second surface after the step (b); and a step (d) of exposing the Zn layer to oxygen so as to convert the Zn layer into a ZnO crystalline layer after the step (c).
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: March 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tomoyuki Komori, Tetsuya Asano
  • Patent number: 8980664
    Abstract: According to one embodiment, a method for fabricating a stacked nitride-compound semiconductor structure includes forming a first protection film on a second surface of a substrate, forming a first nitride-compound semiconductor layer on the first surface of the substrate, forming a second protection film on the first nitride-compound semiconductor layer, removing the first protection film to expose the second surface of the substrate, forming a second nitride-compound semiconductor layer on the second surface of the substrate, and removing the second protection film to expose the first surface of the second nitride-compound semiconductor layer.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Kai, Hideto Sugawara
  • Publication number: 20150072466
    Abstract: Methods for doping an absorbent layer of a p-n heterojunction in a thin film photovoltaic device are provided. The method can include depositing a window layer on a transparent substrate, where the window layer includes at least one dopant (e.g., copper). A p-n heterojunction can be formed on the window layer, with the p-n heterojunction including a photovoltaic material (e.g., cadmium telluride) in an absorber layer. The dopant can then be diffused from the window layer into the absorber layer (e.g., via annealing).
    Type: Application
    Filed: November 18, 2014
    Publication date: March 12, 2015
    Applicant: FIRST SOLAR, INC.
    Inventors: Scott Daniel Feldman-Peabody, Robert Dwayne Gossman
  • Publication number: 20150059837
    Abstract: A multijunction solar cell including a contact layer with sulfur passivation on the surface of the contact layer adjacent to the window layer overlying the top subcell of the solar cell. The passivation is performed by application of a solution of ammonium sulphide.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Emcore Solar Power, Inc.
    Inventor: Arthur Cornfeld
  • Publication number: 20150059832
    Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a final base substrate; providing a first engineered substrate comprising a first zipper layer and a first seed layer; providing a second substrate; transferring the first seed layer to the final base substrate; forming at least one first solar cell layer on the first seed layer after transferring the first seed layer to the final base substrate, thereby obtaining a first wafer structure; forming at least one second solar cell layer on the second substrate, thereby obtaining a second wafer structure; and bonding the first and the second wafer structure to each other.
    Type: Application
    Filed: March 13, 2013
    Publication date: March 5, 2015
    Applicant: SOITEC
    Inventors: Bruno Ghyselen, Chantal Arena, Frank Dimroth, Matthias Grave
  • Publication number: 20150053924
    Abstract: A SPAD-type photodiode has a semiconductor substrate with a light-receiving surface. A lattice formed of interlaced strips made of a first material covers the light receiving surface. The lattice includes lattice openings with lateral walls covered by a spacer made of a second material. Then first and second materials have different optical indices, and further each optical index is less than or equal to the substrate optical index. A pitch of the lattice is of the order of a magnitude of an operating wavelength of the photodiode. The first and second materials are transparent at that operating wavelength. The lattice is made of a conductive material electrically coupled to an electrical connection node (for example, a bias voltage node).
    Type: Application
    Filed: August 21, 2014
    Publication date: February 26, 2015
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Michel Marty, Laurent Frey, Sebastien Jouan, Salim Boutami
  • Publication number: 20150053267
    Abstract: A solar cell according to the disclosure includes a back electrode layer; and a light absorbing layer on the back electrode layer, wherein the light absorbing layer includes an undoped region and a doping region on the undoped region, and the doping region includes zinc. A method of fabricating a solar cell according to the disclosure includes forming a back electrode layer on a substrate; forming a preliminary light absorbing layer on the back electrode layer; forming a dopant supply layer on the preliminary light absorbing layer; and diffusing the dopant supply layer.
    Type: Application
    Filed: October 19, 2012
    Publication date: February 26, 2015
    Applicant: LG INNOTEK CO., LTD.
    Inventor: Chin Woo Lim
  • Patent number: 8963182
    Abstract: A light emitting assembly comprising a solid state device coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first, relatively shorter wavelength radiation, and a down-converting luminophoric medium arranged in receiving relationship to said first, relatively shorter wavelength radiation, and which in exposure to said first, relatively shorter wavelength radiation, is excited to responsively emit second, relatively longer wavelength radiation. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is down-converted to white light by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors in a polymeric matrix.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: February 24, 2015
    Assignee: Cree, Inc.
    Inventors: Bruce H. Baretz, Michael A. Tischler
  • Publication number: 20150047698
    Abstract: A photovoltaic cell comprises a protective layer, a substrate adjacent to the protective layer, and a barrier layer adjacent to the substrate. The protective layer can comprise niobium, or a metal carbide, metal boride, metal nitride, or metal silicide. The barrier layer can comprise an electrically conductive material. The photovoltaic cell further comprises an absorber layer adjacent to the barrier layer. The absorber layer in some cases comprises copper indium gallium di-selenide (CIGS). The photovoltaic cell further comprises an optically transparent window layer adjacent to the absorber layer, and an electrically non-conductive aluminum zinc oxide (AZO) layer adjacent to the window layer. A transparent oxide layer is disposed adjacent to the AZO layer.
    Type: Application
    Filed: January 16, 2013
    Publication date: February 19, 2015
    Inventor: Dennis R. Hollars
  • Publication number: 20150047704
    Abstract: Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of SixGe1?x passivated by amorphous SiyGe1?y:H.
    Type: Application
    Filed: September 29, 2014
    Publication date: February 19, 2015
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Publication number: 20150047699
    Abstract: A thin film photovoltaic device (100) with a tunable, minimally conductive buffer (128) layer is provided. The photovoltaic device (100) may include a back contact (150), a transparent front contact stack (120), and an absorber (140) positioned between the front contact stack (120) and the back contact (150). The front contact stack (120) may include a low resistivity transparent conductive oxide (TCO) layer (124) and a buffer layer (128) that is proximate to the absorber layer (140). The photovoltaic device (100) may also include a window layer (130) between the buffer layer (128) and the absorber (140). In some cases, the buffer layer (128) is minimally conductive, with its resistivity being tunable, and the buffer layer (128) may be formed as an alloy from a host oxide and a high-permittivity oxide. The high-permittivity oxide may further be chosen to have a bandgap greater than the host oxide.
    Type: Application
    Filed: February 5, 2013
    Publication date: February 19, 2015
    Inventors: Teresa M. Barnes, James Burst
  • Publication number: 20150040975
    Abstract: One embodiment of the present invention provides a heterojunction solar cell. The solar cell includes a metallurgical-grade Si (MG-Si) substrate, a layer of heavily doped crystalline-Si situated above the MG-Si substrate, a layer of lightly doped crystalline-Si situated above the heavily doped crystalline-Si layer, a backside ohmic-contact layer situated on the backside of the MG-Si substrate, a passivation layer situated above the heavily doped crystalline-Si layer, a layer of heavily doped amorphous Si (a-Si) situated above the passivation layer, a layer of transparent-conducting-oxide (TCO) situated above the heavily doped a-Si layer, and a front ohmic-contact electrode situated above the TCO layer.
    Type: Application
    Filed: October 27, 2014
    Publication date: February 12, 2015
    Inventors: Chentao Yu, Jiunn Benjamin Heng, Zheng Xu, Jianming Fu, Jianjun Liang
  • Publication number: 20150040970
    Abstract: An inline vacuum deposition system contains thermal source pairs configured in adjacent deposition zones. Dopant sources allow the electrical characteristics of the sequentially formed layers to be controlled for a preferred deposition growth profile.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 12, 2015
    Applicant: First Solar, Inc.
    Inventors: Raffi Garabedian, Roger Malik, Jeremy Theil, Jigish Trivedi, Ming Yu
  • Patent number: 8951827
    Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields and lower costs. Certain solar cells may further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: February 10, 2015
    Assignee: EpiWorks, Inc.
    Inventors: David Ahmari, Swee Lim, Shiva Rai, David Forbes
  • Publication number: 20150037926
    Abstract: Apparatuses and methods for synthesizing nanoscale materials are provided, including semiconductor nanowires. Precursor solutions include mixed reagent precursor solutions of metal and chalcogenide precursors and a catalyst, where such solutions are liquid at room temperature. The precursor solutions are mixed by dividing a solution flow into multiple paths and converging the paths to form a uniform solution. A thermally controlled reactor receives the uniform solution to form semiconductor nanowires. Various electronic, optical, and sensory devices may employ the semiconductor nanowires described herein, for example.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 5, 2015
    Inventors: Anthony C. Onicha, Louise E. Sinks, Stefanie L. Weber
  • Publication number: 20150034968
    Abstract: A photoelectric conversion element of an embodiment is a photoelectric conversion element which performs photoelectric conversion by receiving illumination light having n light emission peaks having a peak energy Ap (eV) (where 1?p?n and 2?n) of 1.59?Ap?3.26 and a full width at half maximum Fp (eV) (where 1?p?n and 2?n), wherein the photoelectric conversion element includes m photoelectric conversion layers having a band gap energy Bq (eV) (where 1?q?m and 2?m?n), and the m photoelectric conversion layers each satisfy the relationship of Ap?Fp<Bq?Ap with respect to any one of the n light emission peaks.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinji SAITO, Rei HASHIMOTO, Mizunori EZAKI, Shinya NUNOUE, Hironori ASAI
  • Publication number: 20150037925
    Abstract: A method of fabricating a superlattice structure requires that atoms of a first III-V semiconductor compound be introduced into a vacuum chamber such that the atoms are deposited uniformly on a substrate. Atoms of at least one additional III-V compound are also introduced such that the atoms of the two III-V compounds form a repeating superlattice structure of alternating thin layers. Atoms of a surfactant are also introduced into the vacuum chamber while the III-V semiconductor compounds are being introduced, or immediately thereafter, such that the surfactant atoms act to improve the quality of the resulting SL structure. The surfactant is preferably bismuth, and the III-V semiconductor compounds are preferably GaSb along with either InAs or InAsSb; atoms of each material are preferably introduced using molecular beam epitaxy. The resulting superlattice structure is suitably used to form at least a portion of an IR photodetector.
    Type: Application
    Filed: August 1, 2013
    Publication date: February 5, 2015
    Inventors: ALLAN EVANS, William Tennant, Andrew Hood
  • Publication number: 20150034159
    Abstract: A hole-blocking silicon/titanium-oxide heterojunction for silicon photovoltaic devices and methods of forming are disclosed. The electronic device includes at least two electrodes having a current path between the two electrodes. The electronic device also includes a heterojunction formed of a titanium-oxide layer deposited over a Si layer and being disposed in the current path. The heterojunction is configured to function as a hole blocker. The first electrode may be electrically coupled to the Si layer and a second electrode may be electrically coupled to the titanium-oxide layer. The device may also include a PN junction disposed in the Si layer, in the current path. The device may also include an electron-blocking heterojunction on silicon in the current path.
    Type: Application
    Filed: March 14, 2013
    Publication date: February 5, 2015
    Applicant: The Trustees of Princeton University
    Inventors: Sushobhan Avasthi, James C. Sturm, William E. McClain, Jeffrey Schwartz
  • Patent number: 8946863
    Abstract: An epitaxial substrate for electronic devices, in which current flows in a lateral direction and of which warpage configuration is properly controlled, and a method of producing the same. The epitaxial substrate for electronic devices is produced by forming a bonded substrate by bonding a low-resistance Si single crystal substrate and a high-resistance Si single crystal substrate together; forming a buffer as an insulating layer on a surface of the bonded substrate on the high-resistance Si single crystal substrate side; and producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate. The resistivity of the low-resistance Si single crystal substrate is 100 ?·cm or less, and the resistivity of the high-resistance Si single crystal substrate is 1000 ?·cm or more.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: February 3, 2015
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Ryo Sakamoto, Tomohiko Shibata
  • Patent number: 8945975
    Abstract: In some embodiments of the invention, a device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. The third semiconductor layer is disposed between the second semiconductor layer and the light emitting layer. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the third semiconductor layer is no more than 1%. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the second semiconductor layer is at least 1%. The third semiconductor layer is at least partially relaxed.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: February 3, 2015
    Assignees: Koninklijke Philips N.V., Philips Lumileds Lighting Company LLC
    Inventors: Andrew Y. Kim, Patrick N. Grillot
  • Publication number: 20150027372
    Abstract: A vapor deposition apparatus to form stacked thin films on discrete photovoltaic module substrates conveyed in a continuous non-stop manner through said apparatus is provided. The apparatus includes a first sublimation compartment positioned over a first deposition area of said apparatus and a second sublimation compartment positioned over a second deposition area of said apparatus. The first sublimation compartment is configured to heat a first source material therein to sublimate the first source material into first source material vapors. A movable first shutter plate within the first sublimation compartment is configured to control the flow rate of the first source material vapors therethrough. Similarly, the second sublimation compartment is configured to heat a second source material therein to sublimate the second source material into second source material vapors, and includes a movable first shutter plate configured to control the flow rate of the second source material vapors therethrough.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 29, 2015
    Applicant: First Solar, Inc.
    Inventor: Christopher Rathweg
  • Publication number: 20150020877
    Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects as well as Fabrication methods and structures for forming thin film back contact solar cells are described.
    Type: Application
    Filed: August 9, 2012
    Publication date: January 22, 2015
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Pawan Kapur, Karl-Josef Kramer, Virendra V. Rana, Sean Seutter, Anand Deshpande, Anthony Calcaterra, Gerry Olsen, Kamran Manteghi, Thom Stalcup, George D. Kamian, David Xuan-Qi Wang, Yen-Sheng Su, Michael Wingert
  • Publication number: 20150017755
    Abstract: A method for fabricating a Cu—In—Ga—Se film solar cell is provided. The method comprises: a) fabricating a molybdenum back electrode on a substrate; b) fabricating a Cu—In—Ga—Se absorbing layer on the molybdenum back electrode; c) performing an annealing; d) fabricating an In2Se3 or ZnS buffer layer on the Cu—In—Ga—Se absorbing layer; e) fabricating an intrinsic zinc oxide high impedance layer; f) fabricating an indium tin oxide film low impedance layer on the intrinsic zinc oxide high impedance layer; g) fabricating an aluminum electrode on the indium tin oxide film low impedance layer.
    Type: Application
    Filed: January 11, 2014
    Publication date: January 15, 2015
    Inventors: Liuyu Lin, Zhun Zhang
  • Patent number: 8933327
    Abstract: A conventional thin-film photoelectric converter using amorphous germanium or crystalline silicon as a photoelectric conversion layer is problematic in that light having a long wavelength of 1100 nm or more cannot be used for photoelectric conversion, and is inefficient. The problem is solved by a thin-film photoelectric converter including one or more photoelectric conversion units each having a photoelectric conversion layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer, wherein the photoelectric conversion layer of at least one photoelectric conversion unit includes an intrinsic or weak n-type crystalline germanium semiconductor, and the absorption coefficient of infrared-absorption peak at wave number of 935±5 cm?1 of the crystalline germanium semiconductor is less than 6000 cm?1.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: January 13, 2015
    Assignee: Kaneka Corporation
    Inventors: Toshiaki Sasaki, Naoki Kadota
  • Patent number: 8928036
    Abstract: A barrier infrared detector with absorber materials having selectable cutoff wavelengths and its method of manufacture is described. A GaInAsSb absorber layer may be grown on a GaSb substrate layer formed by mixing GaSb and InAsSb by an absorber mixing ratio. A GaAlAsSb barrier layer may then be grown on the barrier layer formed by mixing GaSb and AlSbAs by a barrier mixing ratio. The absorber mixing ratio may be selected to adjust a band gap of the absorber layer and thereby determine a cutoff wavelength for the barrier infrared detector. The absorber mixing ratio may vary along an absorber layer growth direction. Various contact layer architectures may be used. In addition, a top contact layer may be isolated into an array of elements electrically isolated as individual functional detectors that may be used in a detector array, imaging array, or focal plane array.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: January 6, 2015
    Assignee: California Institute of Technology
    Inventors: David Z. Ting, Cory J. Hill, Alexander Seibel, Sumith Y. Bandara, Sarath D. Gunapala
  • Publication number: 20150004743
    Abstract: A method to improve operation of a CdTe-based photovoltaic device is disclosed, the method comprising the steps of depositing a semiconductor absorber layer adjacent to a substrate, depositing a semiconductor buffer layer adjacent to the semiconductor layer, and annealing at least one of the semiconductor absorber layer and the semiconductor buffer layer with one of a laser and a flash lamp.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 1, 2015
    Inventors: Pratima Addepalli, Benyamin Buller, Markus Gloeckler, Akhlesh Gupta, David Hwang, Andrei Los, Rick Powell, Rui Shao, Gang Xiong, Ming Lun Yu, San Yu, Zhibo Zhao
  • Publication number: 20140373907
    Abstract: A four-junction quaternary compound solar cell and a method thereof are provided.
    Type: Application
    Filed: December 21, 2012
    Publication date: December 25, 2014
    Applicant: Xiamen Sanan Optoelectronics Technology Co., Ltd.
    Inventors: Jingfeng Bi, Guijiang Lin, Jianqing Liu, Weiping Xiong, Minghui Song, Liangjun Wang, Jie Ding, Zhidong Lin