Abstract: The present invention realizes a hole-selective film provided with both hole selectivity and passivation characteristics. This production method for a semiconductor device is provided with a step for forming a titanium oxide film on a crystalline silicon layer by means of a thermal atomic layer deposition method, and a step for carrying out a hydrogen plasma process on the titanium oxide film.

Abstract: Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.

Abstract: Provided is a semiconductor light receiving element which can achieve a high-speed operation without sacrificing light receiving sensitivity while increasing the margin of a manufacturing process. The semiconductor light receiving element according to the present invention is characterized by comprising: a semiconductor layer doped with a first impurity; a semiconductor light absorption layer in which a band gap energy is adjusted to absorb incident light on the semiconductor layer doped with the first impurity; a semiconductor layer on the semiconductor light absorption layer and doped with a second impurity; and a metal electrode contacting side surfaces of the semiconductor layer doped with the second impurity, wherein side surfaces of the metal electrode are surfaces parallel to a growth direction of the semiconductor layer doped with the second impurity.

Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

Abstract: Provided are opto-electronic devices with low dark noise and high signal-to-noise ratio and methods of manufacturing the same. An opto-electronic device may include: a semiconductor substrate; a light receiving unit formed in the semiconductor substrate; and a driving circuit arranged on a surface of the semiconductor substrate. The light receiving unit may include: a first semiconductor layer partially arranged in an upper region of the semiconductor substrate and doped with a first conductivity type impurity; a second semiconductor layer arranged on the first semiconductor layer and doped with a second conductivity type impurity; a transparent matrix layer arranged on an upper surface of the second semiconductor layer; a plurality of quantum dots arranged to contact the transparent matrix layer; and a first electrode and a second electrode electrically connected to the second semiconductor layer and respectively arranged on both sides of the transparent matrix layer.

Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar cells has a graded band gap throughout its thickness.

Abstract: Disclosed is a method of facilitating straining of a semiconductor element (331) for semiconductor fabrication. In a described embodiment, the method comprises: providing a base layer (320) with the semiconductor element (331) arranged on a first base portion (321) of the base layer (320), the semiconductor element (331) being subjected to a strain relating to a characteristic of the first base portion (321); and adjusting the characteristic of the first base portion (321) to facilitate straining of the semiconductor element (331).

Abstract: A micro light-emitting diode (micro-LED) chip adapted to emit a red light or an infrared light is provided. The micro-LED chip includes a GaAs epitaxial structure layer, a first electrode, and a second electrode. The GaAs epitaxial structure layer includes an N-type contact layer, a tunneling junction layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, and an N-type window layer along a stacking direction. The first electrode electrically contacts the N-type contact layer. The second electrode electrically contacts the N-type window layer.

Abstract: A solar battery device includes a semiconductor substrate and a covering part. The semiconductor substrate has a first semiconductor region and a second semiconductor region. The first semiconductor region is a first-conductivity-type semiconductor region located on a first surface of the semiconductor substrate. The second semiconductor region is a second-conductivity-type semiconductor region different from the first-conductivity-type and located on a second surface opposite from the first surface. The covering part is located on the first surface of the semiconductor substrate. The covering part has a laminated portion in which a plurality of layers including a passivation layer and an antireflection layer are present in a laminated state. In the laminated portion, the passivation layer includes a region in which a thickness decreases from an outer peripheral portion toward a central part of the first surface.

Abstract: A conductive ink may include a nickel component, a polycarboxylic acid component, and a polyol component, the polycarboxylic acid component and the polyol component being reactable to form a polyester component. The polyester component may be formed in situ in the conductive ink from a polyol component and a polycarboxylic acid component. The conductive ink may include a carbon component. The conductive ink may include an additive component. The conductive ink may include nickel flakes, graphene flakes, glutaric acid, and ethylene glycol. The conductive ink may be printed (e.g., screen printed) on a substrate and cured to form a conductive film. A conductive film may include a nickel component and a polyester component.

Abstract: Two-terminal electronic devices, such as photodetectors, photovoltaic devices and electroluminescent devices, are provided. The devices include a first electrode residing on a substrate, wherein the first electrode comprises a layer of metal; an I-layer comprising an inorganic insulating or broad band semiconducting material residing on top of the first electrode, and aligned with the first electrode, wherein the inorganic insulating or broad band semiconducting material is a compound of the metal of the first electrode; a semiconductor layer, preferably comprising a p-type semiconductor, residing over the I-layer; and a second electrode residing over the semiconductor layer, the electrode comprising a layer of a conductive material. The band gap of the material of the semiconductor layer, is preferably smaller than the band gap of the I-layer material. The band gap of the material of the I-layer is preferably greater than 2.5 eV.

Abstract: Embodiments of the invention generally relate to device fabrication of thin films used as solar devices or other electronic devices, and include textured back reflectors utilized in solar applications. In one embodiment, a method for forming a textured metallic back reflector which includes depositing a metallic layer on a gallium arsenide material within a thin film stack, forming an array of metallic islands from the metallic layer during an annealing process, removing or etching material from the gallium arsenide material to form apertures between the metallic islands, and depositing a metallic reflector layer to fill the apertures and cover the metallic islands.

Abstract: A method includes: forming a buffer layer over an absorber layer of a photovoltaic device; and extrinsically doping the buffer layer after the forming step.

Abstract: Manufacturing a particle may include inserting a supporting body into a receiving groove on a first substrate to accommodate a first surface of the supporting body into the receiving groove and to expose a second surface of the supporting body to outside; forming a first coating layer on the second surface; attaching a second substrate to the supporting body on which the first coating layer is formed; exposing the first surface of the supporting body on which the first coating layer is formed to outside, by separating the supporting body on which the first coating layer is formed and which is attached to the second substrate from the first substrate; forming a second coating layer on the first surface of the supporting body; and separating the supporting body, on which the first coating layer and the second coating layer are formed, from the second substrate.

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.

Abstract: A method for forming contacts on a photovoltaic device includes forming a heterojunction cell including a substrate, a passivation layer and a doped layer and forming a transparent conductor on the cell. A patterned barrier layer is formed on the transparent conductor and has openings therein wherein the transparent conductor is exposed through the openings in the barrier layer. A conductive contact is grown through the openings in the patterned barrier layer by a selective plating process.

Abstract: A method of doping solar cell front contact can improve the efficiency of CdTe-based or other kinds of solar cells.

Abstract: A method of manufacturing a photovoltaic device including depositing a cadmium telluride layer onto a substrate; treating the cadmium telluride layer with a compound comprising chlorine and an element from Groups 1-11, zinc, mercury, or copernicium or a combination thereof; and annealing the cadmium telluride layer. A chloride-treated photovoltaic device.

Abstract: Provided are an epitaxial wafer, a photodiode, and the like that include an antimony-containing layer and can be efficiently produced such that protruding surface defects causing a decrease in the yield can be reduced and impurity contamination causing degradation of the performance can be suppressed. The production method includes a step of growing an antimony (Sb)-containing layer on a substrate 1 by metal-organic vapor phase epitaxy using only metal-organic sources; and a step of growing, on the antimony-containing layer, an antimony-free layer including a window layer 5, wherein, from the growth of the antimony-containing layer to completion of the growth of the window layer, the growth is performed at a growth temperature of 425° C. or more and 525° C. or less.

Abstract: A method for forming contacts on a photovoltaic device includes forming a heterojunction cell including a substrate, a passivation layer and a doped layer and forming a transparent conductor on the cell. A patterned barrier layer is formed on the transparent conductor and has openings therein wherein the transparent conductor is exposed through the openings in the barrier layer. A conductive contact is grown through the openings in the patterned barrier layer by a selective plating process.

Abstract: Provided are a semiconductor device and an optical sensor device, each having reduced dark current, and detectivity extended toward longer wavelengths in the near-infrared. Further, a method for manufacturing the semiconductor device is provided. The semiconductor device 50 includes an absorption layer 3 of a type II (GaAsSb/InGaAs) MQW structure located on an InP substrate 1, and an InP contact layer 5 located on the MQW structure. In the MQW structure, a composition x (%) of GaAsSb is not smaller than 44%, a thickness z (nm) thereof is not smaller than 3 nm, and z??0.4x+24.6 is satisfied.

Abstract: Conventionally, CdTe solar cells are grown in superstrate configuration where the light enters the photovoltaic device through a transparent substrate. Still, efficiencies of CdTe solar cells grown in substrate configuration have so far been considerably lower than those grown in superstrate configuration. This invention discloses a photovoltaic device (0) in substrate configuration and a process of making thereof with which efficiencies approaching those of superstrate devices can be reproducibly achieved. Furthermore, long term stability is expected to be better than in state of the art devices. This method is advantageous because the growth in substrate configuration offers several advantages like the growth on metal foils and a more precise control of the junction.

Abstract: Manipulation of the passivation ligands of colloidal quantum dots and use in QD electronics. A multi-step electrostatic process is described which creates bare QDs, followed by the formation of QD superlattice via electric and thermal stimulus. Colloidal QDs with original long ligands (i.e. oleic acid) are atomized, and loaded into a special designed tank to be washed, followed by another atomization step before entering the doping station. The final step is the deposition of bare QDs onto substrate and growth of QD superlattice. The method permits the formation of various photonic devices, such as single junction and tandem solar cells based on bare QD superlattice, photodetectors, and LEDs. The devices include a piezoelectric substrate with an electrode, and at least one layer of bare quantum dots comprising group IV-VI elements on the electrode, where the bare quantum dots have been stripped of outer-layer ligands.

Abstract: The present invention discloses a method of fabricating a heterojunction battery, comprising the steps of: depositing a first amorphous silicon intrinsic layer on the front of an n-type silicon wafer, wherein the n-type silicon wafer may be a monocrystal or polycrystal silicon wafer; depositing an amorphous silicon p layer on the first amorphous silicon intrinsic layer; depositing a first boron doped zinc oxide thin film on the amorphous silicon p layer; forming a back electrode and an Al-back surface field on the back of the n-type silicon wafer; and forming a positive electrode on the front of the silicon wafer. In addition, the present invention further discloses a method of fabricating a double-sided heterojunction battery. In the present invention, the boron doped zinc oxide is used as an anti-reflection film in place of an ITO thin film; due to the special nature, especially the light trapping effect of the boron doped zinc oxide, the boron doped zinc oxide can achieve good anti-reflection.

Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.

Abstract: An improved multiple quantum well solar cell can be achieved by ensuring the bandgap of each quantum well thin layer is not uniform compared with other such layers. Gradation of the bandgap by varying the content of at least two group II to VI elements, and/or varying the thickness of consecutive quantum well layers, within consecutively formed quantum wells provides for an increase in absorption across a greater range of the available solar spectrum.

Abstract: A method for formulating a CIGS nanoparticle-based ink, which can be processed to form a thin film with a crack-free limit (CFL) of 500 nm or greater, comprises: dissolving or dispersing Cu(In,Ga)S2 and Cu(In,Ga)Se2 nanoparticles; mixing the nanoparticle solutions/dispersions and adding oleic acid to form an ink; depositing the ink on a substrate; annealing to remove the organic components of the ink formulation; forming a film with a CFL ?500 nm; and, repeating the deposition and annealing process to form a CIGS film having a thickness ?1 ?m. The film so produced may be incorporated into a thin film photovoltaic device.

Abstract: This invention relates to cells and devices for harvesting light. Specifically the cell comprises at least one electrode which comprises graphene or modified graphene and layer of a transition metal dichalcogenide in a vertical heterostructure. The cell may be part of a light harvesting device. The invention also relates to materials and methods for making such cells and devices.

Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Abstract: A photodiode including at least one active zone located between a first electrode and a second electrode, the active zone including elongated conducting or semiconducting elements extending between the electrodes and configured to promote collection and transport of charge carriers in the active zone.

Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° C. or less and having a contact resistance of less than 5×10?4 ohms-cm2.

Abstract: A method for forming contacts on a photovoltaic device includes forming a heterojunction cell including a substrate, a passivation layer and a doped layer and forming a transparent conductor on the cell. A patterned barrier layer is formed on the transparent conductor and has openings therein wherein the transparent conductor is exposed through the openings in the barrier layer. A conductive contact is grown through the openings in the patterned barrier layer by a selective plating process.

Abstract: A method for fabricating a solar cell element, the method comprising a step (a) of preparing a laminate and a chamber, a step (b) of bringing the laminate into contact with the aqueous solution in such a manner that the second surface is immersed in the aqueous solution after the step (a); a step (c) of applying a voltage difference between an anode electrode and the laminate under an atmosphere of the inert gas to form a Zn layer on the second surface after the step (b); and a step (d) of exposing the Zn layer to oxygen so as to convert the Zn layer into a ZnO crystalline layer after the step (c).

Abstract: The disclosure provides a method for fabricating a solar cell, including: providing a first substrate; forming a light absorption precursor layer on the first substrate; conducting a thermal process to the light absorption precursor layer to form a light absorption layer, wherein the light absorption layer includes a first light absorption layer and a second light absorption layer, and the first absorption layer is formed on the first substrate; forming a second substrate on the second light absorption layer; removing the first substrate to expose a surface of the first light absorption layer; forming a zinc sulfide (ZnS) layer on the surface of the first light absorption layer; and forming a transparent conducting oxide (TCO) layer on the zinc sulfide (ZnS) layer.

Abstract: According to one embodiment, a method for fabricating a stacked nitride-compound semiconductor structure includes forming a first protection film on a second surface of a substrate, forming a first nitride-compound semiconductor layer on the first surface of the substrate, forming a second protection film on the first nitride-compound semiconductor layer, removing the first protection film to expose the second surface of the substrate, forming a second nitride-compound semiconductor layer on the second surface of the substrate, and removing the second protection film to expose the first surface of the second nitride-compound semiconductor layer.

Abstract: Methods for doping an absorbent layer of a p-n heterojunction in a thin film photovoltaic device are provided. The method can include depositing a window layer on a transparent substrate, where the window layer includes at least one dopant (e.g., copper). A p-n heterojunction can be formed on the window layer, with the p-n heterojunction including a photovoltaic material (e.g., cadmium telluride) in an absorber layer. The dopant can then be diffused from the window layer into the absorber layer (e.g., via annealing).

Abstract: A multijunction solar cell including a contact layer with sulfur passivation on the surface of the contact layer adjacent to the window layer overlying the top subcell of the solar cell. The passivation is performed by application of a solution of ammonium sulphide.

Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a final base substrate; providing a first engineered substrate comprising a first zipper layer and a first seed layer; providing a second substrate; transferring the first seed layer to the final base substrate; forming at least one first solar cell layer on the first seed layer after transferring the first seed layer to the final base substrate, thereby obtaining a first wafer structure; forming at least one second solar cell layer on the second substrate, thereby obtaining a second wafer structure; and bonding the first and the second wafer structure to each other.

Abstract: A solar cell according to the disclosure includes a back electrode layer; and a light absorbing layer on the back electrode layer, wherein the light absorbing layer includes an undoped region and a doping region on the undoped region, and the doping region includes zinc. A method of fabricating a solar cell according to the disclosure includes forming a back electrode layer on a substrate; forming a preliminary light absorbing layer on the back electrode layer; forming a dopant supply layer on the preliminary light absorbing layer; and diffusing the dopant supply layer.

Abstract: A SPAD-type photodiode has a semiconductor substrate with a light-receiving surface. A lattice formed of interlaced strips made of a first material covers the light receiving surface. The lattice includes lattice openings with lateral walls covered by a spacer made of a second material. Then first and second materials have different optical indices, and further each optical index is less than or equal to the substrate optical index. A pitch of the lattice is of the order of a magnitude of an operating wavelength of the photodiode. The first and second materials are transparent at that operating wavelength. The lattice is made of a conductive material electrically coupled to an electrical connection node (for example, a bias voltage node).

Abstract: A light emitting assembly comprising a solid state device coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first, relatively shorter wavelength radiation, and a down-converting luminophoric medium arranged in receiving relationship to said first, relatively shorter wavelength radiation, and which in exposure to said first, relatively shorter wavelength radiation, is excited to responsively emit second, relatively longer wavelength radiation. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is down-converted to white light by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors in a polymeric matrix.

Abstract: Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of SixGe1?x passivated by amorphous SiyGe1?y:H.

Abstract: A thin film photovoltaic device (100) with a tunable, minimally conductive buffer (128) layer is provided. The photovoltaic device (100) may include a back contact (150), a transparent front contact stack (120), and an absorber (140) positioned between the front contact stack (120) and the back contact (150). The front contact stack (120) may include a low resistivity transparent conductive oxide (TCO) layer (124) and a buffer layer (128) that is proximate to the absorber layer (140). The photovoltaic device (100) may also include a window layer (130) between the buffer layer (128) and the absorber (140). In some cases, the buffer layer (128) is minimally conductive, with its resistivity being tunable, and the buffer layer (128) may be formed as an alloy from a host oxide and a high-permittivity oxide. The high-permittivity oxide may further be chosen to have a bandgap greater than the host oxide.

Abstract: A photovoltaic cell comprises a protective layer, a substrate adjacent to the protective layer, and a barrier layer adjacent to the substrate. The protective layer can comprise niobium, or a metal carbide, metal boride, metal nitride, or metal silicide. The barrier layer can comprise an electrically conductive material. The photovoltaic cell further comprises an absorber layer adjacent to the barrier layer. The absorber layer in some cases comprises copper indium gallium di-selenide (CIGS). The photovoltaic cell further comprises an optically transparent window layer adjacent to the absorber layer, and an electrically non-conductive aluminum zinc oxide (AZO) layer adjacent to the window layer. A transparent oxide layer is disposed adjacent to the AZO layer.

Abstract: An inline vacuum deposition system contains thermal source pairs configured in adjacent deposition zones. Dopant sources allow the electrical characteristics of the sequentially formed layers to be controlled for a preferred deposition growth profile.

Abstract: One embodiment of the present invention provides a heterojunction solar cell. The solar cell includes a metallurgical-grade Si (MG-Si) substrate, a layer of heavily doped crystalline-Si situated above the MG-Si substrate, a layer of lightly doped crystalline-Si situated above the heavily doped crystalline-Si layer, a backside ohmic-contact layer situated on the backside of the MG-Si substrate, a passivation layer situated above the heavily doped crystalline-Si layer, a layer of heavily doped amorphous Si (a-Si) situated above the passivation layer, a layer of transparent-conducting-oxide (TCO) situated above the heavily doped a-Si layer, and a front ohmic-contact electrode situated above the TCO layer.

Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields and lower costs. Certain solar cells may further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.

Abstract: A hole-blocking silicon/titanium-oxide heterojunction for silicon photovoltaic devices and methods of forming are disclosed. The electronic device includes at least two electrodes having a current path between the two electrodes. The electronic device also includes a heterojunction formed of a titanium-oxide layer deposited over a Si layer and being disposed in the current path. The heterojunction is configured to function as a hole blocker. The first electrode may be electrically coupled to the Si layer and a second electrode may be electrically coupled to the titanium-oxide layer. The device may also include a PN junction disposed in the Si layer, in the current path. The device may also include an electron-blocking heterojunction on silicon in the current path.

Abstract: A method of fabricating a superlattice structure requires that atoms of a first III-V semiconductor compound be introduced into a vacuum chamber such that the atoms are deposited uniformly on a substrate. Atoms of at least one additional III-V compound are also introduced such that the atoms of the two III-V compounds form a repeating superlattice structure of alternating thin layers. Atoms of a surfactant are also introduced into the vacuum chamber while the III-V semiconductor compounds are being introduced, or immediately thereafter, such that the surfactant atoms act to improve the quality of the resulting SL structure. The surfactant is preferably bismuth, and the III-V semiconductor compounds are preferably GaSb along with either InAs or InAsSb; atoms of each material are preferably introduced using molecular beam epitaxy. The resulting superlattice structure is suitably used to form at least a portion of an IR photodetector.