Heterojunction Patents (Class 438/94)
  • Publication number: 20130074912
    Abstract: Disclosed is a solar cell or component thereof that includes a p-type thin film solar light absorbing layer having one or more compositions of group II-VI alloys described as CdTexM1-x, where M is S, Se or O. An n-type thin-film transparent window layer comprising CdS is provided adjacent to the CdTexMi-x p-type thin film solar light absorbing layer such that a p-n junction formed between the layers.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 28, 2013
    Applicant: ROSESTREET LABS, LLC
    Inventor: RoseStreet Labs, LLC
  • Patent number: 8404511
    Abstract: Disclosed is a method for making a solar cell. In the method, there are provided first and second substrates each including first and second faces. There are provided first and second coating devices and a joining device. The first coating device is used to form a transparent electrode layer on the first face of the first substrate. The second coating device is used to form an absorbing layer on the first face of the second substrate. The second substrate is selenized by hot pressing. The joining device is used to join together the first and second substrates by joining the transparent electrode layer with the absorbing layer. The transparent electrode layer is joined with the absorbing layer by hot pressing. Thus, the solar cell is not made by coating one layer on another. Time for making the solar cell is reduced.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: March 26, 2013
    Assignee: Chung-Shan Institute of Science and Technology, Armaments, Bureau, Ministry of National Defense
    Inventors: Wen-Chueh Pan, Feng-Yu Tsai, Kong-Wei Cheng, Sheng-Ming Yeh, Hung-Chuan Hsu, Zan-Yu Chen
  • Patent number: 8399277
    Abstract: A compound semiconductor light-emitting diode includes a light-emitting layer (133) formed of aluminum-gallium-indium phosphide, a light-emitting part (13) having component layers individually formed of a Group III-V compound semiconductor, a transparent supporting layer (14) bonded to one of the outermost surface layers (135) of the light-emitting part (13) and transparent to the light emitted from the light-emitting layer (133), and a bonding layer (141) formed between the supporting layer (14) and the one of the outermost surface layers (135) of the light-emitting part (13) containing oxygen atoms at a concentration of 1×1020 cm?3 or less.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: March 19, 2013
    Assignee: Show A Denko K.K.
    Inventors: Takashi Watanabe, Ryouichi Takeuchi
  • Publication number: 20130062663
    Abstract: A dichromatic photodiode and method for dichromatic photodetection are disclosed. A wide bandgap junction comprises a lattice matched junction operable to detect a first light spectrum. A narrow bandgap junction is coupled to the wide bandgap junction, and comprises a photodiode structure. The narrow bandgap junction is operable to detect a second light spectrum.
    Type: Application
    Filed: September 13, 2011
    Publication date: March 14, 2013
    Inventors: Ping Yuan, Xiaogang Bai, Rengarajan Sudharsanan
  • Patent number: 8394658
    Abstract: Disclosed are methods of forming multi-doped junctions, which utilize a nanoparticle ink to form an ink pattern on a surface of a substrate. From the ink pattern, a densified film ink pattern can be formed. The disclosed methods may allow in situ controlling of dopant diffusion profiles.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 12, 2013
    Assignee: Innovalight, Inc.
    Inventors: Giuseppe Scardera, Dmitry Poplavskyy, Michael Burrows, Sunil Shah
  • Patent number: 8394663
    Abstract: Embodiments of the present invention involve photovoltaic (PV) cells comprising a semiconducting nanorod-nanocrystal-polymer hybrid layer, as well as methods for fabricating the same. In PV cells according to this invention, the nanocrystals may serve both as the light-absorbing material and as the heterojunctions at which excited electron-hole pairs split.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: March 12, 2013
    Assignee: Nanoco Technologies, Ltd.
    Inventors: James Harris, Nigel Pickett
  • Patent number: 8390025
    Abstract: A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: March 5, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Ann Gabrys, Peter J. Hopper, William French, Kyuwoon Hwang
  • Patent number: 8390027
    Abstract: A gallium nitride semiconductor device is disclosed that can be made by an easy manufacturing method. The device includes a silicon substrate, buffer layers formed on the top surface of the silicon substrate, and gallium nitride grown layers formed thereon. The silicon substrate has trenches 12 formed from the bottom surface, each trench having a depth reaching the gallium nitride grown layer through the silicon substrate and the buffer layers. The inside surface of each of the trenches and the bottom surface of the silicon substrate is covered with a drain electrode as a metal film. The vertical gallium nitride semiconductor device with this structure allows an electric current to flow in the direction of the thickness of the silicon substrate regardless of the resistance values of the gallium nitride grown layers and the buffer layers.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: March 5, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Publication number: 20130048989
    Abstract: A touch substrate includes a base substrate, a sensing element and a switching element. The sensing element is disposed over the base substrate, senses infrared light, and includes a sensing semiconductor pattern. The switching element is electrically connected to the sensing element, includes a material substantially the same as a material of the sensing semiconductor pattern, and includes a switching semiconductor pattern having a thickness different from a thickness of the sensing semiconductor pattern.
    Type: Application
    Filed: March 9, 2012
    Publication date: February 28, 2013
    Inventors: Sang-Youn HAN, Mi-Seon SEO, Sung-Hoon YANG
  • Publication number: 20130048061
    Abstract: A device and method for fabrication of a multi-junction photovoltaic device includes providing a parent substrate including a single crystal III-V material. The parent substrate forms a III-V cell of the multi-junction photovoltaic device. A lattice-matched Germanium layer is epitaxially grown on the III-V material to form a final cell of the multi-junction photovoltaic device. The Germanium layer is bonded to a foreign substrate.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: CHENG-WEI CHENG, Jack O. Chu, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20130049569
    Abstract: Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are disclosed. A solid state radiative semiconductor structure in accordance with a particular embodiment includes a first region having a first value of a material characteristic and being positioned to receive radiation at a first wavelength. The structure can further include a second region positioned adjacent to the first region to emit radiation at a second wavelength different than the first wavelength. The second region has a second value of the material characteristic that is different than the first value, with the first and second values of the characteristic forming a potential gradient to drive electrons, holes, or both electrons and holes in the radiative structure from the first region to the second region. In a further particular embodiment, the material characteristic includes material polarization.
    Type: Application
    Filed: August 23, 2011
    Publication date: February 28, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Patent number: 8378385
    Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: February 19, 2013
    Assignee: The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Jeramy Zimmerman, Kyusang Lee, Kuen-Ting Shiu
  • Publication number: 20130039664
    Abstract: Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.
    Type: Application
    Filed: August 12, 2011
    Publication date: February 14, 2013
    Inventors: Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Publication number: 20130037095
    Abstract: There is disclosed ultrahigh-efficiency single- and multi-junction thin-film solar cells. This disclosure is also directed to a substrate-damage-free epitaxial lift-off (“ELO”) process that employs adhesive-free, reliable and lightweight cold-weld bonding to a substrate, such as bonding to plastic or metal foils shaped into compound parabolic metal foil concentrators. By combining low-cost solar cell production and ultrahigh-efficiency of solar intensity-concentrated thin-film solar cells on foil substrates shaped into an integrated collector, as described herein, both lower cost of the module as well as significant cost reductions in the infrastructure is achieved.
    Type: Application
    Filed: July 6, 2012
    Publication date: February 14, 2013
    Inventors: Stephen R. FORREST, Christopher Kyle RENSHAW, Michael SLOOTSKY
  • Patent number: 8372684
    Abstract: The method and system for selenization in fabricating CIS and/or CIGS based thin film solar cell overlaying cylindrical glass substrates. The method includes providing a substrate, forming an electrode layer over the substrate and depositing a precursor layer of copper, indium, and/or gallium over the electrode layer. The method also includes disposing the substrate vertically in a furnace. Then a gas including a hydrogen species, a selenium species and a carrier gas are introduced into the furnace and heated to between about 350° C. and about 450° C. to at least initiate formation of a copper indium diselenide film from the precursor layer.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: February 12, 2013
    Assignee: Stion Corporation
    Inventors: Robert D. Wieting, Steven Aragon, Chester A. Farris, III
  • Publication number: 20130034924
    Abstract: A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.
    Type: Application
    Filed: October 12, 2012
    Publication date: February 7, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company
  • Publication number: 20130032780
    Abstract: A photodiode and the like capable of preventing the responsivity on the short wavelength side from deteriorating while totally improving the responsivity in a type II MQW structure, is provided. The photodiode is formed on a group III-V compound semiconductor substrate 1, and includes a pixel P. The photodiode includes an absorption layer 3 of a type II MQW structure, which is located on the substrate 1. The MQW structure includes fifty or more pairs of two different types of group III-V compound semiconductor layers 3a and 3b. The thickness of one of the two different types of group III-V compound semiconductor layers, which layer 3a has a higher potential of a valence band, is thinner than the thickness of the other layer 3b.
    Type: Application
    Filed: September 28, 2011
    Publication date: February 7, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei Fujii, Takashi Ishizuka, Katsushi Akita, Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai
  • Publication number: 20130032201
    Abstract: [Problem] In the case of further stacking a window layer or the like on a buffer layer, the buffer layer and the light absorption layer are likely to be damaged during the formation of the window layer due to inferior moisture resistance and plasma resistance, and photoelectric conversion elements sometimes fail to achieve any satisfactory conversion efficiency in terms of reliability. [Solving Means] Provided is a photoelectric conversion element including: a light absorption layer containing a I-B group element, a III-B group element, and a VI-B group element, which is provided on a lower electrode layer; a first semiconductor layer containing a III-B group element and a VI-B group element, which is provided on the light absorption layer; and a second semiconductor layer containing an oxide of a II-B group element, which is provided on the first semiconductor layer, wherein the light absorption layer comprises a doped layer region containing the II-B group element, on the first semiconductor layer side.
    Type: Application
    Filed: April 27, 2011
    Publication date: February 7, 2013
    Applicant: KYOCERA CORPORATION
    Inventors: Satoshi Oomae, Shinichi Abe, Masato Fukudome, Takeshi Ookuma, Katsuhiko Shirasawa, Takehiro Nishimura, Daisuke Toyota, Hirotaka Sano, Keita Kurosu
  • Publication number: 20130019944
    Abstract: A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 24, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoar-Tabari, Marinus Hopstaken, Dae-Gyu Park, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20130019945
    Abstract: A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.
    Type: Application
    Filed: September 6, 2012
    Publication date: January 24, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoar-Tabari, Marinus Hopstaken, Dae-Gyu Park, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20130014813
    Abstract: The invention disclosed a method of fabricating GaInP/GaAs/Si triple junction solar cells by epitaxy lift-off and mechanical stack techniques. First, a GaInP(1.85 eV)/GaAs(1.42 eV) dual-junction cell is fabricated on a GaAs substrate, and a Si single junction is fabricated on a Si substrate. The Si single junction cell and the GaInP/GaAs dual-junction cell are joined together robustly by metal-metal bonding. A buffer layer, Gallium Phosphide (GaP) inserted between GaAs and Si can further optimize electrical, thermal and optical coupling. Furthermore, when a GaP layer is grown on a p-type Si substrate, a Si p-n junction as a fully functional solar cell is formed simultaneously, thereby reducing manufacturing cost. The technology can achieve GaInP/GaAs/Si triple junction solar cells of the conversion efficiency as high as 36% under a standard AM1.5 solar spectrum, with the optimal current 13.3 mA/cm2 and the sum of open-circuit voltages 3.1V.
    Type: Application
    Filed: January 11, 2012
    Publication date: January 17, 2013
    Inventors: Weiming Wang, Xin Zhu, Jun Yang
  • Patent number: 8354324
    Abstract: A two-terminal mesa phototransistor and a method for making it are disclosed. The photo transistor has a mesa structure having a substantially planar semiconductor surface. In the mesa structure is a first semiconductor region of a first doping type, and a second semiconductor region of a second doping type opposite to that of the first semiconductor region, forming a first semiconductor junction with the first region. In addition, a third semiconductor region of the first doping type forms a second semiconductor junction with the second region. The structure also includes a dielectric layer. The second semiconductor region, first semiconductor junction, and second semiconductor junction each has an intersection with the substantially planar semiconductor surface. The dielectric covers, and is in physical contact with, all of the intersections.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 15, 2013
    Assignee: Wavefront Holdings, LLC
    Inventor: Jie Yao
  • Patent number: 8350290
    Abstract: Provided is a light-receiving device which has light-receiving sensitivity superior to that of a conventional Schottky diode type light-receiving device and also has sufficiently-strengthened junction of a Schottky electrode. A first contact layer formed of AlGaN and having conductivity, a light-receiving layer formed of AlGaN, and a second contact layer formed of AlN and having a thickness of 5 nm are epitaxially formed on a predetermined substrate in the stated order, and a second electrode is brought into Schottky junction with the second contact layer, to thereby form MIS junction. Further, after the Schottky junction, heat treatment is performed under a nitrogen gas atmosphere at 600° C. for 30 seconds.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: January 8, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Mitsuhiro Tanaka
  • Publication number: 20130000726
    Abstract: A thin film photovoltaic cell (10) comprises an n-type semiconductor window layer (40), a p-type semiconductor absorption layer (5) and a pn-junction (6) at the interface between these two layers, wherein the p-type semiconductor absorption layer is formed of cadmium telluride CdTe. According to the present invention, the n-type semiconductor window layer (40) comprises zinc oxide/sulfide Zn (O,S).
    Type: Application
    Filed: December 22, 2010
    Publication date: January 3, 2013
    Applicant: Beneq Oy
    Inventor: Jarmo Skarp
  • Publication number: 20130005073
    Abstract: A chemical bath deposition method and a system are presented to prepare different thin films on plane substrates. In particular, they are useful to deposit CdS or ZnS buffer layers in manufacture of thin film solar cells. This method and the deposition system deposit thin films onto vertically travelling plane workpieces delivered by a conveyor belt. The thin films are deposited with continuously spraying the reaction solutions from their freshly mixed styles to gradually aged forms until the designed thickness is obtained. The substrates and the solutions are heated to a reaction temperature. During the deposition processes, the front surfaces of the substrates are totally covered with the sprayed solutions but the substrate backsides are remained dry. The reaction ambience inside the reactor can be isolated from the outside atmosphere. The apparatus is designed to generate a minimum amount of waste solutions for chemical treatments.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventor: Jiaxiong Wang
  • Patent number: 8344241
    Abstract: Nanostructures and photovoltaic structures are disclosed. A nanostructure according to one embodiment includes an array of nanocables extending from a substrate, the nanocables in the array being characterized as having a spacing and surface texture defined by inner surfaces of voids of a template; an electrically insulating layer extending along the substrate; and at least one layer overlaying the nanocables. A nanostructure according to another embodiment includes a substrate; a portion of a template extending along the substrate, the template being electrically insulative; an array of nanocables extending from the template, portions of the nanocables protruding from the template being characterized as having a spacing, shape and surface texture defined by previously-present inner surfaces of voids of the template; and at least one layer overlaying the nanocables.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: January 1, 2013
    Assignees: Q1 Nanosystems Corporation, The Regents of the University of California
    Inventors: Ruxandra Vidu, Brian Argo, John Argo, Pieter Stroeve, Jie-Ren Ku
  • Patent number: 8343794
    Abstract: A method is provided for producing a hybrid multi junction photovoltaic device. The method begins by providing a plurality of planar photovoltaic semi-transparent modules. Each of the modules is a fully functional, thin-film, photovoltaic device and includes first and second conductive layers and at least first and second semiconductor layers disposed between the conductive layers. The first and second semiconductor layers define a junction at an interface therebetween. The method continues by disposing the modules one on top of another and hybridly adhering them to each other. At least one of the modules is configured to convert a first spectral portion of optical energy into an electrical voltage and transmit a second spectral portion of optical energy to another of the junctions that is configured to convert at least part of the second spectral portion of optical energy into an electrical voltage.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: January 1, 2013
    Assignee: Sunlight Photonics Inc.
    Inventors: Sergey Frolov, Michael Cyrus
  • Publication number: 20120326122
    Abstract: Provided are an epitaxial wafer, a photodiode, and the like that include an antimony-containing layer and can be efficiently produced such that protruding surface defects causing a decrease in the yield can be reduced and impurity contamination causing degradation of the performance can be suppressed. The production method includes a step of growing an antimony (Sb)-containing layer on a substrate 1 by metal-organic vapor phase epitaxy using only metal-organic sources; and a step of growing, on the antimony-containing layer, an antimony-free layer including a window layer 5, wherein, from the growth of the antimony-containing layer to completion of the growth of the window layer, the growth is performed at a growth temperature of 425° C. or more and 525° C. or less.
    Type: Application
    Filed: October 3, 2011
    Publication date: December 27, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei Fujii, Katsushi Akita, Takashi Ishizuka
  • Patent number: 8338859
    Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and smaller coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area t
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: December 25, 2012
    Assignee: Furukawa Electric Co., Ltd
    Inventors: Takuya Kokawa, Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami
  • Publication number: 20120318340
    Abstract: One embodiment of the present invention provides a back junction solar cell. The solar cell includes a base layer, a quantum-tunneling-barrier (QTB) layer situated below the base layer facing away from incident light, an emitter layer situated below the QTB layer, a front surface field (FSF) layer situated above the base layer, a front-side electrode situated above the FSF layer, and a back-side electrode situated below the emitter layer.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 20, 2012
    Applicant: SILEVO, INC.
    Inventors: Jiunn Benjamin Heng, Jianming Fu, Zheng Xu, Zhigang Xie
  • Publication number: 20120318336
    Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: BAHMAN HEKMATSHOAR-TABARI, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8334451
    Abstract: A photovoltaic (PV) cell device comprises a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of vertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer; a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: December 18, 2012
    Assignee: IXYS Corporation
    Inventors: Nestore Polce, Ronald P. Clark, Nathan Zommer
  • Patent number: 8334157
    Abstract: A method of manufacturing a semiconductor device comprises depositing a semiconductor layer over a semiconductor surface having at least one first region with a first (average surface lattice) parameter value and at least one second region having a second parameter value different from the first. The semiconductor layer is deposited to a thickness so self-organized islands form over both the first and second regions. The difference in the parameter value means the islands over the first region have a first average parameter value and the islands over the second region have a second average parameter value different from the first. A capping layer is deposited over islands and has a greater forbidden bandgap than the islands whereby the islands form quantum dots, which have different properties over the first and second regions due to difference(s) between the first and second region islands.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: December 18, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tim Michael Smeeton, Katherine Louise Smith, Mathieu Xavier Sénès, Stewart Edward Hooper
  • Publication number: 20120298169
    Abstract: A multi junction photovoltaic device includes lower pn junction layers comprising silicon and upper pn junction layers formed over the lower pn junction layers. The upper pn junction layers include a CdTe layer, wherein the upper pn junction layers are electrically serially connected to the lower pn junction layers. The upper pn junction layers can convert a first portion of photons into a first electric voltage. The lower pn junction layers can convert a second portion of photons into a second electric voltage lower than the first electric voltage.
    Type: Application
    Filed: November 18, 2011
    Publication date: November 29, 2012
    Inventors: George X. Guo, Zhengyu Zhang
  • Publication number: 20120301993
    Abstract: A method for generating electric power including the steps of: (a) preparing a solar cell having a condensing lens and a solar cell element, wherein the solar cell element includes an n-type GaAs layer, a p-type GaAs layer, a quantum tunneling layer, an n-type InGaP layer, a p-type InGaP layer, a p-type window layer, an n-side electrode, and a p-side electrode, and satisfies the following equation (I): d2<d1, d3<d1, 1 nanometer?d2?4 nanometers, 1 nanometer?d3?4 nanometers, d5<d4, d6<d4, 1 nanometer?d5?5 nanometers, 1 nanometer?d6?5 nanometers, 100 nanometers?w2, 100 nanometers?w3, 100 nanometers?w4, and 100 nanometers?w5 . . . (I); and (b) irradiating a region S which is included in the surface of the p-type window layer through the condensing lens with light to satisfy the following equation (II) in order to generate a potential difference between the n-side electrode and the p-side electrode: w6?w1 . . . (II).
    Type: Application
    Filed: June 1, 2012
    Publication date: November 29, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Akio MATSUSHITA, Akihiro ITOH, Tohru NAKAGAWA, Hidetoshi ISHIDA
  • Patent number: 8314327
    Abstract: Novel structures of photovoltaic cells (also treated as solar cells) are provided. The cells are based on nanometer-scaled wires, tubes, and/or rods, which are made of electronic materials covering semiconductors, insulators or metallic in structure. These photovoltaic cells have large power generation capability per unit physical area over the conventional cells. These cells will have enormous applications in space, commercial, residential, and industrial applications.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: November 20, 2012
    Assignee: Banpil Photonics, Inc.
    Inventor: Achyut Kumar Dutta
  • Patent number: 8313968
    Abstract: Using a laser lift-off (LLO) nonbonding technique, freestanding 4-layer GaN/AlGaN heterostructure membranes have been formed. A 4×4 mm mask was attached to the area at the center of the most-upper AlGaN layer was attached using a nonbonding material such as vacuum grease. A microscopic slide attached by an adhesive provided support for the structure during the laser lift-off without bonding to the layers. The vacuum grease and the mask isolated the adhesive from the structure at the center. The microscopic slide served as a temporarily nonbonding handle substrate. Laser lift-off of the sapphire substrate from the heterostructures was performed. The remaining adhesive served as a supporting frame for the structure making a free-standing 4-layer GaN/AGaN heterostructure membrane. Other frameless freestanding membranes can be fabricated for a variety of applications including further III-nitride growth, heterogeneous integration, packaging of micro systems, and thin film patterns.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: November 20, 2012
    Inventor: Amal Elgawadi
  • Patent number: 8309843
    Abstract: Novel structures of photovoltaic cells (also treated as solar cells) are provided. The Cells are based on the nanometer-scaled wire, tubes, and/or rods, which are made of the electronics materials covering semiconductors, insulator or metallic in structure. These photovoltaic cells have large power generation capability per unit physical area over the conventional cells. These cells can have also high radiation tolerant capability. These cells will have enormous applications such as in space, in commercial, residential and industrial applications.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: November 13, 2012
    Assignee: Banpil Photonics, Inc.
    Inventors: Nobuhiko P. Kobayashi, Achyut K. Dutta
  • Publication number: 20120282718
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Application
    Filed: July 20, 2012
    Publication date: November 8, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Anthony J. Lochtefeld
  • Publication number: 20120273839
    Abstract: A semiconductor wafer includes a base wafer, a sacrificial layer that is lattice-matched or pseudo lattice-matched to the base wafer, a first crystal layer that is formed on the sacrificial layer and made of an epitaxial crystal of SixGe1-x, (0?x<1), and a second crystal layer that is formed on the first crystal layer and made of an epitaxial crystal of a group 3-5 compound semiconductor having a larger band gap than the first crystal layer. The base wafer is, for example, made of single-crystal GaAs. The sacrificial layer is, for example, made of an epitaxial crystal of InmAlnGa1-m-nAs (0?m<1, 0<n?1, 0<n+m?1).
    Type: Application
    Filed: June 22, 2012
    Publication date: November 1, 2012
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Masahiko HATA, Hisashi YAMADA, Tomoyuki TAKADA
  • Publication number: 20120273838
    Abstract: Disclosed are minority carrier based mercury-cadmium telluride (HgCdTe) infrared detectors and arrays, and methods of making, are disclosed. The constructions provided by the invention enable the detectors to be used at higher temperatures, and/or be implemented on less expensive semiconductor substrates to lower manufacturing costs. An exemplary embodiment a substrate, a bottom contact layer disposed on the substrate, a first mercury-cadmium telluride layer having a first bandgap energy value disposed on the bottom contact layer, a second mercury-cadmium telluride layer having a second bandgap energy value that is greater than the first bandgap energy value disposed on the first mercury-cadmium telluride layer, and a collector layer disposed on the second mercury-cadmium telluride layer, wherein the first and second mercury-cadmium telluride layers are each doped with an n-type dopant.
    Type: Application
    Filed: December 14, 2011
    Publication date: November 1, 2012
    Inventors: Michael A. Kinch, Christopher A. Schaake
  • Patent number: 8294027
    Abstract: A method for fabricating a cell structure includes doping a substrate to form a N-region and a P-region, disposing a first anti-reflective layer on the substrate, disposing a metallic contact paste on the first anti-reflective layer, drying the metallic contact paste to form contacts, disposing a second anti-reflective layer on the first anti-reflective layer and the metallic contacts, and heating the cell structure, wherein heating the cell structure results in metallic contact material penetrating the first anti-reflective layer and contacting the substrate.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Harold J. Hovel, Rainer K. Krause, Zhengwen Li, Huilong Zhu
  • Publication number: 20120255600
    Abstract: A photovoltaic device including at least one top cell that include at least one semiconductor material; a bottom cell of a germanium containing material having a thickness of 10 microns or less; and a back surface field (BSF) region provided by a eutectic alloy layer of aluminum and germanium on the back surface of the bottom cell of that is opposite the interface between the bottom cell and at least one of the top cells. The eutectic alloy of aluminum and germanium bonds the bottom cell of the germanium-containing material to a supporting substrate.
    Type: Application
    Filed: April 6, 2011
    Publication date: October 11, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20120248410
    Abstract: An electron transporting surfactant is added to a raw material solution such that the electron transporting surfactant is coordinated on the surfaces of quantum dots, and after the dispersion solvent is evaporated by vacuum drying, the immersion in a solvent containing a hole transporting surfactant prepares a quantum dot dispersed solution with a portion of the electron transporting surfactant replaced with the hole transporting surfactant. The quantum dot dispersed solution is applied onto a substrate to prepare a hole transport layer and a quantum dot layer at the same time, and thereby to achieve a thin film which has a two-layer structure.
    Type: Application
    Filed: June 15, 2012
    Publication date: October 4, 2012
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Koji Murayama
  • Publication number: 20120240989
    Abstract: A method for fabricating a thin film photovoltaic device is provided. The method includes providing a substrate comprising a thin film photovoltaic absorber which has a surface including copper, indium, gallium, selenium, and sulfur. The method further includes subjecting the surface to a material containing at least a zinc species substantially free of any cadmium. The surface is heated to cause formation of a zinc doped material. The zinc doped material is free from cadmium. Furthermore the method includes forming a zinc oxide material overlying the zinc doped material and forming a transparent conductive material overlying the zinc oxide material.
    Type: Application
    Filed: September 19, 2011
    Publication date: September 27, 2012
    Applicant: Stion Corporation
    Inventors: Kannan Ramanathan, Robert D. Wieting
  • Publication number: 20120231569
    Abstract: An optoelectronic component with three-dimension quantum well structure and a method for producing the same are provided, wherein the optoelectronic component comprises a substrate, a first semiconductor layer, a transition layer, and a quantum well structure. The first semiconductor layer is disposed on the substrate. The transition layer is grown on the first semiconductor layer, contains a first nitride compound semiconductor material, and has at least a texture, wherein the texture has at least a first protrusion with at least an inclined facet, at least a first trench with at least an inclined facet and at least a shoulder facet connected between the inclined facets. The quantum well structure is grown on the texture and shaped by the protrusion, the trench and the shoulder facet.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 13, 2012
    Applicant: HERMES-EPITEK CORP.
    Inventors: BENSON CHAO, CHUNG-HUA FU, SHIH-CHIEH JANG
  • Publication number: 20120227797
    Abstract: Inverted metamorphic multijunction solar cells having a heterojunction middle subcell and a graded interlayer, and methods of making same, are disclosed herein. The present disclosure provides a method of manufacturing a solar cell using an MOCVD process, wherein the graded interlayer is composed of (InxGa1-x)y Al1-yAs, and is formed in the MOCVD reactor so that it is compositionally graded to lattice match the middle second subcell on one side and the lower third subcell on the other side, with the values for x and y computed and the composition of the graded interlayer determined so that as the layer is grown in the MOCVD reactor, the band gap of the graded interlayer remains constant at 1.5 eV throughout the thickness of the graded interlayer.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 13, 2012
    Applicant: Emcore Solar Power, Inc.
    Inventors: Mark A. Stan, Arthur Cornfeld
  • Publication number: 20120216858
    Abstract: Photovoltaic cells with one or more subcells are provided with a wide band gap, pseudomorphic window layer of at least 15 nm in thickness and with an intrinsic material lattice constant that differs by at least 1% from an adjacent emitter layer. This window layer has a higher band gap than a window layer with substantially the same intrinsic material lattice constant as the adjacent emitter layer, which increases the light transmission through the window, thereby increasing the current generation in the solar cell. The quality of being pseudomorphic material preserves a good interface between the window and the emitter, reducing the minority carrier surface recombination velocity. A method is provided for building a wide band gap, pseudomorphic window layer of a photovoltaic cell that has an intrinsic material lattice constant that differs by at least 1% from the adjacent emitter layer.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 30, 2012
    Applicant: Solar Junction Corporation
    Inventors: Rebecca Elizabeth Jones-Albertus, Ferran Suarez Arias, Michael West Wiemer, Michael J. Sheldon, Homan B. Yuen
  • Publication number: 20120217478
    Abstract: Provided are a semiconductor device and an optical sensor device, each having reduced dark current, and detectivity extended toward longer wavelengths in the near-infrared. Further, a method for manufacturing the semiconductor device is provided. The semiconductor device 50 includes an absorption layer 3 of a type II (GaAsSb/InGaAs) MQW structure located on an InP substrate 1, and an InP contact layer 5 located on the MQW structure. In the MQW structure, a composition x (%) of GaAsSb is not smaller than 44%, a thickness z (nm) thereof is not smaller than 3 nm, and z??0.4x+24.6 is satisfied.
    Type: Application
    Filed: May 19, 2011
    Publication date: August 30, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Katsushi Akita, Takashi Ishizuka, Hideaki Nakahata, Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai
  • Publication number: 20120199184
    Abstract: Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 9, 2012
    Applicant: Alta Devices, Inc.
    Inventors: Hui NIE, Brendan M. Kayes, Isik C. Kizilyalli