Heterojunction Patents (Class 438/94)
  • Publication number: 20130344645
    Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields and lower costs. Certain solar cells may further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 26, 2013
    Inventors: David AHMARI, Swee LIM, Shiva RAI, David FORBES
  • Publication number: 20130344644
    Abstract: A photoreceptor includes a multilayer blocking structure to reduce dark discharge of the surface voltage of the photoreceptor resulting from electron injection from an electrically conductive substrate. The multilayer blocking structure includes wide band gap semiconductor layers in alternating sequence with one or more narrow band gap blocking layers. A fabrication method of the photoreceptor includes transfer-doping of the narrow band gap blocking layers, which are deposited in alternating sequence with wide band gap semiconductor layers to form a blocking structure. Suppression of hole or electron injection can be obtained using the method.
    Type: Application
    Filed: July 20, 2012
    Publication date: December 26, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Jeehwan Kim, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8610171
    Abstract: A semiconductor-based SWIR infrared detector sensitive to wavelengths shorter than about 2.5 microns comprises a stack of semiconductor layers based on III-V materials forming a PIN photodiode. The stack includes a naked electrical contact, called a lower electrical contact, serving as an optical window; and a detection layer sensitive to said wavelengths. The lower contact comprises at least one layer of indirect-bandgap III-V material(s) doped n-type, pseudomorphic or lattice matched with a substrate intended to serve as a temporary substrate possibly being made of a III-V material such as InP or GaAs or of silicon or germanium.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: December 17, 2013
    Assignee: Thales
    Inventors: Philippe Bois, Olivier Parillaud, Xavier Marcadet, Michel Papuchon
  • Publication number: 20130327384
    Abstract: The present invention provides a multi-junction solar cell capable of increasing the degree of freedom of the selection of compound semiconductors. The multi-junction solar cell 1 includes a layered structure section 4 including compound semiconductor photovoltaic devices 2 and 3 matched in lattice constant with each other and joined to each other, and a nanopillar structure section 7 including a compound semiconductor photovoltaic device or a plurality of compound semiconductor photovoltaic devices 5 and 6 joined to each other.
    Type: Application
    Filed: March 16, 2012
    Publication date: December 12, 2013
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Hirotaka Endo, Hajime Goto, Takanori Maebashi, Mitsutaka Nishijima, Natsuo Nakamura
  • Publication number: 20130330874
    Abstract: A chemical bath deposition method is presented to prepare different thin films on plane substrates. In particular, they are useful to deposit CdS or ZnS buffer layers in manufacture of thin film solar cells. This method and the deposition apparatus deposit thin films onto vertically travelling plane workpieces delivered by a conveyor belt. The thin films are deposited by continuously spraying the reaction solutions from their freshly mixed styles to gradually aged forms until the designed thickness is obtained. The substrates and the solutions are heated to a reaction temperature. During the deposition processes, the front surfaces of the substrates are totally covered with the sprayed solutions but the substrate backsides are remained dry. The reaction ambience inside the reactor can be isolated from the outside atmosphere. The method is designed to generate a minimum amount of waste solutions for chemical treatments.
    Type: Application
    Filed: August 21, 2013
    Publication date: December 12, 2013
    Inventor: Jiaxiong Wang
  • Publication number: 20130319523
    Abstract: The invention relates to a conductive transparent glass substrate for a photovoltaic cell, that does not comprise a metal layer and comprises, in succession, a sheet of glass, a barrier layer based on oxide, nitride or oxynitride, a conductive functional layer based on doped zinc oxide or doped indium oxide, and a protection layer based on nitride, oxynitride or oxycarbide such that the barrier layer has a thickness that is at least more than, or equal to 10 nm, and, at the most, less than or equal to 100 nm, the functional layer has a thickness that is at least more than or equal to 200 nm and at the most, less than or equal to 1200 nm, and the protection layer has a thickness that is at least more than or equal to 10 nm, and at the most, lower than or equal to 250 nm. The invention also relates to the method of producing said substrate, to the CdTe-based photovoltaic cells incorporating said substrate, and to the method for producing said cells.
    Type: Application
    Filed: February 16, 2012
    Publication date: December 5, 2013
    Applicant: AGC GLASS EUROPE
    Inventors: Bart Ballet, Otto Agutsson, Gaetan Di Stefano
  • Publication number: 20130313521
    Abstract: An object of the present invention is to provide, for example, a photodiode that can have sufficiently high sensitivity in a near-infrared wavelength range of 1.5 ?m to 1.8 ?m and can have a low dark current. A photodiode (10) according to the present invention includes a buffer layer (2) positioned on and in contact with an InP substrate (1), and an absorption layer (3) positioned on and in contact with the buffer layer, wherein the absorption layer includes 50 or more pairs in which a first semiconductor layer 3a and a second semiconductor layer 3b constitute a single pair, the first semiconductor layer 3a having a bandgap energy of 0.73 eV or less, the second semiconductor layer 3b having a larger bandgap energy than the first semiconductor layer 3a, and the first semiconductor layer 3a and the second semiconductor layer 3b constitute a strain-compensated quantum well structure and each have a thickness of 1 nm or more and 10 nm or less.
    Type: Application
    Filed: February 3, 2012
    Publication date: November 28, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takashi Ishizuka, Kei Fujii, Youichi Nagai, Hiroshi Inada, Yasuhiro Iguchi
  • Publication number: 20130312818
    Abstract: A method of forming a multijunction solar cell comprising an upper subcell, a middle subcell, and a lower subcell comprising providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on said substrate having a first band gap; forming a second solar subcell over said first subcell having a second band gap smaller than said first band gap; and forming a grading interlayer over said second sub cell having a third band gap larger than said second band gap forming a third solar subcell having a fourth band gap smaller than said second band gap such that said third subcell is lattice mis-matched with respect to said second subcell.
    Type: Application
    Filed: July 31, 2013
    Publication date: November 28, 2013
    Applicant: Emcore Solar Power, Inc.
    Inventors: Arthur Cornfeld, Mark A. Stan
  • Publication number: 20130306141
    Abstract: The purposes of the present invention are: to eliminate an electrode on a top cell of a multi-junction compound solar cell, said electrode blocking solar light; to provide a multi-junction compound solar cell having a structure that is not easily broken in manufacture steps; and to shorten a manufacture lead time of a multi-junction compound solar battery. A multi-junction compound solar cell has: a multi-junction cell laminate having the top cell and a bottom cell; a transparent electrode, which is disposed on the light incoming surface of the top cell; a lower electrode having potential of the bottom cell; and a side-surface electrode, which is disposed on the side surface of the solar cell with an insulating layer therebetween, and is electrically connected to the transparent electrode. In the multi-junction compound solar cell, the side-surface electrode is led out to the lower electrode.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 21, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: Kazuhiro Nobori
  • Patent number: 8580603
    Abstract: A method of fabricating a solar cell involves electroplating a Group IIB-VIA material as a first or sub-layer over a junction partner layer, and then forming a second layer, also of a Group IIB-VIA material over the sub-layer. Both the sub-layer and the second layer comprise Te. The electroplating is performed at relatively low temperatures, as for example, below 100° C. Forming the sub-layer by low temperature electroplating produces a small grained compact film that protects the interface between the sub-layer and the junction partner during the formation of the second layer. The second layer may be formed by physical vapor deposition or ink deposition. A solar cell has a first layer of a stoichiometric Group IIB-VIA material formed on a CdS film, and a second layer of a Group IIB-V1A material. Both the first and second layers contain Te. The first layer may comprise CdTe with a grain size small than 0.5 microns and the second layer may comprise CdTe with a grin size in the range of 1-5 microns.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: November 12, 2013
    Assignee: EncoreSolar, Inc.
    Inventor: Bulent M. Basol
  • Publication number: 20130292685
    Abstract: The present invention relates to optoelectronic device layer structures, light emitting devices, and detectors based upon heterostructures formed between hexagonal boron nitride (hNB) and III-nitrides, and more particularly, to heterojunction devices capable of emitting and detecting photons in the ultraviolet (UV) and extremely ultraviolet (RUV) spectral range. The present invention also relates to neutron detectors based on epitaxially grown hBN thin films (or epitaxial layers) and hBN stacked thin films (or epitaxial layers) to satisfy the thickness required for capturing all incoming neutrons.
    Type: Application
    Filed: May 5, 2012
    Publication date: November 7, 2013
    Applicant: TEXAS TECH UNIVERSITY SYSTEM
    Inventors: Hongxing Jiang, Sashikanth Majety, Rajendra Dahal, Jing Li, Jingyu Lin
  • Patent number: 8575471
    Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: November 5, 2013
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak, William E. McMahon
  • Publication number: 20130285015
    Abstract: Radiation-emitting semiconductor devices include a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a multi-quantum well structure disposed between the first base region and the second base region. The multi-quantum well structure includes at least three quantum well regions and at least two barrier regions. An electron hole energy barrier between a third of the quantum well regions and a second of the quantum well regions is less than an electron hole energy barrier between the second of the quantum well regions and a first of the quantum well regions. Methods of forming such devices include sequentially epitaxially depositing layers of such a multi-quantum well structure, and selecting a composition and configuration of the layers such that the electron hole energy barriers vary across the multi-quantum well structure.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Inventor: Chantal Arena
  • Patent number: 8569097
    Abstract: Solar cell structures include stacked layers in reverse order on a germanium substrate wherein a n++ (In)GaAs buffer layer plays dual roles as buffer and contact layers in the inverted structures. The absorbing layers employed in such exemplary structures are III-V layers such as (In)GaAs. Controlled spalling may be employed as part of the fabrication process for the solar cell structures, which may be single or multi-junction. The requirement for etching a buffer layer is eliminated, thereby facilitating the manufacturing process of devices using the disclosed structures.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Bahman Hekmatshoartabari, Ning Li, Devendra K. Sadana, Davood Shahrjerdi
  • Publication number: 20130255775
    Abstract: A wide band gap, heterojunction photovoltaic material comprises a bulk layer, a high-resistivity layer and a microcrystalline silicon carbide layer. The heterojunction semiconductor material is formed by heating a single-piece semiconductor material to form a high-resistivity layer over a bulk layer, the high-resistivity layer having SiC seed crystals at the top surface. A layer of SiC is sputtered over the high-resistivity layer, and the structure is annealed. The annealing and the SiC seed crystals causes the sputtered SiC layer to convert into a microcrystalline ?-SiC layer. When the layer of SiC is sputtered using a p-type SiC target, a p-type SiC layer is formed over the high-resistivity layer. The heterojunction material may exhibit photovoltaic properties. Applications include forming a photovoltaic device with the heterojunction material.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 3, 2013
    Inventors: Kuniaki Shida, Daisuke Okumura, Jose Briceno
  • Patent number: 8546167
    Abstract: A nitride-based semiconductor light-emitting element includes an n-GaN layer 102, a p-GaN layer 107, and a GaN/InGaN multi-quantum well active layer 105, which is interposed between the n- and p-GaN layers 102 and 107. The GaN/InGaN multi-quantum well active layer 105 is an m-plane semiconductor layer, which includes an InxGa1-xN (where 0<x<1) well layer 104 that has a thickness of 6 nm or more and 17 nm or less, and oxygen atoms included in the GaN/InGaN multi-quantum well active layer 105 have a concentration of 3.0×1017 cm?3 or less.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: October 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Ryou Kato, Shunji Yoshida, Toshiya Yokogawa
  • Publication number: 20130248821
    Abstract: A light receiving element includes an InP substrate that is transparent to light having a wavelength of 3 to 12 ?m, a buffer layer located in contact with the InP substrate, and a light-receiving layer having a multiple quantum well structure, the light-receiving layer having a cutoff wavelength of 3 ?m or more and being lattice-matched with the buffer layer. In the light receiving element, the buffer layer is epitaxially grown on the InP substrate while the buffer layer and the InP substrate exceed a range of a normal lattice-matching condition, and the buffer layer is constituted by a GaSb layer.
    Type: Application
    Filed: November 29, 2011
    Publication date: September 26, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kohei Miura, Hiroshi Inada, Yasuhiro Iguchi, Tadashi Saito
  • Publication number: 20130240026
    Abstract: The disclosure provides semiconductive material derived from group IV elements that are useful for photovoltaic applications.
    Type: Application
    Filed: September 1, 2012
    Publication date: September 19, 2013
    Applicant: THE CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Harry A. Atwater, Naomi Coronel, Lise Lahourcade
  • Publication number: 20130240039
    Abstract: The present invention provides a method for manufacturing solar cells and the solar cells manufactured thereby. The method is capable of manufacturing flexible solar cells simply, by attaching a flexible substrate on a second electrode after forming multiple layers such as a copper indium gallium selenide (CIGS) absorption layer on a sacrificial substrate under a high temperature process. Additionally, a separation film is removed by a laser or by selective wet etching after the attachment of the flexible substrate. Therefore, flexible CIGS solar cells having high efficiency can be achieved.
    Type: Application
    Filed: November 25, 2011
    Publication date: September 19, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventor: Rae-Man Park
  • Publication number: 20130234202
    Abstract: Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Kei-Wei Chen, Szu-An Wu
  • Publication number: 20130233380
    Abstract: A photovoltaic module including a dielectric tunneling layer and methods of forming a photovoltaic module with a dielectric tunneling layer.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 12, 2013
    Inventors: Zhibo Zhao, Chungho Lee, Benyamin Buller, Rui Shao, Gang Xiong
  • Publication number: 20130230945
    Abstract: A method and apparatus for forming a crystalline cadmium stannate layer of a photovoltaic device by heating an amorphous layer in the presence of hydrogen gas.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 5, 2013
    Applicant: FIRST SOLAR, INC
    Inventors: Rui Shao, Zhibo Zhao, Markus Gloeckler, David Hwang, Benyamin Buller
  • Publication number: 20130230944
    Abstract: Methods for doping an absorbent layer of a p-n heterojunction in a thin film photovoltaic device are provided. The method can include depositing a window layer on a transparent substrate, where the window layer includes at least one dopant (e.g., copper). A p-n heterojunction can be formed on the window layer, with the p-n heterojunction including a photovoltaic material (e.g., cadmium telluride) in an absorber layer. The dopant can then be diffused from the window layer into the absorber layer (e.g., via annealing).
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Applicant: PRIMESTAR SOLAR, INC.
    Inventors: Scott Daniel Feldman-Peabody, Robert Dwayne Gossman
  • Patent number: 8525021
    Abstract: A photovoltaic cell can include a heterojunction between semiconductor layers. The first semiconductor layer can include a III-V compound semiconductor, the first semiconductor layer positioned over a transparent conductive layer. A second semiconductor layer can include a II-VI compound semiconductor, the second semiconductor layer positioned between the first semiconductor layer and a back metal contact.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: September 3, 2013
    Assignee: First Solar, Inc.
    Inventor: David Eaglesham
  • Patent number: 8519435
    Abstract: A photovoltaic cell is fabricated onto a polyimide film using an unbalanced RF magnetron sputtering process. The sputtering process includes the addition of 0.05% to 0.5% oxygen to an inert gas stream. Portions of the photovoltaic cell are exposed to an elevated temperature CdCl2 treatment which is at or below the glass transition temperature of the polyimide film.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: August 27, 2013
    Assignee: The University of Toledo
    Inventors: Anthony Vasko, Kristopher Wieland, James Walker, Alvin Compaan
  • Patent number: 8507789
    Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a substrate of a first conductive type having at least one via hole; an emitter layer only on at least a portion of the via hole and at least one selected from a group consisting of an incident surface and side surfaces of the substrate, the emitter layer having a second conductive type opposite the first conductive type; at least one first electrode on the incident surface, the first electrode being electrically connected to the emitter layer; a second electrode connected to an opposite surface to the incident surface; and at least one first electrode current collector on the opposite surface, the at least one first electrode current collector being insulated from the second electrode and being electrically connected to the at least one first electrode through the via hole.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 13, 2013
    Assignee: LG Electronics Inc.
    Inventors: Jihoon Ko, Juwan Kang, Jonghwan Kim, Daehee Jang
  • Publication number: 20130192656
    Abstract: Multi-crystalline group II-VI solar cells and methods for fabrication of same are disclosed herein. A multi-crystalline group II-VI solar cell includes a first photovoltaic sub-cell comprising silicon, a tunnel junction, and a multi-crystalline second photovoltaic sub-cell. A plurality of the multi-crystalline group II-VI solar cells can be interconnected to form low cost, high throughput flat panel, low light concentration, and/or medium light concentration photovoltaic modules or devices.
    Type: Application
    Filed: January 25, 2013
    Publication date: August 1, 2013
    Applicant: PLANT PV, Inc.
    Inventor: PLANT PV, Inc.
  • Patent number: 8492647
    Abstract: The invention provides an organic solar cell, including: a substrate having a first electrode formed thereon; a hole transport layer overlying the first electrode; a metal layer having a first pattern in the hole transport layer; a photoactive layer, including: a first organic semiconductor film having a second pattern complementary to the first pattern and overlying the metal layer and the hole transport layer; a second organic semiconductor film having a first pattern substantially aligned to the first pattern of the metal layer and overlying the first organic semiconductor film, wherein the first organic semiconductor film and the second organic semiconductor film have opposite conductive types; a second electrode overlying the photoactive layer. The invention further provides a method for forming the organic solar cell.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: July 23, 2013
    Assignee: National Taiwan University
    Inventors: Pin-Han Kuo, Chih-Kung Lee, Min-Hua Yang, Dong-Sheng Wu, Kang-Chuang Lee, Shu-Ming Hsieh, Po-Cheng Lai
  • Publication number: 20130180578
    Abstract: Methods are described for fabricating HIT solar cells, including double heterojunction and hybrid heterojunction-homojunction solar cells, with very thin single crystal silicon wafers, where the silicon wafer may be less than 80 microns thick, and even less than 50 microns thick. The methods overcome potential issues with handling these very thin wafers by using a process including epitaxial silicon deposition on a growth substrate, partial cell fabrication, attachment to a support substrate and then separation from the growth substrate. Some embodiments of the present invention may include a solar cell device architecture comprising the combination of a heterostructure on the front side of the device with a homojunction at the rear of the device. Furthermore, device performance may be enhanced by including a dielectric stack on the backside of the device for reflecting long wavelength infrared radiation.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 18, 2013
    Applicant: Crystal Solar, Incorporated
    Inventor: Crystal Solar, Incorporated
  • Publication number: 20130174895
    Abstract: A photovoltaic cell structure is disclosed that includes a buffer/passivation layer at a CdTe/Back contact interface. The buffer/passivation layer is formed from the same material that forms the n-type semiconductor active layer. In one embodiment, the buffer layer and the n-type semiconductor active layer are formed from cadmium sulfide (CdS). A method of forming a photovoltaic cell includes the step of forming the semiconductor active layers and the buffer/passivation layer within the same deposition chamber and using the same material source.
    Type: Application
    Filed: October 19, 2010
    Publication date: July 11, 2013
    Applicant: UNIVERSITY OF TOLEDO
    Inventors: Alvin D. Compaan, Victor V. Plotnikov
  • Patent number: 8481847
    Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a substrate of a first conductive type having at least one via hole; an emitter layer only on at least a portion of the via hole and at least one selected from a group consisting of an incident surface and side surfaces of the substrate, the emitter layer having a second conductive type opposite the first conductive type; at least one first electrode on the incident surface, the first electrode being electrically connected to the emitter layer; a second electrode connected to an opposite surface to the incident surface; and at least one first electrode current collector on the opposite surface, the at least one first electrode current collector being insulated from the second electrode and being electrically connected to the at least one first electrode through the via hole.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 9, 2013
    Assignee: LG Electronics Inc.
    Inventors: Jihoon Ko, Juwan Kang, Jonghwan Kim, Daehee Jang
  • Publication number: 20130167914
    Abstract: In particular embodiments, a method is described for depositing thin films, such as those used in forming a photovoltaic cell or device. In a particular embodiment, the method includes providing a substrate suitable for use in a photovoltaic device and plasma spraying one or more layers over the substrate, the grain size of the grains in each of the one or more layers being at least approximately two times greater than the thickness of the respective layer.
    Type: Application
    Filed: February 25, 2013
    Publication date: July 4, 2013
    Inventors: Brian Josef BARTHOLOMEUSZ, Michael BARTHOLOMEUSZ
  • Patent number: 8476145
    Abstract: A method to fabricate a semiconductor device, including the sequence of: implanting one or more regions on a semiconductor wafer forming a doped layer; performing a first transfer of the doped layer onto a carrier; and then performing a second transfer of the doped layer from the carrier to a target wafer; and then etching said one or more regions of the doped layer to form transistors on the doped layer.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: July 2, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Isreal Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar
  • Publication number: 20130160831
    Abstract: A method of manufacturing a solar cell including providing a substrate, depositing a first electrode over the substrate and depositing at least one p-type semiconductor absorber layer over the first electrode. The p-type semiconductor absorber layer comprises a copper indium selenide (CIS) based alloy material. The method also includes depositing by reactive sputtering an n-type In-VI semiconductor layer over the at least one p-type semiconductor absorber layer and depositing a second electrode over the n-type In-VI semiconductor layer.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: MiaSole
    Inventors: Robert Zubeck, Randy Dorn
  • Publication number: 20130164874
    Abstract: Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 27, 2013
    Applicant: Soitec
    Inventors: Chantal Arena, Robin Scott, Claudio Canizares
  • Publication number: 20130164884
    Abstract: A method and system for assembling a quasicrystalline heterostructure. A plurality of particles is provided with desirable predetermined character. The particles are suspended in a medium, and holographic optical traps are used to position the particles in a way to achieve an arrangement which provides a desired property.
    Type: Application
    Filed: February 21, 2013
    Publication date: June 27, 2013
    Applicants: The Trustee of Princeton University, New York University
    Inventors: New York University, The Trustee of Princeton University
  • Publication number: 20130157404
    Abstract: One embodiment of the present invention provides a double-sided heterojunction solar cell. The solar cell includes a lightly doped epitaxial crystalline Si (c-Si) base layer, a front-side passivation layer situated on the front side of the lightly doped epitaxial c-Si base layer, a back-side passivation layer situated on the back side of the lightly doped epitaxial c-Si base layer, a front-side emitter situated on the surface of the front-side passivation layer, a back surface field (BSF) layer situated on the surface of the back-side passivation layer, a front-side electrode, and a back-side electrode.
    Type: Application
    Filed: February 14, 2013
    Publication date: June 20, 2013
    Applicant: SILEVO, INC.
    Inventor: Silevo, Inc.
  • Publication number: 20130146133
    Abstract: A thin-film photovoltaic solar cell device is disclosed. A transparent conductive oxide (TCO) layer is disposed on a substrate as a front contact. A window layer is disposed on the TCO layer. A metal oxide layer is disposed on the window layer. An absorber layer is disposed on the metal oxide layer. A back contact layer is disposed on the absorber layer. In one embodiment, the device includes a high resistance barrier (HRT) layer interposed between the window layer and the TCO layer.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: BATTELLE MEMORIAL INSTITUTE
    Inventors: John P. Lemmon, Evgueni Polikarpov, Wendy D. Bennett
  • Patent number: 8460965
    Abstract: A manufacturing method for a solar cell including an upper electrode extracting an electrode at an incident light side, the upper electrode including a transparent conductive film, a basic structural element of the transparent conductive film being any one of an indium (In), a zinc (Zn), and tin (Sn), the manufacturing method including: a step A forming a texture on a front surface of a transparent substrate using a wet etching method, the transparent conductive film being formed on the transparent substrate, wherein in the step A, when the texture is formed, a metal thin film is formed on the transparent substrate, and an anisotropic etching is performed with the metal thin film being a mask.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: June 11, 2013
    Assignee: ULVAC, Inc.
    Inventors: Hirohisa Takahashi, Satoru Ishibashi, Kyuzo Nakamura
  • Publication number: 20130133731
    Abstract: Methods for forming a resistive transparent buffer layer on a substrate are provided. The method can include depositing a resistive transparent buffer layer on a transparent conductive oxide layer on a substrate. The resistive transparent buffer layer can comprise a cadmium doped tin oxide that has an as-deposited stoichiometry where cadmium is present in an atomic amount that is less than 33% of a total atomic amount of tin and cadmium. Zinc may also be provided in the resistive transparent buffer layer in certain embodiments. Additionally, thin film photovoltaic devices having such resistive transparent buffer layers are provided.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: PRIMESTAR SOLAR, INC.
    Inventors: Scott Daniel Feldman-Peabody, Robert Dwayne Gossman, George Theodore Dalakos, Anping Zhang, Allan Robert Northrup, Hong Piao, Laurie Le Tarte
  • Publication number: 20130130431
    Abstract: An alloy composition for a subcell of a solar cell is provided that has a bandgap of at least 0.9 eV, namely, Ga1-xInxNyAs1-y-zSb, with a low antimony (Sb) content and with enhanced indium (In) content and enhanced nitrogen (N) content, achieving substantial lattice matching to GaAs and Ge substrates and providing both high short circuit currents and high open. circuit voltages in GaInNAsSb subcells for multijunction solar cells. The composition ranges for Ga1-xInxNyAs1-y-zSbz are 0.07?x?0.18, 0.025?y?0.04 and 0.001?z?0.03.
    Type: Application
    Filed: January 11, 2013
    Publication date: May 23, 2013
    Applicant: Solar Junction Corp.
    Inventor: Solar Junction Corp.
  • Publication number: 20130122640
    Abstract: Provided is a manufacturing method of a semiconductor quantum dot-sensitized solar cell. More particularly, the manufacturing method according to the present invention includes: a quantum dot forming step of forming a semiconductor layer containing a group 4 element and InP on a substrate and then performing heat-treatment on the substrate including the semiconductor layer formed thereon to remove indium (In) therefrom, thereby forming an n-type semiconductor quantum dot, which is a group 4 element quantum dot doped with phosphorus (P).
    Type: Application
    Filed: July 2, 2010
    Publication date: May 16, 2013
    Applicant: KOREA RESEARCH INSTITUTE OF STANDARDS AND SCIENCE
    Inventors: Kyung Joong Kim, Seung Hui Hong, Jae Hee Park, Woo Lee
  • Publication number: 20130112265
    Abstract: One embodiment of the present invention provides a heterojunction solar cell. The solar cell includes a metallurgical-grade Si (MG-Si) substrate, a layer of heavily doped crystalline-Si situated above the MG-Si substrate, a layer of lightly doped crystalline-Si situated above the heavily doped crystalline-Si layer, a backside ohmic-contact layer situated on the backside of the MG-Si substrate, a passivation layer situated above the heavily doped crystalline-Si layer, a layer of heavily doped amorphous Si (a-Si) situated above the passivation layer, a layer of transparent-conducting-oxide (TCO) situated above the heavily doped a-Si layer, and a front ohmic-contact electrode situated above the TCO layer.
    Type: Application
    Filed: September 25, 2012
    Publication date: May 9, 2013
    Applicant: SILEVO, INC.
    Inventor: SILEVO, INC.
  • Publication number: 20130112263
    Abstract: A solar cell. The solar cell includes a substrate, a first layer comprising a first copper-based material deposited upon the substrate, the first copper-based material electrically attracted to the substrate or to a first optional deposit layer deposited between the substrate and the first layer, and a second layer comprising a second copper-based material deposited upon the first layer or an second optional deposit layer deposited between the first layer and the second layer, the second copper-based material electrically attracted to the first layer or to the second optional deposit layer, wherein the first copper-based material and the second copper-based material are selected from the group consisting of copper indium gallium (di)selenide (CIGS), copper indium selenium (CIS), and cadmium sulfate (CdS).
    Type: Application
    Filed: July 27, 2011
    Publication date: May 9, 2013
    Applicant: INDIANA UNIVERSITY RESEARCH AND TECHNOLOGY CORPORATION
    Inventors: Mangilal Agarwal, Khodadad Varahramyan, Sudhir Shrestha
  • Publication number: 20130112275
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 9, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20130109124
    Abstract: In one aspect of the present invention, a method is included. The method includes thermally processing an assembly to form at least one transparent layer. The assembly includes a first panel including a first layer disposed on a first support and a second panel including a second layer disposed on a second support, wherein the second panel faces the first panel, and wherein the first layer and the second layer include substantially amorphous cadmium tin oxide. Method of making a photovoltaic device is also included.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 2, 2013
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Hongying Peng, Juan Carlos Rojo, Hongbo Cao, George Theodore Dalakos, Holly Ann Blaydes, David William Vernooy, Mark Jeffrey Pavol, Jae Hyuk Her, Hong Piao, Robert Dwayne Gossman, Scott Daniel Feldman-Peabody, Yangang Andrew Xi
  • Publication number: 20130104972
    Abstract: Provided is a Se- or S-based thin film solar cell, including a substrate, a rear electrode formed on the substrate, a light absorbing layer formed on the rear electrode and containing at least one of selenium (Se) and sulfur (S), and an rear electrode top layer. The rear electrode top layer is formed between the rear electrode and the light absorbing layer, and contains a large amount of oxygen (O) to control diffusion of sodium (Na) through the rear electrode to the light absorbing layer. In this manner, it is possible to improve the electrical conductivity and interfacial adhesion of the rear electrode while stimulating diffusion of sodium (Na) to improve the efficiency of a thin film solar cell.
    Type: Application
    Filed: August 1, 2012
    Publication date: May 2, 2013
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jeung Hyun JEONG, Ju Heon YOON, Won Mok KIM, Young Joon BAIK, Jong Keuk PARK
  • Patent number: 8431817
    Abstract: Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may be a multi junction solar cell. The optoelectronic device may have a bi-layer electrical interconnect that is physically and electrically connected to sidewalls of the array of nanostructures. The optoelectronic device may be operated as a multi junction solar cell, wherein each junction is associated with one portion of the device. The bi-layer electrical interconnect allows current to pass from one portion to the next. Thus, the bi-layer electrical interconnect may serve as a replacement for a tunnel junction, which is used in some conventional multi junction solar cells.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: April 30, 2013
    Assignee: Sundiode Inc.
    Inventors: James C. Kim, Sungsoo Yi, Danny E. Mars
  • Publication number: 20130099249
    Abstract: An ultraviolet light sensor and method of manufacturing thereof are disclosed. The ultraviolet light sensor includes Group-III Nitride layers adjacent to a silicon wafer with one of the layers at least partially exposed such that a surface thereof can receive UV light to be detected. The Group-III Nitride layers include a p-type layer and an n-type layer, with p/n junctions therebetween forming at least one diode. Conductive contacts are arranged to conduct electrical current through the sensor as a function of ultraviolet light received at the outer Group-III Nitride layer. The Group-III Nitride layers may be formed from, e.g., GaN, InGaN, AlGaN, or InAlN. The sensor may include a buffer layer between one of the Group-III Nitride layers and the silicon wafer. By utilizing silicon as the substrate on which the UV sensor diode is formed, a UV sensor can be produced that is small, efficient, cost-effective, and compatible with other semiconductor circuits and processes.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 25, 2013
    Applicant: ROSESTREET LABS, LLC
    Inventor: RoseStreet Labs, LLC
  • Patent number: 8415761
    Abstract: Exemplary embodiments of the invention include a thermoelectric material having an aligned polarization field along a central axis of the material. Along the axis are a first atomic plane and a second atomic plane of substantially similar area. The planes define a first volume and form a single anisotropic crystal. The first volume has a first outer surface and a second outer surface opposite the first outer surface, with the outer surfaces defining the central axis passing through a bulk. The bulk polarization field is formed from a first electrical sheet charge and a second opposing electrical sheet charge, one on each atomic plane. The opposing sheet charges define a bulk polarization field aligned with the central axis, and the bulk polarization field causes asymmetric thermal and electrical conductivity through the first volume along the central axis.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: April 9, 2013
    Assignee: Carrier Corporation
    Inventor: Joseph V. Mantese