Abstract: There is provided a bias power supply for setting a collector bias current of a mixer transistor and a collector bias current of an oscillation transistor. When a control voltage is equal to or smaller than a first predetermined value, an output voltage of the bias power supply is set to be increased so that at least one of the collector bias current of the mixer transistor and the collector bias current of the oscillation transistor can be increased.

Abstract: A carrier recovery method and apparatus using multiple stages of carrier frequency recovery are disclosed. A receiver uses multiple frequency generation sources to generate carrier signals used to downconvert a received signal. An analog frequency reference having a wide frequency range and coarse frequency resolution is used in conjunction with a digital frequency reference having a narrow frequency range and fine frequency resolution. The multiple carrier signals are multiplied by a received signal to effect a multi-stage downconversion, resulting in a baseband signal. A frequency tracking module measures the residual frequency error present in the baseband signal. The measured residual frequency error is then used to adjust the frequencies of the carrier signals generated by the multiple frequency generation sources.

Abstract: A disclosed method tunes a signal from a channelized spectrum having a predetermined channel spacing. A signal of interest having a predetermined maximum bandwidth is mixed with a local oscillator signal, which has a frequency that is an integer multiple of the channel spacing or one-half of a channel spacing displaced from an integer multiple of the channel spacing. The local oscillator signal is selected to frequency translate the signal of interest to within a near-baseband passband whose lower edge is spaced from DC by at least about the maximum bandwidth of the signal of interest. Problems associated with 1/f noise, DC offsets, and self-mixing products are avoided or substantially diminished. Other methods and systems are also disclosed.

Abstract: A receiver receives an RF-band modulated signal transmitted from a transmitter, as well as an un-modulated carrier also transmitted from the transmitter and having a phase noise characteristic coherent with that of the modulated signal, and a product of the two components is generated to thereby restore an IF-band transmission source signal. In the receiver, a small planar antenna having a broad beam characteristic such as a single-element patch antenna is combined with an amplifier and a mixer circuit, which are formed on a micro planar circuit by an MMIC technique, so as to form a unit receiving circuit. A plurality of such unit receiving circuits are disposed on the receiver at intervals smaller than a wavelength corresponding to an IF band, and detection outputs from the unit receiving circuits are power-mixed. Thus, the receiver serves as a high-gain antenna having a detection function, and can realize a broad beam radiation characteristic comparable to that of a single-element antenna.

Abstract: A receiver (100) includes a mixing digital-to-analog converter (DAC) (120), a direct digital frequency synthesizer (DDFS) (116), and a clock circuit (114). The mixing DAC (120) includes a radio frequency (RF) transconductance section (124) and a switching section (128). The RF transconductance section (124) includes an input configured to receive an RF signal. The switching section is coupled to the RF transconductance section (124) and includes inputs, configured to receive bits associated with a digital local oscillator (LO) signal, and an output. The DDFS (116) includes outputs, configured to provide the bits associated with the digital LO signal to the inputs of the switching section (128), and a first clock input, configured to receive a first clock signal that sets a sample rate for the digital LO signal The clock circuit (114) is configured to provide the first clock signal to the first clock input of the DDFS (116) at a frequency that is based on a selected channel.

Abstract: Determination and processing for fractional-N programming values. The present invention is operable to receive a clock signal (CLK) and to transform that CLK into a new CLK, when necessary, for use by various circuitries within a system. The present invention is operable to generate two different CLKs for use by a radio frequency (RF) circuitry and a baseband processing circuitry in certain embodiments. The present invention employs a measurement circuitry and to characterize a first CLK and uses a fractional-N synthesizer to perform any necessary processing to generate the one or more CLKs to the other CLKs within the system. The first CLK may be received from an external source or it may be generated internally; in either case, the present invention is able to modify the CLK into another CLK for use by other circuitries within the system or for use by another external device.

Abstract: An apparatus is provided, for reducing power consumption in a system operating in a power saving mode, comprising a controller, an oscillator circuit and a voltage regulator. The controller provides a first control signal and a second control signal. The oscillator circuit, connected to the controller, wherein the controller controls the oscillator circuit according to the second control signal. The voltage regulator providing electric power to the oscillator circuit, connected to the controller, wherein the controller controls the voltage regulator according to the first control signal.

Abstract: A time constant automatic adjusting circuit comprises: a filter circuit varying a phase of an clock signal to be input so as to output the clock signal; a phase comparison circuit comparing a phase of an output signal of the filter circuit with the phase of the clock signal, and outputting a predetermined voltage when the phase of the output signal and the phase of the clock signal are the same; at least three comparators comparing the output voltage with a plurality of different voltages; an up-down counter counting a number of output bits of either one of the at least three different voltages in accordance with an output result of the comparators; and a control circuit varying the time constant of the filter circuit in accordance with the number of output bits counted by the up-down counter.

Abstract: A method and apparatus for generating a phase-locked output signal includes generating an intermediate signal phase locked to an input signal by frequency dividing the intermediate signal by a temporally-varying divide ratio sequence to generate a first feedback signal and phase comparing the first feedback signal with the input signal. An output signal is generated phase locked to the first feedback signal by frequency dividing the output signal by the temporally-varying divide ratio sequence to generate a second feedback signal and phase comparing the second feedback signal with the first feedback signal.

Abstract: A method for processing signals is disclosed and may include performing using one or more circuits in a multiband radio, functions including receiving an input signal from an oscillator that generates signals for each of a plurality of bands handled by the multiband radio. The received input signal may be divided. A feedback loop reference signal may be generated from the input signal. A coarse calibration signal and/or a fine calibration signal may be generated from the generated feedback loop reference signal. The oscillator may be calibrated utilizing the coarse calibration signal and/or the fine calibration signal. The input signal generated by the oscillator may be between about 3.4 GHz and 4 GHz. The receive input signal may be buffered. The generated feedback loop reference signal may also be buffered.

Abstract: A semiconductor device for a tuner generates a local oscillation signal inside or selects a local oscillation signal introduced from the outside, and controls the power consumption of the circuit used for generating the local oscillation signal. The diversity receiver constituted using the semiconductor device has semiconductor device 1 selected to generate a local oscillation signal inside and semiconductor device 2 selected to introduce a local oscillation signal from the outside. The local oscillation signal of the semiconductor device 2 is driven by the local oscillation signal of the semiconductor device 1. Consequently, any unnecessary power consumption of the circuit generating the local oscillation signal of semiconductor device 2 can be reduced. In addition, since they are the same type of semiconductor device, the uniformity of the operating characteristics of the diversity receiver can be improved.

Abstract: A tuner architecture is disclosed that mixes an analog RF input signal and a digital local oscillator signal to generate a output signal at a desired IF frequency, including low-IF and zero-IF solutions. The tuner provides a number of advantages over previous implementations, such as improved performance for low-IF and zero-IF architectures and a significant reduction in interference between adjacent paths in a multiple tuner solution. Other features and variations can be implemented, if desired, and related methods can be utilized, as well.

Abstract: A receiver apparatus includes a preamplifier to amplify an input signal, an equalizer configured to subject an amplified signal to an equalization process, an identification reproducer to reproduce the input signal based on an output signal of the equalizer, and a magnetic oscillator arranged on a pre-stage of the preamplifier to improve a SN ratio of the input signal.

Abstract: A mobile radio terminal includes a system clock having a controller, a frequency generator for outputting a clock signal and a temperature sensor for detecting an operating temperature of the frequency generator. The controller adjusts a frequency of the clock signal by inputting a frequency generator control value associated with the detected operating temperature to the frequency generator. A control circuit that manages overall operation of the mobile radio terminal is configured to place the mobile radio in one of plural operational modes and the clock signal is used to clock an electrical component activated in connection with the one of the operational modes.

Abstract: A receiver includes a receiver clock oscillator controllable with regard to its receiver oscillator frequency, means for detecting a number of clock periods that the receiver clock oscillator performs in a specifiable period of time, means for extracting a first and a temporally following second reference entry in a received data stream, wherein means for extracting is implemented in order to control means for detecting on the basis of the extracted first and second reference entry with regard to the specifiable period of time, and means for comparing the number of clock periods of the receiver clock oscillator with the information in the second reference entry in order to control the controllable oscillator depending on a comparison result so that the oscillator frequency is increased or decreased so that the oscillator frequency is in a predetermined ratio to a frequency of the clock oscillator in the transmitter or is equal to the frequency of the clock oscillator in the transmitter.

Abstract: An active inductor includes bipolar transistors T1, T2, T3 and TD (TD being arranged in diode), where T1's emitter is connected to an output port and to T2's collector. T2's base is connected to a first voltage line and between two connected capacitors. T2's emitter is connected to T3's collecter. An end of one capacitor is connected to T1's base and to a second voltage line. An end of the other capacitor is connected to T3's emitter and to a third voltage line. T1's collector is connected to a fourth voltage line and to TM's collecter, which is connected to TM's base. TM's emitter is electrically connected to T3's base. Preferably, the transistors T1-T3 and TD are Silicon based, and the active inductor is fabricated on a single substrate comprising Silicon. The active inductor is incorporated into adaptive oscillators and amplifiers and an improved transceiver.

Abstract: The present invention is related to a method and apparatus for automatic frequency correction of a local oscillator. The apparatus receives a carrier signal. The carrier signal includes a code sequence known to the apparatus. The apparatus downconverts the carrier signal to a baseband signal using the local oscillator. The apparatus performs a block correlation of the samples of the baseband signal with the known code sequence to generate a frequency error signal. The frequency error signal is fed back to the local oscillator to correct the frequency error.

Abstract: Circuitry is provided to drive a step recovery diode (SRD) (8) in a sampler based vector network analyzer (VNA) that allows harmonic samplers (10, 11) to operate over many octaves. The circuit includes a digital pulse generator (FIG. 5) for providing a LO signal. The LO signal is provided over an octave frequency range as in previous SRD driver circuits, but pulse forming circuitry is provided to decrease the pulse rate to a sub multiple of the LO generating oscillator signal. The pulse forming circuitry includes a programmable frequency divider (50) to vary the pulse rate. The pulse forming network further includes registers (50, 52) connected to the programmable frequency divider (50) to limit the pulse width resulting in reduced heating of the SRDs. With an effectively wider frequency operation range using the SRD (8), only one downconversion is required in the VNA, eliminating the need for additional mixers (30, 31) and a second LO signal generator (24) to provide a second downconversion.

Abstract: A communications subsystem for a wireless device for correcting errors in a reference frequency signal. The communications subsystem comprises a frequency generator for generating the reference frequency signal and a closed loop reference frequency correction module that generates a reference frequency adjustment signal for correcting the reference frequency signal when the communications subsystem operates in closed loop mode. The subsystem further includes an open loop frequency correction means that that samples values of the reference frequency adjustment signal during the closed loop mode and generates a frequency correction signal for correcting the reference frequency signal when the communications subsystem operates in a mode other than closed loop mode.

Abstract: Methods and systems for processing signals for a multiband radio are disclosed herein. Aspects of the method may comprise dividing an input signal generated by an oscillator used to generate signals for each of a plurality of bands for the multiband radio. A feedback loop reference signal may be generated from the input signal and a coarse calibration signal may be generated from the feedback loop reference signal. The oscillator may be calibrated utilizing the coarse calibration signal. The input signal may be buffered and/or divided by a divide by four (4) divider circuit. The input signal generated by the oscillator may be between about 3.4 GHz and 4 GHz. The generated feedback loop reference signal may be buffered and/or divided prior to the calibration. The coarse calibration signal may comprise a 7-bit calibration signal. A fine calibration signal may be generated from the feedback loop reference signal.

Abstract: An oscillation device, includes: an oscillator circuit that generates an oscillation signal based on a direct current voltage to be inputted, the oscillation signal being provided with a specification requested by a supplied device that is supposed to receive a supply of the oscillation signal; a gate circuit provided in the subsequent stage of the oscillator circuit and capable of outputting the oscillation signal from the oscillator circuit towards the supplied device; a power supply monitor circuit for detecting that the direct current voltage to be inputted has reached a voltage at which the oscillator circuit is able to start to generate the oscillation signal; and a delay circuit that causes the gate circuit to output to the supplied device the oscillation signal from the oscillator circuit, when a time required for the state of the oscillation signal, which the oscillator circuit generates, to become substantially constant is clocked on the basis of a time when a notice of the detection is received fro

Abstract: A hopping control device selects one hopping pattern out of hopping patterns P1 to PN, reads out a hopping frequency sequence arranged in the selected hopping pattern from a frequency hopping pattern memory, and sends the hopping frequency sequence to frequency synthesizers as a frequency designation signal by wire at a predetermined period. The frequency synthesizers generate local oscillation signals of a frequency specified by the frequency designation signal, respectively, and output the local oscillator signals to mixers, respectively, to thereby perform communication by a frequency hopping system between a first housing unit and a second housing unit.

Abstract: A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.

Abstract: VCO (voltage-controlled oscillator) device used for a radio unit such as a television broadcast receiver. A VCO device oscillating in a wide band of oscillation frequency and capable of realizing low power consumption is provided. VCO circuit group 4 oscillates signals of frequencies corresponding to control voltage Vt applied to frequency control voltage terminal 8. LO signal selecting means 3 selects a required output signal from VCO circuit group 4. PLL 6 frequency-divides local signal fvco selected by LO signal selecting means 3, compares a phase thereof with a phase of a reference signal and outputs a signal converted from a phase difference. Loop filter 7 smoothes the output signal from PLL 6, outputs control voltage Vt that is a frequency control voltage and outputs the local-signal selected by signal selecting means 3 to high frequency signal processing means 1.

Abstract: Integrated multiple tuner architectures and associated methods are disclosed that utilize frequency isolated local oscillators (LO). These architectures utilize dividers and multipliers within the signal paths for the local oscillator mixing signals to reduce interference among the multiple local oscillators operating on a single integrated circuit. A multiple tuner direct-down-conversion (DDC) receiver and a multiple tuner intermediate frequency (IF) receiver are provided as example embodiments. And an example integrated multi-tuner satellite receiver is also described.

Abstract: In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.

Abstract: A dual frequency synthesizer includes a reference oscillator, an R counter, a first fractional-N phase-locked loop (for a receiving channel) and a second fractional-N phase-locked loop (for a transmitting channel) and one shared sigma-delta modulator. The reference oscillator outputs a reference oscillation frequency clock. The R counter outputs a reference frequency clock based on the reference oscillation frequency clock. The first fractional-N phase-locked loop (PLL) (for a receiving channel) generates a first (receiving channel frequency) clock based on the reference frequency clock. The second fractional-N phase-locked loop (for a transmitting channel) generates a second (transmitting channel frequency) clock based on the same reference frequency clock. Both fractional-N phase-locked loops share a common sigma-delta modulator. Therefore, the chip size of the dual frequency synthesizer may be reduced.

Abstract: A phase locked loop (PLL) circuit (1) comprising a loop input (11); a phase detector section (2) for detecting a phase difference between an input signal and a reference signal. The phase detector section (2) has a detector input connected to the loop input, a reference input and a detector output for outputting a signal related to the phase difference. A controlled oscillator (4) is connected with an input to the detector output and an oscillator output is connected to a loop output (12). The PLL has a feedback circuit which connects the oscillator output to the reference input, wherein the feedback circuit includes a device (7;71-74) having a transfer function with at least one zero.

Abstract: In one embodiment, a PLL circuit is provided with a plurality of pull-in operation modes for pulling a voltage across a filter capacitor (C1, C2) in a lock-up voltage, and with a register (CRG) for designating one of the plurality of pull-in operation modes. The pull-in operation is performed in accordance with a setting value in the register.

Abstract: A differential and quadrature harmonic voltage controlled oscillator (VCO), and a method for generating a differential and quadrature harmonic signal. The VCO may include a first oscillation unit for generating a first and a third signal, a first combining unit for combining the first and the third signal, a second oscillation unit for generating a second and a fourth signal, and a second combining unit for combining the second and the fourth signal. The phase of the second signal is determined through a phase-invert and delay using the first signal, the phase of the third signal is determined through a phase-invert and delay using the second signal, the phase of the fourth signal is determined through a phase-invert and delay using the third signal, and the phase of the first signal is determined through a phase-invert and delay using the fourth signal.

Abstract: An apparatus and method to use a single voltage controlled oscillator (VCO) to generate frequencies to cover multiple frequency bands. The single VCO generates local oscillator signals for more than one frequency band of a communication standard or protocol, such as the IEEE 802.11 standard.

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock.

Abstract: An oscillation circuit for generating two oscillation signals having a phase difference of 90° by using an LC oscillator has a disadvantage for integration. Therefore, a differential type ring oscillator comprising interpolation type delay circuits of four stages is used as an original oscillator without using any LC oscillator. The oscillation frequency of the original oscillator is set to f/2. Intermediate signals S(k) having a phase difference of 45(k?1)° with respect to a reference phase are obtained as the outputs of the respective stages of the original oscillator. A multiplying circuit 22 generates the product signal of S(2) and S(4) in mixers. This product signal is vibrated at cos (ft/2), and the output signal Vout1 is generated on the basis of the product signal. A multiplying circuit generates the product signal of S(1) and S(3) in mixers. This product signal is vibrated at cos(ft/2+?/2), and the output signal Vout2 is generated on the basis of the product signal.

Abstract: A numerical control oscillator (NCO) for reducing a circuit size and power consumption while maintaining a desired frequency deviation, and suppressing generation of a spurious as much as possible. The NCO comprises a phase accumulator for accumulating input phase difference data to generate phase data, and a read only memory (ROM) for storing a phase/amplitude conversion table to output amplitude data corresponding to the phase data generated by the phase accumulator. The phase accumulator includes a phase register and a phase calculator. If a sampling frequency of an output signal from the NCO is Fs, the upper limit of a desired frequency setting interval of the output signal is FD and K and L are arbitrary integers, the phase calculator adds or subtracts the input phase difference data and phase data from the phase register to or from each other by a modulo operation taking the nearest integer of M as a modulus, where M=Fs/FD×K/L.

Abstract: A portable radio terminal for realizing automatic frequency control (AFC) for automatically controlling the oscillation frequency of an oscillator includes a unit for intermittently performing AFC operation, and a unit for shortening an AFC operation stop period when the frequency shift of the oscillation frequency is large. An AFC control method is also disclosed.

Abstract: In a mobile communication device, a method for compensating for a frequency adjustment in an oscillator shared between a communication circuit and a positioning signal receiver is provided. In one embodiment, a method for determining the operating frequency of an oscillator detects a beginning time point of a reference signal received by the mobile communication device and enables a counter to count in step with a clock signal derived from the oscillator. When an ending time point of the reference signal is received by the mobile communication device, the count is stopped, and the frequency of the oscillator is determined based on the count in the counter and an expected time that elapsed between the beginning time point and the ending time point.

Abstract: A system and method are disclosed for dynamically selecting high-side injection or low-side injection of local oscillator mixing signals based upon an assessment of signal power within the input signal spectrum that could cause unwanted images in the processed signal. This image rejection assessment provides an advantageous basis upon which to make dynamic high-side versus low-side injection determinations.

Abstract: A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.

Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.

Abstract: The invention relates to a tuner for converting a radio frequency signal into an intermediate frequency signal, said tuner comprising a voltage converter supplying a control signal, a mixer associated with an oscillator which is voltage-controlled by said control signal. The invention is characterized in that said voltage converter comprises: an auto-oscillating circuit generating an alternating voltage signal of a variable level, rectifying means for supplying a direct voltage signal of a variable level based on said alternating voltage signal of a variable level, an additional circuit for reducing the variations of the attenuation coefficient of said auto-oscillating circuit, said additional circuit receiving said direct voltage signal of a variable level and supplying said control signal. The invention provides an inexpensive solution having an improved performance in terms of spectral purity, ease of implementation and stability of control of said intermediate frequency signal.

Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.

Abstract: A super-regenerative receiver uses controlled Q-quenching and may limit the resonant tank circuit amplitude by loading the tank circuit as soon as regenerative oscillation is detected. An amplitude detector is coupled to the regenerative amplifier and controls a Q loading circuit coupled to the tank circuit of the regenerative amplifier. The amplitude detector turns on the Q loading circuit which then stops the regenerative amplifier from oscillating, and the Q-loading remains on for a brief time to insure that the regenerative amplifier has stopped oscillating. After the brief time, the Q loading circuit is turned off and the regenerative amplifier goes into oscillation again. This cycle repeats controllably over and over, resulting in a lower self-induced noise floor and improved received signal sensitivity.

Abstract: Systems and techniques are disclosed relating to wireless communications. These systems and techniques involve wireless communications wherein a device may be configured to recover an information signal from a carrier using a reference signal, detect a frequency error in the information signal; and periodically tune the reference signal to reduce the frequency error.

Abstract: A combination mobile phone and navigation satellite receiver comprises a circuit for correcting GPS receiver reference frequency drift by using VCO burst information periodically received by a PDC handset. A corrected GPS receiver reference frequency drift then enables faster initialization and stable operation of the position solutions made available to users. A GPS numeric controlled oscillator (NCO) receives a PDC handset VCO sample.

Abstract: A method of receiving an FM digital audio broadcasting signal including a first plurality of subcarriers in an upper sideband of a radio channel and a second plurality of subcarriers in a lower sideband of the radio channel comprises the steps of mixing the digital audio broadcasting signal with a local oscillator signal to produce an intermediate frequency signal, passing the intermediate frequency signal through a bandpass filter to produce a filtered signal, determining if one of the upper and lower sidebands of the digital audio broadcasting signal is corrupted, and adjusting the local frequency oscillator signal to change the frequency of the intermediate frequency signal such that the bandpass filter removes the subcarriers in the upper or lower sideband that has been corrupted. A receiver that processes a digital audio broadcasting signal in accordance with the method is also provided.

Abstract: An architecture for providing high-speed access over frequency-division multiplexed (FDM) channels allows transmission of ethernet frames and/or other data across a cable transmission network or other form of FDM transport. The architecture involves downstream and upstream FDM multiplexing techniques to allow contemporaneous, parallel communications across a plurality of frequency channels. Moreover, an automatic frequency control resolves some issues of a free-running clock in an upstream tuner of the central concentrator by performing adjustments based on the average frequency error of a number of active upstream tones. In the preferred embodiments of the present invention, the automatic frequency control (AFC) utilizes a feedback loop for at least each active upstream tone. Also, the average of the active upstream tones is determined and is utilized in providing feedback to adjust the automatic frequency control (AFC).

Abstract: A digital television receiver includes a tuner for down-converting an incoming signal to produce a down-converted signal according to a local oscillator signal corresponding to a selected channel. A filter is coupled to the tuner for filtering the down-converted signal to produce an intermediate frequency (IF) signal. A carrier recovery unit is coupled to the filter for locking to a carrier frequency of the IF signal, and a pre-shift unit is coupled to the tuner. By shifting the local oscillator signal in a first direction by a predetermined first frequency shift in a first phase of carrier recovery, and then by shifting the local oscillator signal in a second direction by a second frequency shift in a second phase of carrier recovery, the pre-shift unit ensures a pilot tone of a selected channel is not filtered from the down-converted signal by the filter.

Abstract: A power management scheme for a wireless communications device substantially implemented on a single CMOS integrated circuit is described. The present invention provides a method and apparatus for generating first and second clock signals for a wireless communication device, with the first and second clock signals corresponding first and second power levels, depending on the operating mode of the wireless communication unit. In the first operating state, the transceiver in the RF analog module is operational and the clock generator provides a first clock signal having the high-speed, high-accuracy characteristics necessary to maintain efficient operation of the transceiver. In a second operating state, the transceiver in the RF analog module is turned off. In this second operational state, the clock generator provides a second clock signal having a frequency and quality sufficient to maintain efficient operation of the digital modules in the wireless communication device.

Abstract: A direct conversion receiver includes a local oscillator for generating a sinusoid, a mixer for receiving an incoming signal and for mixing the incoming signal with the sinusoid, an analog-to-digital converter for converting the mixed analog signal into a digital signal, and a digital signal processor for outputting the digital signal so that an I-channel signal and a Q-channel signal are output separately and for transmitting to the local oscillator a phase control signal that determines the phase of a sinusoid to be generated by the local oscillator. The direct conversion receiver may further include a low noise amplifier for amplifying the incoming while preventing noise included in the input signal from being amplified, a baseband amplifier for amplifying the mixed analog signal in a baseband, and a baseband low pass filter for removing low frequency noise from a signal amplified by the baseband amplifier.

Abstract: A circuit provides a reduced harmonic content output signal OUTA and/or OUTB that is modulated according to an input signal 231. The circuit has an oscillator circuit 210 and a harmonic rejection mixer (HRM) 230. The oscillator circuit 210 includes at least one “circuit portion” (FIG. 2A) configured to receive first and second orthogonal oscillator input signals (two of I, I?, Q, Q?) having respective first and second phases, and to provide an arbitrarily large number of oscillator output signals (?M) having respective mutually distinct phases that are interpolated between the first and second phases. Harmonic rejection mixer 230 is configured to use the input signal to modulate a combination of the oscillator output signals, the oscillator output signals being respectively weighted so as to provide an emulated sinusoidal signal constituting the reduced harmonic content output signal.