Phase Lock Loop Or Frequency Synthesizer Patents (Class 455/260)
  • Patent number: 10763781
    Abstract: A system and method of performing temperature compensation based on temperature of a crystal. An integrated circuit includes a clock circuit, a memory, an interface developing a sense voltage indicative of a temperature of the crystal, and a controller. The memory stores compensation values including nominal values based on a nominal third order polynomial that defines a nominal frequency versus temperature relationship of a crystal design representing multiple crystals, and a pair of adjustment values derived from two temperature-frequency error points. The controller determines a temperature value based on the sense voltage, calculates a frequency offset using the temperature value and the compensation values to solve a compensated third order polynomial defining a compensated frequency versus temperature relationship of the crystal, and adjusts a clock signal of the clock circuit using the frequency offset. A Wi-Fi device may be optimized for industrial IoT operating within an extended temperature range.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 1, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Thomas Edward Voor, Jeffrey A. Tindle, Euisoo Yoo, Wei Shen
  • Patent number: 10749662
    Abstract: A receiver system that includes a clock and data recovery (CDR) system for aligning a local clock signal to an incoming data signal to extract correct timing information from the incoming data signal is provided. A timing error detector generates an output phase error signal representing the phase difference between the incoming data signal and the local clock signal. The timing error detector determines the phase difference according to recovered symbols and the difference between the recovered symbols and digital samples of the incoming data signal. The digital samples of the incoming data signal include intersymbol interference. The output timing information is suitable for aligning the local clock signal to the incoming data signal.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: August 18, 2020
    Assignee: INPHI CORPORATION
    Inventor: Fernando De Bernardinis
  • Patent number: 10694467
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may support dynamic clock switching within a transmission time interval (TTI) to allow for more efficient and flexible processing within the TTI. In particular, a user equipment (UE) may be configured to use multiple clock speeds for processing signals within a TTI, and the UE may determine a clock speed to use for processing data within a TTI based on control information received from a base station. For example, the UE may determine an amount of time available for processing data based on the control information received from the base station, and the UE may adjust its clock speed to finish processing the data in the determined amount of time.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: June 23, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Hari Sankar, Alexei Yurievitch Gorokhov, Michael Lee McCloud, Li Zhang, Brian Clarke Banister, Jittra Jootar, Joseph Binamira Soriaga, Afshin Shiravi
  • Patent number: 10603750
    Abstract: A mounting system having a dual plunger arrangement wherein the side of each plunger has a pull down cam to provide a desired pull down action in relation to at least two studs, the cams moving relative to one another and axially aligning relative to one another relative to the two axially spaced pull down studs to allow the plungers to provide a maximum hold down force for the two pull down studs, balance the hold down forces thereby maximizing performance and reducing unlocking forces.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 31, 2020
    Assignee: Jergens, Inc.
    Inventors: Darel R. Taylor, Terry Schron, Edward Conaway
  • Patent number: 10355702
    Abstract: A hybrid PLL is provided that includes an digital integral path and an analog proportional path.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Zhuo Gao, Bupesh Pandita, Eskinder Hailu
  • Patent number: 10084483
    Abstract: Techniques for interleaving information for media data are described. In at least some embodiments, interleaving information is propagated from a network-based service to endpoint devices that participate in communication sessions. The endpoint devices may utilize the interleaving information to interleave media data of communication sessions.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: September 25, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Amer Aref Hassan, Andrew Nicholas Paul Smith
  • Patent number: 10041292
    Abstract: A low-power RF receiver has a decreased current consumption. The receiver may be used in control devices, such as battery-powered motorized window treatments and two-wire dimmer switches. The receiver uses an RF sub-sampling technique to check for RF signals and then puts the receiver to sleep for a sleep time that is longer than a packet length of a transmitted packet to conserve battery power. The receiver compares detected RF energy to a threshold that may be increased to decrease the sensitivity of the receiver and increase the battery lifetime. After detecting an RF signal, the receiver is put to sleep for a snooze time that is longer than the sleep time and just slightly shorter than the time between two consecutive transmitted packets.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: August 7, 2018
    Assignee: Lutron Electronics Co., Inc.
    Inventors: Andrew Karl Cooney, Jordan H. Crafts, Stuart W. Dejonge, Galen E. Knode, Jonathan T. Lenz, Justin J. Mierta, Donald R. Mosebrook
  • Patent number: 10044358
    Abstract: A loop filter with an active discrete-level loop filter capacitor can be used in a VCO (such as for CDR). A loop filter capacitor function is simulated by sensing input loop filter current (such as with a current mirror and source follower in the input leg), and forcing back a loop filter (VCO) control voltage. Loop filter voltage control is provided using a VDAC with a discrete-level VDAC feedback voltage, incremented/decremented based on the sensed loop filter current. In one embodiment, the VDAC voltage is provided as the non-inverting input to an amplifier, with the inverting input providing the control voltage, forced to the VDAC feedback voltage. The VDAC feedback voltage can be provided by increment/decrement comparators based on a voltage deviation on a C2 capacitor (from a reference voltage) that receives the sensed loop filter current (effectively multiplying the C2 capacitance to provide a simulated loop filter capacitance).
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: August 7, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Steven Ernest Finn
  • Patent number: 9966986
    Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: May 8, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shih-Chi Shen, Shao-Wei Feng, Chun-Ming Kuo, Chi-Hsueh Wang, Ang-Sheng Lin
  • Patent number: 9892649
    Abstract: The invention provides an audio noise reduction circuit, an intelligent terminal and a teaching method using this audio noise reduction circuit, where a dual microphone array is used for abatement of noise, ICA algorithm is used for blind source analysis; the audio noise reduction circuit is used to realize the extraction and separation of voice and improve the voice quality in noisy environment, so that the user can also obtain clear voice communication or recording effect even in noise environment; through real-time acquisition and recording of the audio information of teacher, the invention realizes the real-time recording of teaching voice data and solves the following problem: when the learning content is preset in the intelligent terminal, the learning experience is relatively monotonous, leading to unsatisfactory results of learning.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: February 13, 2018
    Assignee: SHENZHEN EAGLESOUL TECHNOLOGY CO., LTD.
    Inventor: Qiwei Lu
  • Patent number: 9882661
    Abstract: Methods and systems for calibrating a transceiver using frequency separation are disclosed. A method configured to calibrate a transceiver that includes connecting an output of a transmitter to an input of a receiver. A receiver local oscillator signal having a receiver local oscillator frequency (fRXLO) is provided to a receiver mixer. A transmitter local oscillator signal having a transmitter local oscillator frequency (fTXLO) to is provided to a transmitter mixer. The receiver local oscillator frequency is separated from the transmitter local oscillator frequency by a nonzero intermediate frequency (fIF). The method includes upconverting a test signal having a baseband frequency (fBB) using the transmitter mixer and downconverting the output signal of the transmitter mixer with the receiver mixer to generate a calibration signal. The transceiver is calibrated based on the calibration signal.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 30, 2018
    Assignee: Intel IP Corporation
    Inventor: Shahar Gross
  • Patent number: 9853649
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: December 26, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 9729329
    Abstract: Examples herein are directed to communicating on a communication bus in accordance with a message-based signal protocol. One or more messages are generated with a data field, in which a portion of the data field is reserved for a signature. The signature has a bit length corresponding to a bit length of the reserved portion of the data field. The signature is coded in the portion of the data field reserved for the signature, and at least one message is transmitted with the signature coded therein. Each message received on the communication bus and having a signature coded in a data field therein is authenticated based on the signature, and processed by removing the signature from the data field and decoding the message with the signature removed.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: August 8, 2017
    Assignee: NXP B.V.
    Inventor: Bernd Elend
  • Patent number: 9549214
    Abstract: A cable network gateway receives a downstream broadband signal via service provider cabling at an interface. An Analog to Digital Converter (ADC) converts the downstream broadband signal to a digital downstream broadband signal. A digital filter attenuates an upper spectrum from the digital downstream broadband signal to produce a filtered digitized downstream broadband signal. An in-home communications transceiver produces a digital in-home communications signal that overlaps the upper spectrum. Summing circuitry sums the filtered digitized downstream broadband signal with the digital in-home communications signal to produce a combined digital signal. A Digital to Analog Converter (DAC) converts the combined digital signal to a combined analog signal and an in-home cable interface transmits the combined analog signal via in-home cabling. The downstream broadband signal may be a Data over Cable System Interface Specification (DOCSIS) 3.0/3.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: January 17, 2017
    Assignee: BROADCOM CORPORATION
    Inventors: Ardie Venes, Donald George McMullin
  • Patent number: 9544123
    Abstract: The present invention provides an electronic device including a coupler, a noise-estimation apparatus and an assembly unit. The coupler receives a baseband signal. The noise-estimation apparatus receives the baseband signal and subtracts a predetermined synchronization preamble from the baseband signal to obtain a noise-estimation signal, and the predetermined synchronization preamble is a transmission signal that conforms to the standards of 802.11bg and/or IEEE 802.11n. The assembly unit receives the baseband signal and subtracts a noise-estimation signal from the baseband signal to obtain an output signal.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: January 10, 2017
    Assignee: WISTRON NEWEB CORP.
    Inventors: Chen-Chao Chang, Yung-Cheng Lin
  • Patent number: 9537590
    Abstract: Apparatus and methods relating to synchronization of communication equipment are disclosed. Synchronization information received from a bonded communication link can be used to synchronize local and/or remote communication equipment, such as femtocell sites coupled to nodes in a ring network. This may involve isolating a frequency reference signal from a DSL (Digital Subscriber Line) communication link which is a constituent link of a bonded communication link, for example. In a ring network, received synchronization information could be used in synchronizing a locally connected installation of communication equipment, and passed for transmission in the ring network for synchronizing other communication equipment. Such dropping and passing of an analog frequency reference signal could be applied in networks having other topologies as well. At least some embodiments of the invention are applicable to optical links.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: January 3, 2017
    Assignee: GENESIS TECHNICAL SYSTEMS CORP.
    Inventors: Stephen P. Cooke, Tino Zottola
  • Patent number: 9501087
    Abstract: A frequency-agile frequency source. The frequency source includes an oscillator having an output and being configured to generate a signal at a first frequency at the output, a first direct digital synthesizer (DDS) having an output and a sampling clock input connected to the output of the oscillator, a filter amplifier block having an input directly connected to the output of the first DDS and an output, and a second DDS having a sampling clock input directly connected to the output of the filter amplifier block. The filter amplifier block is a substantially linear time-invariant element having a frequency response, the magnitude of the frequency response being at least 12 dB lower, at a second frequency within the first Nyquist zone of the first frequency, than at a third frequency above the first Nyquist zone of the first frequency.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: November 22, 2016
    Assignee: RAYTHEON COMPANY
    Inventors: Matthew J. Koeth, Michael R. Patrizi
  • Patent number: 9503103
    Abstract: A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Mao-Hsuan Chou
  • Patent number: 9490827
    Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: November 8, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hua Wang, David Steven Ripley, Bryan J. Roll
  • Patent number: 9438301
    Abstract: In the stop state of a VCO and an injection locked frequency divider, an ILFD controller sets the control parameter of an injection locked frequency divider on the basis of the frequencies of a reference signal and the frequency-divided signal measured according to the control parameter of the injection locked frequency divider. While the injection locked frequency divider is operated and in the stop state of the VCO, the ILFD controller sets the control parameter of the injection locked frequency divider on the basis of the frequencies of the reference signal and the frequency-divided signal measured according to the control parameter of the injection locked frequency divider.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 6, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoichi Nagaso, Kenji Miyanaga, Takahiro Shima
  • Patent number: 9401724
    Abstract: A frequency synthesizer device provides amplitude control. Using switch circuit operating in a first mode, a charge voltage is applied to an oscillator circuit that an inductive-capacitive (LC) tank circuit. The LC tank circuit has a capacitive element, and an inductive element that is connected to the capacitive element. Using the switch circuit operating in a second mode, the LC tank circuit is enabled to oscillate. Using driver circuits that are response to a voltage applied to the tank circuit, current is reinforced in the LC tank, and the reinforcement is based upon a transconductance gain of the driver circuits. Using a calibration circuit, an amplitude of an output signal from the oscillator circuit is detected. In response to the detected amplitude, the transconductance gain is adjusted by enabling or disabling auxiliary circuits from plurality of auxiliary circuits.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: July 26, 2016
    Assignee: NXP B.V.
    Inventors: Yuan Gao, Frank Leong, Robert Bogdan Staszewski
  • Patent number: 9401720
    Abstract: In order to provide a circuit arrangement (100) and also a method for clock and/or data recovery (CDR) having low power consumption, having low power loss and also having scalability of the power loss from the clock and/or data recovery at the data rate, at least one frequency regulation circuit and at least one phase regulation circuit are proposed, wherein firstly only the frequency regulation circuit is active for the purpose of setting the frequency on the basis of the data rate that can be applied to the data input and then changeover to the phase regulation circuit occurs for the purpose of ascertaining the phase difference between the data input and the clock input.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 26, 2016
    Assignee: Silicon Line GmbH
    Inventor: Heinz Werker
  • Patent number: 9356556
    Abstract: A circuit for implementing a dual-mode oscillator is disclosed. The circuit comprises a first oscillator portion having a first inductor coupled in parallel with a first capacitor between a first node and a second node; a first pair of output nodes coupled to the first and second nodes; a second oscillator portion inductively coupled to the first oscillator portion, the second oscillator portion having a second inductor coupled in parallel with a second capacitor between a third node and a fourth node; a second pair of output nodes coupled to the third and fourth nodes; and a control circuit coupled to enable a supply of current to either the first oscillator portion or the second oscillator portion. A method of implementing a dual-mode oscillator is also disclosed.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: May 31, 2016
    Assignee: XILINX, INC.
    Inventors: Mayank Raj, Parag Upadhyaya
  • Patent number: 9344926
    Abstract: The present invention discloses a base station and a handover processing method for digital trunking communication. The handover processing method comprises: a base station transmitting a System Parameter and Neighbor Channel Assignment Message (SNCAM) to a terminal at a normal period; the base station receiving a handover request from the terminal; the base station transmitting the SNCAM to the terminal at a preset period; the preset period is set to be shorter than the normal period and ensures that the power consumption of the base station is lower than a threshold which leads to power overload. The present invention has increased the possibility that the terminal receives the SNCAM, and can also avoid the power overload of the system, thus not only the user experience is improved, but also the life of the base station is prolonged.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: May 17, 2016
    Assignee: ZTE Corporation
    Inventor: Fan Pei
  • Patent number: 9312866
    Abstract: A clock signal generation circuit provides an output clock signal to a digital system. The digital system is powered by a power supply voltage, VDD, that may include transients associated with the impedance of the packaged digital system. The clock signal generation circuit dynamically scales an output clock frequency based on monitored changed to VDD. The output clock frequency may be selected to approximate a maximum (margin-less) system Fmax for the monitored VDD. The average clock frequency may be improved compared with operating at a fixed output clock frequency.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: April 12, 2016
    Assignee: NVIDIA Corporation
    Inventors: Tao Liu, Jawid Aziz, Albert Harjono
  • Patent number: 9294264
    Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: March 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Endo, Keisuke Ueda, Toshiya Uozumi
  • Patent number: 9257996
    Abstract: An oscillator circuit may include a local oscillator to generate a carrier signal having a tunable frequency, a first modulator and a power amplifier coupled in cascade to the local oscillator to generate an output signal. The first modulator may be activated from a first modulating signal having a first frequency alternatively defining ON and OFF states of the first modulator. An estimator unit may receive the carrier signal during a time window and detect an estimated frequency variation of the carrier signal during the ON and OFF states. A compensation unit may include a second modulator to generate a compensation signal proportional to the estimated frequency variation and modulated with a second modulating frequency. The second modulating frequency may be substantially the same as the first modulating frequency, and the compensation signal may be added to a bias signal of the local oscillator to tune the tunable frequency.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: February 9, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Angelo Scuderi, Antonino Calcagno, Salvatore Scaccianoce
  • Patent number: 9191056
    Abstract: An ILFD control unit sets a control parameter of an injection locked frequency divider based on each frequency of a reference signal and a frequency-divided signal measured in response to the control parameter of the injection locked frequency divider, in a stop state of a VCO and an injection locked frequency divider. The ILFD control unit runs the injection locked frequency divider and sets a control parameter of the injection locked frequency divider based on each frequency of the reference signal and the frequency-divided signal measured in response to the control parameter of the injection locked frequency divider, in the stop state of the VCO.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 17, 2015
    Assignee: PANASONIC CORPORATION
    Inventor: Takahiro Shima
  • Patent number: 9179170
    Abstract: A circuit, electrical device or other apparatus for band stacking and/or band translating multiple transmissions. Such transmissions may be satellite transmissions, terrestrial transmissions, signals carried across a wired network such as a cable network, and so forth. Two sets of left-hand polarized and right-hand polarized signals may be accepted by an embodiment. One left-hand polarized signal and one right-hand polarized signal may be band stacked such that the left-hand polarized signal occupies a first frequency and the right-hand polarized signal occupies a second frequency, thereby permitting the two signals to be transmitted simultaneously across a single transmission line as a first unique signal. The second left-hand polarized signal and second right-hand polarized signal may likewise be combined into a second unique signal for transmission. The first and second unique signals may be stacked as a first stacked output and a second stacked output by a band translating circuit.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: November 3, 2015
    Assignee: EchoStar Technologies, L.L.C.
    Inventor: Edmund F. Petruzzelli
  • Patent number: 9148186
    Abstract: A radio receiver supporting cancellation of thermal and phase noise in a down-converted RF signal. An inbound RF signal and blocking signal are provided directly to a passive mixer for down-conversion into a first baseband signal having data, thermal noise, and reciprocal mixing (RM) noise components. The inbound signals are also provided to a transconductance circuit, the output of which is provided to a second passive mixer for conversion into a current signal having data and blocking signal components, and a RM image. The blocking signal component and the RM image are mixed with a second LO signal, derived from the blocking signal, to produce a RM noise cancellation signal. The data component of the current signal is converted into a second baseband signal having data and thermal noise components. The first baseband signal, second baseband signal and RM noise cancellation signal are then combined through harmonic recombination.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: September 29, 2015
    Assignee: Broadcom Corporation
    Inventors: Hao Wu, Mohyee Salahelden Mikhemar, David Patrick Murphy, Hooman Darabi
  • Patent number: 9100028
    Abstract: It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: August 4, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takeshi Osada
  • Patent number: 9099466
    Abstract: Provided are a semiconductor device including an oscillator and a manufacturing method thereof, in which cost is low and design flexibility is high. The semiconductor device includes a wiring structure region and an oscillator region. The semiconductor device also includes, in the oscillator region, a metal resistive element as the same layer as a conducting film over uppermost metal wiring in the wiring structure region.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: August 4, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Toshihiko Miyazaki
  • Patent number: 9042854
    Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: May 26, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hua Wang, David Steven Ripley, Bryan J. Roll
  • Patent number: 9020011
    Abstract: A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 28, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventors: Mark Hiebert, Jay Chen
  • Patent number: 9020018
    Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment and calibration computing equipment for receiving and processing test and calibration signals from wireless communications circuitry to be calibrated. During testing and calibration operations, a device may be provided with initial pre-distortion calibration values. The initial pre-distortion calibration values may be generated at least in part based on calibration operations performed for other wireless electronic devices. The device may generate a test signal using the initial pre-distortion calibration values. The calibration system may determine whether the test signal is within an acceptable range of a known reference signal.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: April 28, 2015
    Assignee: Apple Inc.
    Inventors: Gary Lang Do, David A. Donovan, Gurusubrahmaniyan Radhakrishnan
  • Patent number: 9020086
    Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: April 28, 2015
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Ming Chen, An-Chung Chen
  • Patent number: 9019018
    Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: April 28, 2015
    Assignee: ams AG
    Inventor: Ruggero Leoncavallo
  • Patent number: 9013245
    Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: April 21, 2015
    Assignee: Sand 9, Inc.
    Inventors: Reimund Rebel, Klaus Juergen Schoepf, Jan H. Kuypers
  • Patent number: 8982974
    Abstract: Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.
    Type: Grant
    Filed: February 10, 2013
    Date of Patent: March 17, 2015
    Inventor: John W Bogdan
  • Patent number: 8965310
    Abstract: A transmitter including a first mixer, a first frequency divider to divide a frequency of an input signal to generate a first signal, and a plurality of second frequency dividers to divide the frequency to respectively generate a plurality of second signals, and a control module. In response to the transmitter being turned on, the control module turns on the first frequency divider, turns off the plurality of second frequency dividers, and drives the first mixer with the first signal. Subsequently, in response to determining that a transmit power of the transmitter is to be increased, the control module sequentially turns on and connects each of the plurality of second frequency dividers in parallel to the first frequency divider. Upon a second frequency divider being connected to the first frequency divider, the control module also drives the first mixer using the second signal generated by that second frequency divider.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: February 24, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Danilo Gerna, Stefano Dal Toso, Gregory Uehara
  • Patent number: 8965301
    Abstract: A method includes transmitting, by a first node, a first carrier signal and receiving, from a second node, which receives the first carrier signal, a second carrier signal. The first node measures first and second values of a first phase, the first value assigned to a first frequency of the second carrier signal and the second value assigned to a second frequency of the second carrier signal. The first and second frequencies have a frequency difference. A third value of a second phase is assigned to a third frequency of the first carrier signal, and a fourth value of the second phase is assigned to a fourth frequency of the first carrier signal. The third and fourth frequencies have the frequency difference. A distance between the first and second nodes is determined from the frequency difference from the first and second values and from the third and fourth values.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: February 24, 2015
    Assignee: Atmel Corporation
    Inventors: Wolfram Kluge, Eric Sachse
  • Patent number: 8954017
    Abstract: A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: February 10, 2015
    Assignee: Broadcom Corporation
    Inventors: Love Kothari, Ajat Hukkoo, Kerry Alan Thompson
  • Patent number: 8928423
    Abstract: A narrow band receiver or transceiver for processing electrical signals. The narrow band receiver or transceiver includes an amplifier, a voltage controlled oscillator and a tuning assembly comprising at least one control loop for tuning of the voltage controlled oscillator. At least a gain control of the amplifier is coupled to the control loop for simultaneously tuning the output amplitude of the voltage controlled oscillator and the gain of the amplifier. A compensation of the effect of variation on the gain of the amplifier, which includes an LC tank circuit, is performed by using an information in another LC tank circuit of the voltage controlled oscillator in the control loop.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: January 6, 2015
    Assignee: EM Microelectronic-Marin S.A.
    Inventors: Armin Tajalli, Marc Morin
  • Patent number: 8923790
    Abstract: A wireless communication receiver includes a circuit, an analog-to-digital converter (ADC) and a processing circuit. The circuit receives a wireless signal and outputs an analog signal according to a gain index. The ADC converts the analog signal to a digital signal. The processing circuit adjusts the gain index according to a clipping number of the ADC.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: December 30, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chien-Wei Hsin, Chung-Yao Chang
  • Patent number: 8903345
    Abstract: A method and apparatus for non-linear frequency control tracking of a control loop of a voltage controlled oscillator (VCO) in a wireless mobile device receiver is provided. A channel metric based on one or more channel quality indicators associated with a received radio frequency channel is determined and a state metric associated with the current operating state of the control loop are determined. One or more state metric threshold value associated with the determined channel metric, providing hysteresis between operating states, are determined wherein each state metric threshold value is associated with a transition to a possible operating state of the control loop. The control loop transitions from the current operating state to the operating state associated with an exceeded state metric threshold value. Coefficients are provided to an adaptive loop filter of the control loop, wherein the coefficients are associated with the transitioned operating state.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 2, 2014
    Assignee: BlackBerry Limited
    Inventors: Onur Canpolat, Francis Chukwuemeka Onochie
  • Patent number: 8902796
    Abstract: Embodiments of the present disclosure provide power-efficient time division duplexing (TDD) mode configurations of frequency division duplexing (FDD) transceivers. Embodiments avoid time slotted operation of the receive and transmit synthesizers, thereby avoiding undesired operation under transient conditions, frequent calibration, and reduced power supply efficiency. In embodiments, a single synthesizer is used to enable TDD operation, thereby reducing power consumption and calibration requirements by approximately 50%. The single synthesizer may be maintained ON at all times, thus allowing the power supply's switching regulator to operate with substantially constant load conditions.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: December 2, 2014
    Assignee: Broadcom Corporation
    Inventors: Nikolaos Haralabidis, Konstantinos Vavelidis
  • Patent number: 8903030
    Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei, Tsung-Ching Huang
  • Patent number: 8896158
    Abstract: A variable capacitance circuit includes: a prescribed node, to which an alternate current signal with a reference potential as a center voltage is applied; a first capacitor connected to the prescribed node; a second capacitor connected between the first capacitor and the reference potential; a third capacitor and a transistor for controlling capacitance, provide between a first node between the second capacitor and the first capacitor, and the reference potential; and a bias circuit which applies a first bias voltage to a second node between the third capacitor and the transistor.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroyuki Nakamoto
  • Patent number: 8896384
    Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: November 25, 2014
    Assignee: Broadcom Corporation
    Inventor: Hung-Ming Chien
  • Patent number: 8890635
    Abstract: A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: November 18, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Alexander Belitzer, Andre Hanke, Boris Kapfelsperger, Volker Thomas, Elmar Wagner