Abstract: Calibration of a phase locked loop and applications thereof within a radio frequency integrated circuit begins by determining an intersection of an up current and down current produced by a charge pump within the phase locked loop. The RFIC then determines a reference voltage corresponding to the intersection, which varies from an ideal voltage of VDD/2 based on process variations. The RFIC then offsets a control voltage to the voltage control oscillator (VCO) of the phase locked loop based on the reference voltage. Accordingly, by determining the offset of the actual intersection from the ideal intersection, the control voltage to the VCO may be adjusted thereby calibrating the phase locked loop for more linear performance.

Abstract: A linear fractional-N synthesizer includes phase and frequency detection module, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a fractional-N divider. The phase and frequency detection module is operably coupled to produce a charge up signal, a charge down signal, or an off signal based on a phase difference and/or a frequency difference between a reference oscillation and a feedback oscillation. The charge pump circuit is operably coupled to produce a positive current when the charge up signal is received, a negative current when the charge down signal is received, and a non-zero offset current when the off signal is received. The charge pump includes a resistor and a control module. The resistor provides the non-zero offset current and the control module maintains the non-zero offset current at a substantially constant value.

Abstract: Techniques are described that facilitate the generation of different waveforms at different frequencies required for transmission and reception of wireless voice signals and wireless data signals. For example, a technique may include generating a first waveform in a wireless communication device using a frequency synthesizer, wherein the first waveform has a frequency associated with a voice communication standard, and generating a second waveform in the wireless communication device using the same frequency synthesizer, wherein the second waveform has a frequency associated with a wireless networking standard. In this manner, a wireless communication device can be improved and possibly simplified.

Abstract: A transceiver for a code division multiple access communication system comprises a receiver to receive coded information signals and a transmitter to transmit coded information signals. A local oscillator provides a time and frequency reference for the receiver and the transmitter. A timing controller provides timing signals for the receiver and the transmitter. A signal processor decodes received signals to determine a common error associated with the timing controller. A timing correction circuit smoothly adjusts the timing of the coded information signals transmitted by the transmitter responsive to the timing error to reduce the timing error over a desired time interval.

Abstract: A receiver circuit that includes a direct conversion receiver that receives a modulated signal, and generates an in-phase differential signal and a quadrature-phase differential signal. The receiver circuit includes an in-phase branch that processes the in-phase differential signal, and a quadrature-phase branch that processes the quadrature-phase differential signal. Each branch includes an amplifier and a summer. The amplifier is configured to receive and amplify the respective in-phase or quadrature-phase differential signal. The summer receives the resulting amplified differential signal and sums the signals to generate a single signal. A log amplifier receives the summed in-phase and quadrature-phase signal, and generates an RSSI signal that is proportional to the log of the difference between the two summed signals. The data may then be extracted based on the amplitude of the RSSI signal.

Abstract: A tunable element in the microwave frequency range is described that may include one or more tunable elements that are directly digitally controlled by a digital bus connecting a digital control circuit to each controlled element. In particular, each digital signal is filtered by a digital isolation technique so that the signal reaches the tunable elements with very low noise. The low noise digital signals are then converted to analog control voltages. The direct D/A conversion is accomplished by a special D/A converter which is manufactured as an integral part of a substrate. This D/A converter in accordance with the invention may consist of a resistor ladder or a directly digitally controlled capacitor. The direct digitally controlled capacitor may be a cantilevered type capacitor having multiple separate electrodes or sub-plates representing binary bits that may be used to control the capacitor.

Abstract: Methods to generate a mobile time reference are provided. A representative method includes providing a high frequency clock, providing a low frequency clock, generating a mobile time reference using the high frequency clock, maintaining the mobile time reference using the low frequency clock when the high frequency clock is turned off, and continuing to generate the mobile time reference using the high frequency clock when the high frequency clock has been turned back on. Systems and other methods are also provided.

Abstract: A smart radio incorporating Parascan® varactors embodied within an intelligent adaptive RF front end. More specifically, this is provided for by a smart radio incorporating Parascan® varactors embodied within an intelligent adaptive RF front end that comprises at least one tunable antenna; at least one antenna null steering facility associated with said at least on tunable antenna; at least one tunable duplexer receiving the output from and providing input to said at least one antenna null steering facility; a first tunable RF filter receiving the output from said at least one tunable duplexer and providing the input to an analog to digital converter, said analog to digital converter providing the input to a digital signal processor, the output of which is input for a digital to analog converter; a second tunable RF filter receiving the analog output of said digital to analog converter and providing an input to said at least one tunable duplexer.

Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.

Abstract: A carrier recovery method and apparatus using multiple stages of carrier frequency recovery are disclosed. A receiver uses multiple frequency generation sources to generate carrier signals used to downconvert a received signal. An analog frequency reference having a wide frequency range and coarse frequency resolution is used in conjunction with a digital frequency reference having a narrow frequency range and fine frequency resolution. The multiple carrier signals are multiplied by a received signal to effect a multi-stage downconversion, resulting in a baseband signal. A frequency tracking module measures the residual frequency error present in the baseband signal. The measured residual frequency error is then used to adjust the frequencies of the carrier signals generated by the multiple frequency generation sources.

Abstract: Systems and methods to recover spread spectrum radio signals are provided. A representative system includes an antenna, a radio frequency subsystem, a baseband subsystem, and at least one peripheral device. The radio frequency subsystem is coupled to the antenna and includes a high frequency oscillator and a low frequency oscillator. The baseband subsystem is coupled to the radio frequency subsystem and includes a free running counter coupled to the high frequency oscillator and the low frequency oscillator and a multipath signal recovery circuit coupled to the free running counter. The multipath signal recovery circuit includes a plurality of signal path processors to recover clock information from a plurality of incoming signals.The peripheral device is coupled to the baseband subsystem to receive and supply signals to the baseband receiver.

Abstract: A phase locked loop that includes such a loop filter, the phase locked loop includes a difference detector, programmable charge pump, fixed loop filter, voltage controlled oscillator and adjustable divider module. The difference detector is operably coupled to determine a different signal based on differences in phase and/or frequency between a reference oscillation and a feedback oscillation. The programmable charge pump is operably coupled to generate a charge current based on the difference signal and a scaling signal. The fixed loop filter is operably coupled to convert the charge current into a control voltage. The voltage controlled oscillator generates an output oscillation based on the control voltage and the adjustable divider module generates the feedback oscillation based on the output oscillation and a divider value. The scaling module is operably coupled to produce the scaling signal based on the selected divider.

Abstract: An FM radio receiver includes a low noise amplifier, down conversion mixing module, local oscillation module, bandpass filter, demodulation module, and a DC offset estimation module. The low noise amplifier, the down conversion mixing module, the bandpass filter, and the demodulation module are operably coupled to recapture data from a received a radio frequency (RF) signal. The local oscillation module is operably coupled to generate the local oscillation based on a reference oscillation and a DC offset correction signal. The DC offset estimation module is operably coupled to generate the DC offset correction signal based on a determined a DC offset. The DC offset estimation module determines the DC offset prior to compensation of the local oscillation, such as during a test sequence and/or during a preamble.

Abstract: For use in an orthogonal frequency division multiplexing (OFDM) transceiver, a multimode local oscillator circuit and a method of operating the same. In one embodiment, the circuit includes: (1) a single sideband mixer having an output, first and second inputs and a local oscillator input and (2) a signal generator, coupled to the single sideband mixer, for alternatively providing to the first and second inputs: (2a) constant values to cause the single sideband mixer to generate a first receiver local oscillator signal for operating the OFDM transceiver as a zero intermediate frequency receiver and (2b) a first orthogonal baseband signal to cause the single sideband mixer to generate a second receiver local oscillator signal for operating the OFDM transceiver as a low intermediate frequency receiver.

Abstract: In a cellular telephone provided with a receiving circuit of a direct conversion type, a passive low-pass filter is arranged between a mixer for an I-channel and a base band circuit for removing interference waves of or above a channel next to a channel neighboring to the I-channel, and another passive low-pass filter is arranged between a mixer for a Q-channel and the base band circuit for removing interference waves of or above a channel next to a channel neighboring to the Q-channel. Since the low-pass filters for removing the interference waves of or above the channel next to the neighboring channel are of a differential type, the circuit scale can be small, and the power consumption is small. Since the interference waves are removed by the passive low-pass filters and the active low-pass filters, only the desired channel can be reliably received.

Abstract: A radio communication unit employs passive devices and a loop filter to receive a coded frequency modulated wakeup or synchronization signal that enables the receiving radio unit and initiates communications. The loop filter simultaneously tracks phase and frequency and provides smoothing to enable synchronization with weak signals (e.g., signals that typically do not enable a standard phase locked loop (PLL) to lock). In particular, when the communication unit is in a standby mode, the passive circuits of the present invention are receiving energy from a unit antenna and initially function as a phase locked loop (PLL) to lock onto an incoming signal. The wakeup or synchronization signal includes a series of tones at different frequencies, where the specific sequence is prearranged between the transmitting and receiving units. When each tone in the sequence has been detected by the receiving unit, the unit is enabled for communications.

Abstract: A portable radio terminal for realizing automatic frequency control (AFC) for automatically controlling the oscillation frequency of an oscillator includes a unit for intermittently performing AFC operation, and a unit for shortening an AFC operation stop period when the frequency shift of the oscillation frequency is large. An AFC control method is also disclosed.

Abstract: A radio communication apparatus includes a low-rate clock oscillator for generating a low-rate clock signal used for reception timing estimation; a frequency deviation measuring duration controller for determining a deviation measuring duration of measuring a frequency deviation of the low-rate clock signal in accordance with an intermittent time interval of the radio signal; a frequency deviation measuring section for measuring the frequency deviation of the low-rate clock signal over the deviation measuring duration; and a timing counter for correcting the frequency deviation of the low-rate clock signal, for measuring an intermittent span of the received signal in response to the low-rate clock signal after the correction, and for generating the estimated reception timing of the radio signal.

Abstract: An integrated circuit including a substrate, a conductive layer, at least one inductive element superposed on the conductive layer and formed by a metallic turn having an outer contour and an inner contour, which bound between them a surface referred to as the radiation surface, and insulating material for insulating the conductive layer from the inductive element. The conductive layer has a surface substantially identical to the radiation surface.

Abstract: A data-pattern feedback mechanism is introduced into the peak detection process of an automatic frequency compensation system in a Gaussian Frequency Shift Keying (GFSK) modulated system, providing fast and accurate fine-stage automatic frequency compensation (AFC). Maximum positive and negative peak registers are updated with new values as necessary based on detection during a sequence of identical binary bit values (e.g., during a “00” for detection of maximum negative peak frequency, or during a “11” for detection of maximum positive peak frequency), in a particular data frame. As soon as an initial value is determined for both the maximum positive and negative peak frequencies (e.g., after the first occurrence of a “11” and a “00”, in any order), fine-stage automatic frequency compensation can be initiated. Subsequent adjustments to the VCO of the local oscillator will further refine the frequency offset towards the ideal of zero.

Abstract: The frequency error of an oscillator is minimized by characterizing the oscillator. A reference signal from an external source containing a minimal frequency error is provided to an electronic device. The external signal is used as a reference frequency to estimate the frequency error of an internal frequency source. The electronic device monitors parameters that are determined to have an effect on the frequency accuracy of the internal frequency source. Temperature is one parameter known to have an effect on the frequency of the internal frequency source. The electronic device collects and stores the values of the parameters as well as the corresponding output frequency or frequency error of the internal frequency source. The resultant characterization of the internal frequency source is used to compensate the internal frequency source when the internal frequency source is not provided the external reference signal.

Abstract: A sinusoidal RF carrier is modulated for the transmission of digital binary data streams through the amplitude suppression of carrier wavelets. These wavelets are defined between zero crossover positions representing zero energy locations. This modulation is accomplished when the carrier is slightly amplitude modulated with a modulation signal that is equal in frequency to the carrier itself and the modulation always begins or ends upon the exact zero voltage crossing point of the RF cycle phase. The modulation is applied as a slight shift of the amplitude of any single cycle, each cycle representing a single bit of data. A single cycle of RF will either represent a “1” or “0” depending upon the amplitude of the cycle, relative to other adjacent cycles in the same carrier.

Abstract: A method for producing an output signal (42) with a specific frequency from an input signal (40) received, the frequency of which changes quickly in steps of the size of an input frequency resolution or a multiple of the input frequency resolution, on the input frequency band. Furthermore, a method is presented for producing an output signal (72) from an input signal (70) with a specific frequency, and for changing the frequency of the output signal (72) quickly in steps of the size of an output frequency resolution or a multiple of the output frequency resolution, on the output frequency band. Methods, as well as a receiver and a transmitter that implement the methods are based on the setting of an intermediate frequency from an intermediate frequency band, which comprises at least two different values. The difference between the values, i.e. the intermediate frequency resolution, is higher than the input or output frequency resolutions.

Abstract: To minimize the overall circuitry necessary in a multiband-frequency generator, output terminals of a voltage-controlled multiband oscillator (22-1, . . . , 22-N) are coupled to a frequency synthesis unit (10) via a frequency selective coupling unit (24). The frequency synthesis unit (10) derives a phase difference between a frequency control input signal and the output signal of the frequency selective coupling unit (24) to control the voltage-controlled multiband oscillator (22-1, . . . , 22-N).

Abstract: Fast switching and fast settling is achieved in a phase locked loop (“PLL”) containing a bandwidth switched active loop filter (8) by feeding the phase error signal of the phase detector (1) of the PLL to the non-inverting input of the amplifier (7) within the loop filter and having the electronic switch (17) control the loop filter bandwidth through changing the resistance (9, 11) to ground at the inverting input of the amplifier between a high and low value associated respectively with broad bandwidth and narrow bandwidth to the loop filter. Switching is possible in as little as one microsecond, and is accompanied by fast settling of the loop with minimal generation of phase/frequency perturbation. The foregoing PLL is of particular benefit in fast switching frequency synthesizers, such as used in frequency hopping frequency synthesizers of frequency and time division multiplexing systems.

Abstract: A three port structure for the down conversion demodulation of a digitally modulated RF signal is proposed, wherein no RF switches are provided. The three port structure (1) has a first input (2) for the RF signal to be down converted and a second input (3) for a RF signal originating from a local oscillator (8). An output (4) of the three port structure (1) is supplied to a power sensor unit (5). The RF signal from the local oscillator (8) is modulated (7) before it is supplied to the three port structure (1).

Abstract: There is provided a voltage controlled oscillation (VCO) circuit which can adjust the oscillation frequency without trimming and a semiconductor integrated circuit for communication comprising the same VCO circuit, wherein as the VCO circuit forming the PLL circuit, an LC resonance type oscillation circuit is used in which a plurality of capacitance elements are connected in parallel via a selection means such as a switch and the oscillation frequency is varied by changing the circuit constant (LC) depending on the selecting condition of the selecting means, moreover a comparing circuit for comparing the control voltage supplied to the VCO circuit from the loop filter of PLL circuit with the reference voltage and a frequency adjustment circuit for generating the signal to control the selecting means based on the comparison result of the comparing circuit are also provided to determine the signal to control the selecting means through the sequential comparison.

Abstract: To address the problem of aging and drift of a local oscillator in a mobile telephone the frequency Fi of the local oscillator is shifted upwards so that base station logging-on FCH signals are measured perfectly whether said drift is upwards or downwards. It is shown that the actual drift resulting from the initial shift and drift with time can be measured during logging on. It is shown that conforming to the standard is facilitated without having to provide an oscillator whose frequency stability with time is guaranteed.

Abstract: A phase lock loop receives a baseband signal which has an input frequency, and modulating the baseband signal to be a corresponding RF signal which has a predetermined transmission frequency for transmitting. The phase lock loop comprises a programmable divider, a modulator, a phase detector, a charging pump, a loop filter, a voltage-controlled oscillator and a frequency converter. The programmable divider divides the frequency of a local oscillating signal by a programmable divisor to generate a reference signal. The modulator receives the baseband signal, modulates the frequency of the reference signal according to the baseband signal, and generates a corresponding first comparison signal. The frequency converter receives the feedback RF signal and the local oscillating signal and outputs the second comparison signal according to the frequency difference. The divisor of the divider is programmable to avoid the spur frequency being generated because the local oscillating signal is interfered.

Abstract: Frequency modification circuitry may be employed as part of a crystal oscillator circuit to generate a reference signal with adjustable frequency. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may adjust the frequency of the reference signal in response to one or more frequency control signals. In one example, the frequency modification circuitry may include variable capacitors such as one or more continuously variable and/or discretely variable capacitors for providing coarse and/or fine adjustment of the reference signal frequency.

Abstract: The invention provides for a mobile radio communications device having a first crystal oscillator for providing a first master clock frequency for a timebase of a first communication system, a second crystal oscillator for providing a second master clock frequency for a timebase for a second communication system, a third oscillator for providing a relatively low frequency clock signal within the device, and means for calibrating each of the first and second master clock signals to the third oscillator clock signal, means for determining the ratio of the first and second master clocks on the basis of respective measurements of the first and second master clocks to the relatively low frequency clock signal.

Abstract: A tunable filter circuit includes a first differential pair biased by a first current, a second differential pair biased by a second current, a first capacitor and a second capacitor. The tunable filter circuit of the present invention can be configured as a bandpass filter or a bandstop filter by connecting the input voltage signal to different input nodes of the tunable filter circuit. The tunable filter circuit can be tuned by adjusting the values of the first current and the second current. In an alternate embodiment, frequency tuning is achieved either by switching capacitive loads or changing resistive impedances introduced at the emitter of the differential pairs, which also extends the input voltage range of the filter. This emitter resistance is implemented using MOS switches whose on-resistance can be controlled for a precise tuning within a large frequency range.

Abstract: A single chip superhetrodyne AM receiver is disclosed herein. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver. To further improve the signal to noise ratio of the receiver, the IF filter is tuned within a range so as not to include any integer multiple or integer divisor of the timing reference frequency. Various techniques are described for enabling a complete superhetrodyne AM receiver to be implemented on a single chip which receives an antenna input signal and outputs a digital data signal.

Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit for the transmission PLL circuit is configured to be operable in a plurality of bands. The communication semiconductor integrated circuit also comprises a circuit for measuring the oscillating frequency of the oscillator circuit for the transmission PLL circuit, and a storage circuit for storing the result of measurement made by the measuring circuit. A band to be used by the oscillator circuit for the transmission PLL circuit is determined based on values for setting the oscillating frequencies of the oscillator circuit forming part of the reception PLL circuit and the intermediate frequency oscillator circuit, and the result of measurement stored in the storage circuit.

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract: A radio communication unit employs passive devices and a loop filter to receive a coded frequency modulated wakeup or synchronization signal that enables the receiving radio unit and initiates communications The loop filter simultaneously tracks phase and frequency and provides smoothing to enable synchronization with weak signals (e.g., signals that typically do not enable a standard phase locked loop (PLL) to lock). In particular, when the communication unit is in a standby mode, the passive circuits of the present invention are receiving energy from a unit antenna and initially function as a phase locked loop (PLL) to lock onto an incoming signal. The wakeup or synchronization signal includes a series of tones at different frequencies, where the specific sequence is prearranged between the transmitting and receiving units. When each tone in the sequence has been detected by the receiving unit, the unit is enabled for communications.

Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

Abstract: A data-pattern feedback mechanism is introduced into the peak detection process of an automatic frequency compensation system in a Gaussian Frequency Shift Keying (GFSK) modulated system, providing fast and accurate fine-stage automatic frequency compensation (AFC). Maximum positive and negative peak registers are updated with new values as necessary based on detection during a sequence of identical binary bit values (e.g., during a “00” for detection of maximum negative peak frequency, or during a “11” for detection of maximum positive peak frequency), in a particular data frame. As soon as an initial value is determined for both the maximum positive and negative peak frequencies (e.g., after the first occurrence of a “11” and a “00”, in any order), fine-stage automatic frequency compensation can be initiated. Subsequent adjustments to the VCO of the local oscillator will further refine the frequency offset towards the ideal of zero.

Abstract: A frequency-timing control loop comprising (1) a frequency control loop to acquire and track the frequency of a given signal instance in a received signal and (2) a timing control loop to acquire and track the timing of the same signal instance. The timing control loop processes data samples for the received signal to provide a first control indicative of timing error in the data samples for the signal instance. The frequency control loop includes (1) a frequency discriminator used to derive a second control indicative of frequency error in the data samples for the signal instance, and (2) a loop filter used to filter the first and second controls to provide a third control. This third control is used to adjust the frequency and phase of a periodic signal, which is used (directly or indirectly) to downconvert and digitize the received signal to provide the data samples.

Abstract: Some improvements to the conventional algorithms for data aided frequency synchronisation in cellular systems are introduced in a new method executable by the user equipments of various standards, i.e. 3GPP CDMA-TDMA, FDD mode at 3.84 Mcps, TDD mode at 3.84 Mcps, TDD mode at 1.28 Mcps; CWTS TD-SCDMA; GSM/DCS/GPRS. The method begins to obtain the suboptimal frequency errors &Dgr;{tilde over (f)}i using a well known formula which calculates the argument of the autocorrelation over a subset of the baseband samples of the detected training sequence. The errors &Dgr;{tilde over (f)}i are stored into a shift register L-position long and averaged to obtain an estimated frequency error &Dgr;{circumflex over (f)}i used for recursively correcting the reference frequency of the local oscillator, as: {circumflex over (f)}i={circumflex over (f)}i−1+K&Dgr;{circumflex over (f)}i where K (0≦K≦1) is a weighting factor.

Abstract: A receiver for use in a wireless audio transmission system includes a first voltage-controlled oscillator (“1st VCO”) for generating a first local oscillator (“1st LO”) signal, a down converter responsive to the first LO signal for converting a received high-frequency signal into a 1st IF signal having a frequency determined in part by the 1st LO signal, a reference signal source for generating a first reference signal, a second voltage-controlled oscillator (“2nd VCO”) responsive to the first reference signal for generating a second reference signal having a desired frequency for the 1st LO signal, a first phase-locked loop (“1st PLL”) responsive to the first and second reference signals for controlling the 2nd VCO to synchronize the phase of the first and second reference signals, and a second phase-locked loop (“2nd PLL”) responsive to the 1st LO signal and the second reference signal for controlling the 2nd VCO to synchronize the phase of the 1st

Abstract: An Automatic Frequency Control (AFC) circuit for a mobile terminal employs a fractional-N Phase Locked Loop (PLL) to directly reduce errors in the synthesized frequency, such as due to component tolerances, temperature drift, and the like. The frequency error is detected by the average speed of rotation of the I,Q constellation. A corresponding offset is added to the tuning frequency selection word prior to encoding, such as in a &Dgr;&Sgr; modulator, to generate an effective non-integer PLL frequency division factor over a specified duration. The &Dgr;&Sgr; modulator may include dithering the different integer values by a pseudo-random number to minimize noise in the output frequency spectrum introduced by the fractional-N division. Component and parameter selection allow a high degree of resolution in frequency control of the fractional-N PLL. By directly controlling for the frequency error, a DAC and XTAL oscillator tuning circuit may be eliminated from the AFC circuit.

Abstract: This device utilizes frames transported on carriers of different frequencies (BCCH ext CBCH(SD/8)). For processing the information coming from these frames, the device comprises a transceiver circuit (10) including a phase-locked loop for a local oscillator (12). The information is distributed over these frames in locations so that the loop has time to phase lock the local oscillator (12) for receiving information contained in another frame of a different carrier.

Abstract: In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.

Abstract: A low noise multi-loop radio frequency synthesizer is disclosed for the read channel in a hard disk drive, and for RF wireless communications local oscillator applications. The frequency synthesizer receives an input reference signal having a frequency fR, into a fine tune phase locked loop and into a coarse tune phase locked loop. Driven by the input reference signal, the fine tune PLL outputs a fine tune signal with a frequency fR·P, where P is an integer, while the coarse tune PLL, also driven by the same input reference signal, outputs a coarse tune signal with a frequency fR·A, where A is an integer. A translation phase locked loop has a unity multiplication factor and is driven by the fine tune signal output.

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock.

Abstract: A method and system for receiving a signal in a received frequency and shifting the received frequency to become a desired frequency is provided. The system includes a controllable oscillator for generating a first internal frequency, a frequency estimating unit connected to the controllable oscillator, a first frequency shift unit, connected to the controllable oscillator and to the frequency estimating unit, for shifting the received frequency according to the first internal frequency, thereby obtaining an initially shifted frequency and a second frequency shift unit connected to the first frequency shift unit and the frequency estimating unit for shifting the initially shifted frequency. The frequency estimating unit determines a total frequency shift value from the desired frequency, the received frequency and the first internal frequency and it also determines a first frequency shift value and a second frequency shift value from the total frequency shift value.

Abstract: A method and apparatus for providing frequency acquisition and locking detection for a phase lock loop is disclosed. The phase lock loop locks a receiver local oscillator to the frequency and phase of an RF carrier to allow data to be recovered from the RF carrier in the receiver. An analog mixer in the phase lock loop compares the frequency and phase of a receive LO output by a voltage controlled oscillator in the phase lock loop and the received RF carrier. A locking indicator dependent on the result of the comparison indicates whether the phase lock loop is locked. The locking indicator is coupled to a comparator. The comparator generates a pulse to close a switch in order to inject a periodic sweeping signal generated by a free running multi vibrator into the phase lock loop to push the receiver LO into the locking range.

Abstract: Methods and circuitry reduce adverse impacts of intermodulation and optimize performance of integrated circuits that include two or more oscillator circuits on the same chip. In one embodiment, intermodulation between voltage-controlled oscillators (VCOs)in the receiver and transmitter paths of a transceiver is reduced by adjusting relative power of the VCOs and/or bandwidths of the phase-locked loops (PLLs). The invention measures the injection lock frequency range of the VCOs based on which transmitter and receiver VCO power and loop bandwidths are adjusted.

Abstract: A transceiver includes a Downstream Signal Processor (DSP), an Upstream Signal Processor (USP), a Local Oscillator (LO), a differencer, a reference signal generator, and an estimator. The DSP receives an initial downstream signal, a downstream LO signal from the LO, and from the estimator a frequency-offset estimate indicative of a free-running frequency offset included in the initial downstream signal. The DSP uses the LO signal and the estimate to frequency down-convert the initial downstream signal, and also to remove the frequency offset from the initial downstream signal, thereby producing a corrected downstream signal. The USP uses both an upstream LO signal from the LO and the estimate to frequency convert an initial upstream signal so as to produce a frequency pre-corrected upstream signal.