Abstract: A digital demodulator includes a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a digital signal modulated by phase shift keying, a capacitor to store the charge of the resonator, an amplifier including an input node and an output node between which the capacitor is connected to convert a stored charge of the capacitor into a voltage signal, and a controller configured to accumulate in the resonator the charge induced by the frequency signal modulated by phase shift keying in a first control mode and configured to transfer the charge of the resonator to the capacitor in a second control mode, to output the voltage signal corresponding to the stored charge of the capacitor from the output node of the amplifier.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The input signal is fed to a synthesizer timed to a rational multiplier of the RF frequency L/N fRF. The clock signal generated is divided by a factor Q to form 2Q phases of the clock at a frequency of L(N*Q)fRF, wherein each phase undergoes division by L. The phase signals are input to a pulse generator which outputs a plurality of pulses. The pulses are input to a selector which selects which signal to output at any point in time. By controlling the selector, the output clock is generated as a TDM based signal. Any spurs are removed by an optional filter.

Abstract: The present invention is a method and apparatus that produces an estimate of the local oscillator (LO) frequency error using an external reference signal. The error estimate can be used for LO calibration, correction and other purposes. The present invention does not require the external reference signal to be a precision reference signal, nor does the present invention require that the reference signal be continuously supplied. Further, the present invention can be implemented exclusively in software, and therefore does not add to the size or weight of any device that it is resident in. Thus, the present invention can be added to microcontrollers and various specialized programmable digital ICs that were not initially designed for this task.

Abstract: A dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed. A low pass filter allows all channels below a selected frequency enter the circuit. A precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal. An automatic carrier detection circuit monitors the IF signal and determines whether the signal is of analog or digital format and intermediate frequency filters are adjusted based upon the type of signal detected. A coherent oscillator circuit generates in-phase and quadrature reference signals that are used by video and audio detectors for further processing of the IF signal. In-phase and quadrature outputs are provided for digital signals and composite video and audio outputs are provided for analog signals.

Abstract: An integrated circuit includes clock deskew circuitry. The deskew circuitry includes a loop circuit to align an input clock signal with an output clock signal, and also aligns transmitted data with the output clock signal.

Abstract: A circuit is formed to steer current in and out of an inductive load in a manner that enables an amplifier to provide a plurality of gain steps without modifying an LC time constant for the circuit and, therefore, without modifying the tuning or frequency of oscillation for the circuit. A first group of MOSFETs are coupled in parallel and define the circuit current flow. A second group of MOSFETs are coupled in parallel to each other and in series to an impedance device. A third group of MOSFETs coupled to steer current in and out of the impedance device to affect the output signal coupled to one end of the impedance device. The transistors in the second and third groups of MOSFETs are selectively activated to control the amount of current that goes through the impedance device.

Abstract: A method for recovering data includes generating a plurality of out-of-phase clock signals. The method also includes generating samples of an incoming data signal, where a plurality of samples are generated using each of the plurality of clock signals. The method further includes selecting one of the plurality of clock signals and providing the samples generated using the selected clock signal. The incoming data signal may be received over a serial interface that includes a clock line for transporting a main clock signal. The out-of-phase clock signals could be approximately 0°, 90°, 180°, and 270° out-of-phase with respect to the main clock signal. The out-of-phase clock signals could be used to clock different registers that sample the incoming data signal. The selected clock signal could be selected by identifying a transition that occurs between samples associated with two of the clock signals and then selecting another of the clock signals.

Abstract: A fast switching, dual frequency phase locked loop comprising dual phase/frequency detectors, dual charge pumps, a pair of loop filters, and a low leakage voltage controlled oscillator. Each phase/frequency detector and associated tuning ports of the voltage controlled oscillator can be activated and deactivated separately without disturbing the charge on the loop filters.

Abstract: A downconverter and upconverter are provided which can obtain a sufficient image rejection ratio in a low-Intermediate Frequency (IF) scheme while reducing power consumption and can suppress Error Vector Magnitude (EVM)-related degradation in a zero-IF scheme. A complex-coefficient transversal filter rejects one side of a positive or negative frequency, and converts a Radio Frequency (RF) signal to a complex RF signal configured by real and imaginary parts. A local oscillator outputs a real local signal with a set frequency. A half-complex mixer, connected to the complex-coefficient transversal filter and the local oscillator, performs a frequency conversion process by multiplying the complex RF signal output from the complex-coefficient transversal filter and the real local signal output from the local oscillator, and outputs a complex signal of a frequency separated by the set frequency from a frequency of the RF signal.

Abstract: A medium access control (MAC) entity first computes an achievable rate region based on a total transmit power limit and a channel gain of each of a plurality of WTRUs. Next, the MAC entity selects an order of DPC among the WTRUs. A rate set for use in transmitting to the WTRUs is then selected, said rate set being within the computed achievable rate region. Then, based on the selected DPC order and rate set, a DPC entity performs DPC on a plurality of data streams intended for the plurality of WTRUs. If nested lattice-based DPC is utilized, rate compatibility is achieved by selecting proper nesting ratios corresponding to a desired data rate set. Otherwise, if binary-code based DPC is utilized, rate compatibility is achieved via selecting appropriate message input sizes for input to point-to-point coding units prior to performing DPC.

Abstract: Determination and processing for fractional-N programming values. The present invention is operable to receive a clock signal (CLK) and to transform that CLK into a new CLK, when necessary, for use by various circuitries within a system. The present invention is operable to generate two different CLKs for use by a radio frequency (RF) circuitry and a baseband processing circuitry in certain embodiments. The present invention employs a measurement circuitry and to characterize a first CLK and uses a fractional-N synthesizer to perform any necessary processing to generate the one or more CLKs to the other CLKs within the system. The first CLK may be received from an external source or it may be generated internally; in either case, the present invention is able to modify the CLK into another CLK for use by other circuitries within the system or for use by another external device.

Abstract: Systems and methods are provided that compensate for frequency drift due to temperature variation without the need for a temperature sensor. In one embodiment, a navigation receiver with an integrated communication device receives a base station reference signal, which is used to periodically calibrate a local oscillator frequency. In another embodiment, the calibrated local oscillator frequency drives a counter that is used to provide code phase estimation at the start of satellite signal acquisition. To provide temperature compensation in one embodiment, the calibrated local frequency is used to drive one or more counters at different calibration rates (i.e., different time intervals between calibrations). Count values from these counters are used to determine compensation for frequency drift due to temperature variation based on predicted frequency drift variation patterns between calibrations.

Abstract: A method for reducing adjacent channel interference begins by determining a desired channel of a radio frequency (RF) signal. The method continues by determining a plurality of potential local oscillations for the desired channel. The method continues by determining a proximal power level of an image frequency of each of the plurality of potential local oscillations to produce a plurality of proximal power levels. The method continues by selecting one of the plurality of potential local oscillations for down converting the desired channel based on the plurality of proximal power levels.

Abstract: Various embodiments of the present invention relate to circuits for and methods of generating a bias current for a plurality of data transceivers on an integrated circuit. According to one embodiment, an integrated circuit having a plurality of data transceivers comprises a first data transceiver receiving a reference voltage. A plurality of data transceivers are preferably coupled to the first data transceiver, where each the data transceiver of the plurality of data transceivers receives a reference current based upon the reference voltage from the first data transceiver. According to alternate embodiment of the invention, an external resistor is coupled to a data transceiver to generate a fixed bias current in addition to a variable bias current. A method of generating a bias current for a plurality of data transceivers is also disclosed.

Abstract: A method for controlling local oscillator (LO) feed-through in a direct transmitter includes detecting a signal level corresponding to LO feed-through in a radio frequency (RF) signal that is output by a direct transmitter. Responsive to detecting the signal level corresponding to LO feed-through, DC offset levels are modified for an in-phase (I) signal and/or a quadrature-phase (Q) signal in the direct transmitter.

Abstract: A phase locked loop (PLL) circuit (1) comprising a loop input (11); a phase detector section (2) for detecting a phase difference between an input signal and a reference signal. The phase detector section (2) has a detector input connected to the loop input, a reference input and a detector output for outputting a signal related to the phase difference. A controlled oscillator (4) is connected with an input to the detector output and an oscillator output is connected to a loop output (12). The PLL has a feedback circuit which connects the oscillator output to the reference input, wherein the feedback circuit includes a device (7;71-74) having a transfer function with at least one zero.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: An antenna-receiver communications system and method is provided to mechanize multibeam mobile antenna-receive subsystems. Digital beam forming for modern wideband mobile communications systems is provided. In an aspect, subsystems can simultaneously receive, acquire, track and output a multiplicity of signals from sources of different locations using a single antenna aperture from a mobile platform. The angle of arrival of a signal of interest is continuously determined. Individual phased array antenna output channels are phased aligned as required by the phased array equation and monopulse signal processing. Angle sensing and beamsteering are separated from antenna channel coherent summation. Thus, the angle sensing and beamsteering functions are not required to be computed at the data rate, but can instead be computed at a rate necessary for the beam acquisition and beam tracking function speed requirements. Signal processing computational load and system cost is reduced as compared to current systems.

Abstract: A highly integrated GPS RF Front End which uses a single conversion stage employs an image rejection mixer stage to eliminate the need for an image reject RF bandpass filter. Also a relatively high sample rate A/D is employed which allows a timeless monolitic IF Filter to be used. The disclosure also discusses a GPS Front End topology that is easily integrated from industry standard building blocks. With the broad variation in potential receiver designs, the present invention includes some specific receiver topologies that lend themselves to a high level of integration. The specific designs presented here are comprised of industry standard building blocks and functions that have been described elsewhere in the related art.

Abstract: A receiver IC provided with a SAW-based oscillator with an external SAW device. The receiver IC comprises an oscillating circuit. The oscillating circuit comprises an inverter stage, a first capacitor, a second capacitor, and a resistor. The inverter stage has input and output terminals respectively coupled to two ends of the external SAW device. The first and second capacitors are respectively coupled between the input/output terminal and a ground. The resistor is coupled between the input and output terminals of the inverter stage.

Abstract: A power amplifier develops a modulated high power signal by summing the outputs of multiple voltage controlled oscillators. A phase control circuit synchronizes the phase relationship of multiple voltage controlled oscillators. The voltage control oscillators provide amplitude modulation of an output signal of the voltage controlled oscillator by adjusting transconductance of amplification devices of the voltage controlled oscillator. Another embodiment of the power amplifier provides buffer circuits at the outputs of the voltage controlled oscillators. The gain or delay of the buffer circuits is varied to provide amplitude modulation of the power amplifier.

Abstract: A super-regenerative receiver uses controlled Q-quenching and may limit the resonant tank circuit amplitude by loading the tank circuit as soon as regenerative oscillation is detected. An amplitude detector is coupled to the regenerative amplifier and controls a Q loading circuit coupled to the tank circuit of the regenerative amplifier. The amplitude detector turns on the Q loading circuit which then stops the regenerative amplifier from oscillating, and the Q-loading remains on for a brief time to insure that the regenerative amplifier has stopped oscillating. After the brief time, the Q loading circuit is turned off and the regenerative amplifier goes into oscillation again. This cycle repeats controllably over and over, resulting in a lower self-induced noise floor and improved received signal sensitivity.

Abstract: Systems and techniques are disclosed relating to wireless communications. These systems and techniques involve wireless communications wherein a device may be configured to recover an information signal from a carrier using a reference signal, detect a frequency error in the information signal; and periodically tune the reference signal to reduce the frequency error.

Abstract: A frequency tracking circuit and method comprising a master crystal oscillator circuit is used for frequency tracking between a handset and a base station comprising a calibration subsystem for taking a temperature measurement, a reference control circuit for determining a numerical value needed to align a handset frequency with a base station frequency, an adder for adding the numerical value to a previous numerical value determined by the reference control circuit, a latch for latching the output of the adder, and a low precision master crystal oscillator for clocking the frequency of the latch. The most significant bit from the latch is input into a phase/frequency detector for forcing a voltage controlled oscillator to track a desired frequency.

Abstract: In order to always maintain a frequency of an oscillator within a proper range, the frequency chages due to temperature and a secular change, a method is disclosed in which the secular change is calculated from past control information, and the frequency of the oscillator is corrected according to the secular change. A storing unit records the past control information for the oscillator. A processing unit calculates the secular change of the frequency of the oscillator from the past control information. Thereafter, the processing unit gives the oscillator new control information for correcting the calculated secular change.

Abstract: An improved low-cost super-regenerative receiver includes sampling phase-locked loop. Phase sampling is controlled by the quench signal (264). In the preferred embodiment, logic state HIGH to logic state LOW transition of the quench signal (264) defines the timing for the event of sampling. While the quench signal (264) is in logic state HIGH, a quenched oscillator is being turned ON and the oscillation amplitude builds-up until a steady-state level is reached. When the oscillator is turned OFF, effective quality factor of an electronically tunable resonator (206) is reduced, by increasing losses in the circuit, thus to ensure aperiodic (non-oscillatory) decay. The resonator's charge—an energy stored on internal reactive components of the resonator (206), which existed at the instant of turning the oscillations OFF, is transferred during precisely defined period of time to the charge holding capacitor (404) of a charge transfer circuit (216).

Abstract: One embodiment of a tuner integrated circuit includes two mixer circuits, an IF amplifier circuit, three oscillation circuits, a PLL circuit, and a reference oscillation circuit. A plurality of terminals are provided at two sides of the tuner integrated circuit and are connected to these elements. Among the terminals, at least an oscillator-connecting terminal for connecting an externally provided oscillator to the reference oscillation circuit, a power supply terminal through which a power supply voltage is supplied, and a ground terminal connected to a ground are provided at one side of the tuner integrated circuit. The power supply terminal and the ground terminal are disposed adjacent to the oscillator-connecting terminal such that they sandwich the oscillator-connecting terminal therebetween.

Abstract: A low-noise current reference circuitry includes a voltage source, a current source, and a controller. The voltage source generates a reference voltage. The current source provides a low-noise output current in response to a control signal. The controller provides the control signal based at least in part on the relative magnitudes of the reference voltage and a voltage derived from the output current. A low-noise voltage reference circuitry includes a reference voltage source, a voltage source, and a controller. The reference voltage source generates a reference voltage. The voltage source provides a low-noise output voltage in response to a control signal. The controller provides the control signal based at least in part on the relative magnitudes of the output voltage and the reference voltage.

Abstract: A linear fractional-N synthesizer includes phase and frequency detection module, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a fractional-N divider. The phase and frequency detection module is operably coupled to produce a charge up signal, a charge down signal, or an off signal based on a phase difference and/or a frequency difference between a reference oscillation and a feedback oscillation. The charge pump circuit is operably coupled to produce a positive current when the charge up signal is received, a negative current when the charge down signal is received, and a non-zero offset current when the off signal is received. The charge pump includes a resistor and a control module. The resistor provides the non-zero offset current and the control module maintains the non-zero offset current at a substantially constant value.

Abstract: A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.

Abstract: A wireless communication system, which is provided with a PLL circuit having a plurality of oscillators and is capable of processing two or more transmit and receive signal different in frequency band from one another according to the switching between the oscillators, has a reset means which resets a voltage applied to each of filter capacitors lying within the PLL circuit to a predetermined voltage when the switching between the oscillators is performed.

Abstract: A transceiver includes a Downstream Signal Processor (DSP), an Upstream Signal Processor (USP), a Local Oscillator (LO), a differencer, a reference signal generator, and an estimator. The DSP receives an initial downstream signal, a downstream LO signal from the LO, and from the estimator a frequency-offset estimate indicative of a free-running frequency offset included in the initial downstream signal. The DSP uses the LO signal and the estimate to frequency down-convert the initial downstream signal, and also to remove the frequency offset from the initial downstream signal, thereby producing a corrected downstream signal. The USP uses both an upstream LO signal from the LO and the estimate to frequency convert an initial upstream signal so as to produce a frequency pre-corrected upstream signal.

Abstract: A communication semiconductor integrated circuit device includes an RFVCO and a TXVCO and is formed over one semiconductor substrate, and has a first operation mode (idle mode) which does not perform transmission and reception, a second operation mode (warmup mode) which performs a preparation prior to the start of transmission or reception, and a third operation mode (transmission or reception mode) which performs transmission or reception. In the first operation mode, two oscillators are deactivated, and the operation of selecting a frequency band to be used in at least the TXVCO which generates a transmit signal, is performed in the second operation mode.

Abstract: A method for improving sensitivity of a RF receiver and a RF receiver designed by the same are provided. The RF receiver, which receives a RF signal, comprises a sampling converting circuit, a decoding circuit, a frequency-hopping circuit, a constant current source and a ring oscillating circuit. The RF receiver outputs a frequency-hopping signal to the frequency-hopping circuit when the decoding circuit determines that the digital data converted from the RF signal is not equivalent to each of the internal preset data. The frequency-hopping circuit outputs a frequency-hopping current to the ring oscillating circuit to change a sampling clock of the RF receiver.

Abstract: A method and apparatus for calibrating a reference oscillator and use of a calibrated reference oscillator is disclosed. To gain cost reduction advantages, a less accurate reference oscillator is utilized in a wireless communication device. The cost benefit is gained at the expense of reference oscillator accuracy in that its inability to generate a signal with a highly accurate reference frequency inhibits acquisition of a carrier or pilot signal. To compensate, a correction factor is generated by minimizing the difference between the reference oscillator signal and a signal of known frequency, such as an external reference signal. Access to the reference oscillator signal, or a signal related thereto, may be gained via the communication device antenna or a test port. The correction factor may be stored in the wireless communication device for use in conjunction with the reference oscillator to thereby generate the highly accurate reference signal at the reference frequency.

Abstract: A transceiver for a code division multiple access communication system comprises a receiver to receive coded information signals and a transmitter to transmit coded information signals. A local oscillator provides a time and frequency reference for the receiver and the transmitter. A timing controller provides timing signals for the receiver and the transmitter. A signal processor decodes received signals to determine a common error associated with the timing controller. A timing correction circuit smoothly adjusts the timing of the coded information signals transmitted by the transmitter responsive to the timing error to reduce the timing error over a desired time interval.

Abstract: Method for acquiring frequency of a desired channel having a carrier frequency FMAIN, for a dynamic receiver frequency FMOBILE, from a starting frequency FSTART, in the presence of high power adjacent interfering channels, wherein the starting frequency FSTART is shifted from FMAIN by not more than a predetermined frequency gap ?F, the method includes the steps of determining a first frequency boundary and a second frequency boundary, detecting channels within a filtering bandwidth, selecting a dominant channel from the detected channels, progressing the dynamic receiver frequency FMOBILE towards the carrier frequency of the dominant channel, detecting when the step of progressing has exceeded one of the first frequency boundary and the second frequency boundary, restarting the step of detecting channels, from the other of the one of the first frequency boundary and the second frequency boundary, and repeating from the step of detecting channels.

Abstract: A receiver for use in a wireless communication system includes a voltage controlled oscillator and estimating means for obtaining a frequency estimate to adjust the voltage controlled oscillator, thereby correcting an oscillator frequency error. The estimating means performs a number of block correlations on a received signal with a known midamble reference. The output of the block correlators are conjugately multiplied and summed to produce a low-variance estimate of the phase change between correlators. A number of the largest summed values are located, and the located values that exceed a detection threshold are summed to provide a single complex number whose angle is an estimate of the phase change between the correlators.

Abstract: A mobile communications device using a common oscillator for communication and global positioning system (GPS) functions. In one embodiment, a communications unit receives a precision carrier frequency signal from a source and generates a reference signal that is used to calibrate a common oscillator.

Abstract: A phase locked loop that includes such a loop filter, the phase locked loop includes a difference detector, programmable charge pump, fixed loop filter, voltage controlled oscillator and adjustable divider module. The difference detector is operably coupled to determine a different signal based on differences in phase and/or frequency between a reference oscillation and a feedback oscillation. The programmable charge pump is operably coupled to generate a charge current based on the difference signal and a scaling signal. The fixed loop filter is operably coupled to convert the charge current into a control voltage. The voltage controlled oscillator generates an output oscillation based on the control voltage and the adjustable divider module generates the feedback oscillation based on the output oscillation and a divider value. The scaling module is operably coupled to produce the scaling signal based on the selected divider.

Abstract: A calibration circuitry includes an adjustable capacitor, a voltage generator, a reference voltage generator, and a controller. The reference voltage generator provides a reference voltage. The voltage generator provides a measurement voltage that depends on the capacitance of the adjustable capacitor. The capacitance of the adjustable capacitor varies in response to a control signal. The controller provides the control signal based on the relative values of the reference voltage and the measurement voltage.

Abstract: A control unit measures a phase error between a reference timing of a mobile station and a reception timing from a base station based on reception data from a reception unit and a count from a reference timing counter unit, determines a frequency deviation correction value calculation period corresponding to the measured phase error, and outputs it to a frequency deviation correction value calculation unit. The frequency deviation correction value calculation unit does not calculate a deviation at every reception time when intermittent reception is repeated, but calculates a deviation at intervals following the frequency deviation correction value calculation period given from the control unit.

Abstract: Determination and processing for fractional-N programming values. The present invention is operable to receive a clock signal (CLK) and to transform that CLK into a new CLK, when necessary, for use by various circuitries within a system. The present invention is operable to generate two different CLKs for use by a radio frequency (RF) circuitry and a baseband processing circuitry in certain embodiments. The present invention employs a measurement circuitry and to characterize a first CLK and uses a fractional-N synthesizer to perform any necessary processing to generate the one or more CLKs to the other CLKs within the system. The first CLK may be received from an external source or it may be generated internally; in either case, the present invention is able to modify the CLK into another CLK for use by other circuitries within the system or for use by another external device.

Abstract: A radio transceiver includes a charge pump formed within a local oscillator that adjusts a voltage input to a voltage-controlled oscillator in a manner that flattens a response curve for small changes in voltage due to a variety of effects including channel length modulation. Thus, a local oscillation tends to provide a greater degree of stability. More specifically, the charge pump of the transceiver includes a pair of feedback circuits that source an additional amount of current into a filter to slightly increase a voltage input to the voltage-controlled oscillator in response to small upward changes in output voltage levels (input with respect to the voltage-controlled oscillator). Similarly, when the output voltage level drops slightly, a second feedback circuit causes a small amount of current to be sinked from the output node thereby slightly decreasing the input voltage to the voltage-controlled oscillator.

Abstract: A tuner comprises a first frequency changer with a mixer and local oscillator. The output of the frequency changer is connected to a first intermediate frequency filter, whose output is connected to a second frequency changer. The output of the frequency changer is connected to the usual second intermediate frequency filter and to an amplitude detector. A reference oscillator is connectable under control of a controller via a multiplexer to the input of the mixer. During an alignment mode of the tuner, the reference signal from the oscillator is supplied to the mixer and the local oscillators and are controlled by the controller to sweep across a frequency range encompassing all possible pass frequencies of the filter. The controller monitors the output of the detector so as to establish the frequency response of the filter. Frequency offsets are then stored in the synthesizers and so as to center each channel during a reception mode on the actual center frequency of the filter.

Abstract: A receiver uses an adaptive algorithm to tune a low-cost crystal oscillator according to a temperature compensation profile so as to produce a precision master reference frequency despite temperature, initial tolerance, and aging effects. An automatic frequency control system also tunes the crystal oscillator. The adaptive algorithm adjusts the temperature compensation profile for the crystal oscillator according to the adjustments made by the automatic frequency control should a received signal's quality factor exceed that associated with the temperature compensation profile.

Abstract: A highly integrated GPS RF Front End which uses a single conversion stage employs an image rejection mixer stage to eliminate the need for an image reject RF bandpass filter. Also a relatively high sample rate A/D is employed which allows a timeless monolitic IF Filter to be used. The disclosure also discusses a GPS Front End topology that is easily integrated from industry standard building blocks. With the broad variation in potential receiver designs, the present invention includes some specific receiver topologies that lend themselves to a high level of integration. The specific designs presented here are comprised of industry standard building blocks and functions that have been described elsewhere in the related art.

Abstract: A method and apparatus for generating a self-correcting local oscillation includes processing that begins by generating a synthesized frequency from a reference frequency. The processing then continues by dividing the synthesized frequency by a divider value to produce a divided frequency. The processing continues by generating an auxiliary frequency and mixing the auxiliary frequency with the divided frequency to produce a corrected frequency. The processing then continues by mixing the corrected frequency with the synthesized frequency to produce a local oscillation.

Abstract: A local oscillator architecture provides a signal at an output frequency with reduced pulling effect. A voltage controlled oscillator (VCO) generates a first signal having a frequency that is a fraction of the output frequency. A frequency shifter generates a second signal with a frequency substantially equal to the difference between the VCO frequency and the output frequency. Single-sideband mixers are used to produce output signals at the sum of the VCO frequency and the shifted frequency while suppressing an unwanted sideband at the difference of the two frequencies.

Abstract: A circuit configuration having a filter, for example a bandpass filter, and a method for its operation are specified, which the circuit configuration allows for compensation of a frequency error, for example between an actual mid-frequency and a nominal frequency. A first mixer, upstream of the filter and a second mixer downstream from the filter are provided. A signal and a respective oscillation frequency are each supplied to respective inputs of the first and second mixers. The oscillation frequencies are mixed as a function of the frequency error in frequency generators such that the signal at the intermediate frequency is matched to the filter characteristics of the filter which is subject to tolerances. In consequence, filters that satisfy the stringent requirements for WCDMA mobile radio applications, but by virtue of the manufacturing technique, have an excessive mid-frequency error, can be used, for example, in heterodyne receivers.