Abstract: A method and apparatus for improving the sensitivity of a radio frequency (RF) receiver at certain frequencies suffering from co-channel interference. In the preferred embodiment, when a reference frequency, FREF, generates significant harmonics for a received RF signal in a selected channel, the reference frequency is varied or offset by a small amount, &Dgr;F. The harmonics of the offset reference frequency, F′REF=FREF±&Dgr;F, are thereby shifted away from the frequency of the received RF signal, thus reducing co-channel interference. The offset amount &Dgr;F is chosen such that the same injection frequency synthesized from FREF can still be synthesized from FREF±&Dgr;F by shifting N by an integer amount, preferably to N+1 or N−1. However, the invention encompasses shifting N by other integer amounts.

Abstract: A mobile radio for use in multiple different frequency plans is disclosed. The multiple different frequency plans, such as land-based plans (cellular, land mobile radio, etc.) and satellite-based plans may employ different frequency bands and, within those different bands, different frequency channel step sizes. The mobile radio employs only a single loop synthesizer to accommodate all of the different plans, including all of the different channel step sizes. It does so by employing a dynamically programmable divider circuit within the single loop synthesizer for macro-adjustment of the local oscillator frequency and a dynamically adjustable reference oscillator within the single loop synthesizer for micro-adjustment of the local oscillator frequency depending upon a recovered carrier signal.

Abstract: This invention provides a method of generating multiple frequencies for use in a digital data transmission system including a remote transmitter and receiver. The reference frequency used in the transmitter is replicated in a remote receiver. A single crystal oscillator is used to generate a reference frequency similar to that used in the transmitter. The receiver reference frequency is manipulated by dividing the frequency into required multiple frequencies for use within the receiver. A constant comparison is made between the clock signal received in the transmitted data stream with the receiver reference frequency and the divisors are adjusted accordingly to maintain the clock frequency in the receiver within a predetermined tolerance range. This allows the output signal for display from the receiver to match the quality of the input display provided to the transmitter.

Abstract: An electronic system, such as a wireless telephone handset (10), having multiple voltage-controlled oscillators (26, 28) so that the system can operate in a selected one of multiple frequency bands, is disclosed. Each of the voltage-controlled oscillators (26, 28) is associated with one of multiple loop filters (32, 34), which filter the control voltage (CP1, CP2) responsive to which the frequency of oscillation of the voltage-controlled oscillators (26, 28) controlled. Only one of the voltage-controlled oscillators (26, 28) is enabled at any one time, responsive to a control signal (VCOSEL). Synthesizer circuitry (30) includes a phase detector (44) which is coupled to a common node (VCOCLK) at which outputs of the voltage-controlled oscillators (26, 28) are coupled; the phase detector (44) compares the phase of this signal (VCODIV) to a reference signal (REFDIV) based on a reference clock (REFCLK), and controls a charge pump (46) accordingly.

Abstract: Parasitic feedback is prevented in a transmitter, a modulator, or a demodulator from having an interfering influence on the circuit section that generates the mixed frequency. The circuit has a main oscillator and a subordinate oscillator connected downstream of the main oscillator. The main oscillator generates a signal having an x.sup.th harmonic that serves to excite the subordinate oscillator. Furthermore, a frequency divider is connected downstream of the subordinate oscillator. The frequency divider divides the frequency of an output signal of the subordinate oscillator by an integer divider value. The divider value differs from the value x.

Abstract: A frequency synthesizer module with temperature compensation of a crystal oscillator circuit frequency controlled by a varactor. A module memory contains information characterizing a temperature dependency of a crystal which is applied to the varactor to temperature compensate the crystal in response to a temperature sensor signal. The module includes at least one locked loop circuit including a loop filter, at least one associated frequency divider, and a switchable dual band voltage controlled oscillator. The crystal oscillator is coupled to the at least one locked loop circuit and the frequency of the crystal is controlled by the memory via the varactor such that a temperature compensated output frequency is provided by the module.

Abstract: In an apparatus for intermittently receiving a broadcasting signal at a reception timing which appears by a predetermined intermittent reception cycle and is determined by using a clock generator (5) for generating a clock signal of a clock frequency liable to vary due to an environment temperature, a first section (309) determines a maximum count by multiplying the predetermined intermittent reception cycle by the clock frequency at a particular time instant. Given the maximum count at the particular time instant, a second section (308) repeatedly carries out a counting operation of counting up a count to the maximum count in response to the clock signal to produce, when the count is equal to the maximum count, a coincidence signal specifying the reception timing.

Abstract: A wireless mobile terminal for a wireless communication system comprises a wireless transceiver, a global positioning system (GPS) receiver, wherein the wireless transceiver and the GPS receiver share a frequency reference signal. The frequency reference signal can be multiplied by an integer multiple to create a first local oscillator for a signal conversion to an intermediate frequency for signal processing of the GPS signal. In addition, the frequency reference signal can also be divided into a lower frequency to create a second local oscillator for a conversion to a second intermediate frequency. The frequency reference signal can also be divided to create a frequency necessary for other signal processing, such as an analog-to-digital converter sampling signal at the GPS receiver. The frequency reference signal can be taken from different places within the frequency synthesis mechanism of the wireless transceiver.

Abstract: A frequency stabilization circuit includes a local oscillator, a mixer, a level comparator, a frequency comparator, and a controller. The local oscillator outputs a local oscillation signal in accordance with a control voltage. The mixer converts a received radio frequency signal into an intermediate frequency signal using the local oscillation signal from the local oscillator. The level comparator compares a DC voltage corresponding to the intermediate frequency signal from the mixer with a reference voltage to determine whether the reception electric field level of the radio frequency signal is high or low. The frequency comparator compares the frequency of the intermediate frequency signal from the mixer with the frequency of the reference signal to output frequency difference information. The frequency comparator outputs previous frequency difference information when the comparison result of the level comparator indicates a decrease in reception electric field level.

Abstract: A double superheterodyne type receiving circuit having a first local oscillating circuit for converting a received signal into a first intermediate frequency signal and a second local oscillating circuit for converting the first intermediate frequency signal into a second intermediate frequency signal, comprising an oscillator 16 composing the first local oscillating circuit, a first variable frequency divider 17 composing the second oscillating circuit for dividing the frequency of an output signal of the first oscillator, a second variable frequency divider 18 for dividing the frequency of an output signal of the first variable frequency divider, a variable frequency dividing controlling circuit 23 for controlling frequency dividing values of the first and second variable frequency dividers on the base of an exponential function relation, at least one fixed frequency divider 19 for dividing the frequency of an output signal of the second variable frequency divider 18, a reference oscillator 20 for outputtin

Abstract: A PHS relay station demodulates a digital signal from a received radio-frequency signal by use of a reproduction clock produced from the digital signal. The relay station has an oscillator which generates a clock and a variable-ratio frequency divider for the clock outputted from the oscillator. A bit clock is produced from the output of the divider. A signal processor processes the digital signal by use of the bit clock. A detector detects a specific code in the digital signal in synchronism with the bit clock. The length of time that passes after the specific code detection signal is generated until the reproduction clock changes its level is detected as the phase deviation between the reproduction clock and the bit clock. The phase deviation is eliminated by temporarily changing the frequency division ratio of the divider in accordance with the amount of the deviation.

Abstract: A method and apparatus for reducing power consumption in a communication device. In a standby mode, a relatively high power clock with a high degree of accuracy is powered down and a lower power, low frequency clock is used to maintain system synchronization. Synchronization means are provided to improve the accuracy of the low frequency clock during the standby mode.

Abstract: A method and apparatus for controlling frequency synchronization in a frequency correction feedback loop of a radio telephone. A processor in a frequency update controller ascertains increment/decrement values pro-proportionally related to confidence levels representing a ratio that a likelihood probability of estimated offset frequecies of an input carrier signal are accurate in proportion to a likelihood probability that the estimated offset frequencies are inaccurate. The processor adds or subtracts the value to a counter depending on its sign. When the counter reaches a certain predefined positive number, the counter is decremented by this number and the processor increases the frequency of a reference oscillator frequency. When the counter reaches a certain predefined negative number, the counter is incremented by the absolute value of the negative number and the processor decreases the frequency of the reference oscillator frequency.

Abstract: A reference oscillator (118) in a communication device (100) such as a radiotelephone is controlled by temperature compensating the reference oscillator (118). At the time of manufacture, characterizing data are stored in non-volatile memory (128) in the communication device (100). When the communication device (100) is powered up, the characterizing data are read and used to provide an initial correction (206) to the output frequency of the reference oscillator (118). Subsequently, an automatic frequency control operation is performed using the RF signal received from a remote transmitter as a reference signal. A frequency correction is determined (214) in the form of a frequency step size and step direction. The output frequency of the reference oscillator is repeatedly stepped until frequency error is minimized.

Abstract: A reception clock signal used for a data sampling unit to sample received data is generated by a reception clock generator based on a reference clock signal, which is generated by a reference clock generator based on a reference bit rate frequency. The reference bit rate frequency is produced by a reference oscillator which is controlled by a control voltage. The control voltage is generated by a phase difference-to-voltage converter depending on the phase difference, detected by the reception clock generator, between the timing of a change in the received data and the reference clock signal. If good reception sensitivity is not available due to a phase difference, then the phase difference-to-voltage converter generates a control voltage in a manner to eliminate the phase difference, and applies the generated control voltage to a variable capacitor connected to the reference oscillator for automatically adjusting the reference bit rate frequency.

Abstract: A vehicle structural accessory includes one or more electronic accessories. One electrical accessory which may be provided is an electronically trainable transmitter which is trainable to generate a control signal which will actuate a garage door opening mechanism. Another electronic accessory which may be included is an electronic compass. Yet another device is an electronically adjustable mirror having parameters set for each driver of a vehicle. The electronically adjustable rearview mirror and the electronically trainable garage door opener may be advantageously provided with a keyless entry system.

Abstract: Radio equipment based on an AFC system comprising a local oscillator, a reference frequency oscillator, a receiver, a frequency comparator, an AFC controller, a temperature detection sensor, and a memory. The AFC controller inputting, when starting AFC, reads out a control frequency corresponding to the detected temperature inputted thereinto to control the reference frequency for the reference frequency oscillator. When a lock signal is inputted thereinto, the detected temperature and control frequency are stored in a memory.

Abstract: A phase locked loop (PLL) circuit for use as a demodulator and other applications. The PLL circuit (200) comprises a phase detector (210), a transconductance amplifier (212) and a current controlled oscillator (ICO) (214). The phase detector has two signal inputs and two outputs, and detects a phase difference between signals at its inputs. A capacitor C1 is connected to the output of phase detector (210) and develops an output voltage signal vo(t). A transconductance amplifier (212) is coupled to the capacitor C1 and converts the output voltage signal vo(t) to an output current signal. The ICO (214) is coupled to the transconductance amplifier (212) and the second output of the phase detector (210) and generates an output signal having a frequency which is proportional to an input current signal. The output signal of the ICO (214) is coupled to the second signal input of the phase detector (212).

Abstract: An apparatus and method for automatically controlling a reference frequency (120) in a receiver (104) that receives either analog (116) or digital (136) information signals. The receiver (18) includes a frequency translator (109) for translating a carrier frequency (137) to an intermediate frequency (118) and maintaining the intermediate frequency (118) at a desired value responsive to the reference frequency (120). A first measure of frequency error (211, 212) is detected between the reference frequency (120) and the intermediate frequency (118). A second measure of frequency error (125, 126) is detected between the reference frequency (120) and the intermediate frequency (118). A current signal (213) is produced responsive to the first measure of frequency error (211, 212) when the receiver receives the analog information signal (116) and responsive to the second measure of frequency error (125, 126) when receiver receives the digital information signal (136).

Abstract: A communication system which includes a receiving section having a frequency convertor for converting a received signal into an intermediate frequency signal by mixing with a local oscillation signal, and a demodulator for demodulating the received signal converted into the intermediate frequency signal, a transmission section for modulating a transmission signal received thereby, to transmit the so modulated signal, and an input/output section for receiving the demodulated signal from the receiving section and outputting it externally and receiving the transmission signal externally and outputting it to the transmission section.

Abstract: This invention relates to an abnormal synchronization preventing device used in a multiple value quadrature modulation type radio device and the abnormal synchronization preventing device includes a monitoring circuit for monitoring the carrier pull-out based on demodulated base band signals to output a carrier pull-out alarm signal, an abnormal synchronization detection circuit for sampling the reception signal level at a speed twice the transmission speed of reception data according to identification data and detecting abnormal synchronization according to whether or not the detection area of sampled data lies in a specified area, an abnormal synchronization preventing circuit for generating a signal for a preset period of time when abnormal synchronization is detected in a case where the carrier pull-out alarm signal is not output, and a selection circuit for receiving a reference signal used for generating a reference carrier frequency signal having a frequency close to the frequency of the carrier wave a

Abstract: A wireless transmission system includes a plurality of terminal units, a specific one of which is provided with a transmission/receiving circuit that transmits a reference signal of a local oscillation frequency, while all others of which are provided respectively with a transmission/receiving circuit that prepares, on the basis of the reference signal received, a local oscillation frequency signal for frequency conversion of transmitting/receiving frequency signal and intermediate frequency signal, to thereby realize the system at lower costs even when a high local oscillation frequency is employed.

Abstract: A demodulation circuit having an automatic frequency control (AFC) function in which a received input high frequency signal is mixed with a first reference signal to once form an intermediate frequency signal, the intermediate frequency signal is then mixed with a second reference signal having an adjustable frequency through such a frequency correction unit as a matched filter unit to obtain a demodulation signal having a maximum power value kept as a base band signal. For the purpose of preventing the failure of maintaining the AFC function caused by the limited correctable range of the frequency correction unit such as the matched filter unit, when the correctable range of the frequency correction unit reaches its limit, the frequency of the first reference signal is separately adjusted to thereby keep the frequency of the intermediate frequency signal always within the correctable range of the frequency correction unit.

Abstract: A frequency control circuit, and associated method, for a receiver operative to receive a TDMA signal transmitted by a transmitter in a TDMA communication system. A first frequency detector generates a first frequency control signal. A second frequency detector, comprised of a portion of a decision-directed demodulator, generates a second frequency control signal. The first frequency control signal is utilized to effectuate frequency control when a signal is continuously received by the receiver, such as times immediately subsequent to initial powering of the receiver as the receiver becomes synchronized with the TDMA signal transmitted thereto. Onces a receiver becomes synchronized to the transmitter, the receiver need only be powered during intermittent time periods when the TDMA signal is transmitted to the receiver.

Abstract: An offset frequency converter for the intermediate frequency (IF) stages of a multi-channel radio frequency (RF) phase/amplitude measurement receiver, particularly useful for measuring the performance characteristics of antennas. The converter allows use of noncoherent transmitter and receiver local oscillator sources which utilize digital frequency synthesizers and enables harmonic mixing to be employed when the tuning resolution of the receiver local oscillator is incremental. The converter samples an incoming first intermediate frequency signal IF.sub.1 in a reference channel, which typically is obtained by mixing an LO source in the receiver with an incoming signal from a reference antenna. The IF.sub.1 sample is then upconverted with an upconversion signal to a higher frequency, filtered, and the downconverted with a downconversion signal to an IF.sub.1 +IF.sub.2 signal offset from the IF.sub.1 sample by a lower second intermediate frequency IF.sub.2. The added frequency offset IF.sub.

Abstract: A receiver for receiving a transmitted signal comprising first and second bandwidth limited component signals modulating a single high frequency carrier in phase quadrature with the first component signal as originally transmitted including an identification signal has a source of a reference signal subject to phase error. Circuitry combines the received transmitted component signals with the reference signal to provide first and second demodulated signals characteristic of the first and second component signals respectively. A detector responds to the first and second demodulated signals to provide first and second detected components of the identification signal. Feedback circuitry responds to the detected components of the identification signal by providing a correction signal that is applied to the source of reference signal to reduce the phase error.

Abstract: A receiver which converts the RF carrier to a very low frequency and incorporates a PLL demodulator which allows the IF to be AC coupled. This PLL demodulator does not include the IF filters. The bandwidth of the PLL demodulator is wide enough to demodulate FM. Also, components of the receiver can be switched to a transmission mode capable of FM or PSK modulation with a simple circuit. Finally, the receiver includes an AM or PSK coherent amplitude detector which is modified into an imageless spectrum analyzer.

Abstract: Receiver (1-9) provided with a frequency control loop (2-6) for automatic fine tuning, consecutively incorporating a controllable oscillator (6) which is tunable in frequency by means of a variable capacitance diode (D), a mixer stage (2) to which the signal from the controllable oscillator (6) is applied for converting an RF receiver signal into an intermediate frequency signal, a frequency voltage converter (4) tuned to a fixed intermediate frequency for converting frequency deviations of the intermediate frequency signal relative to the fixed intermediate frequency into amplitude variations of the frequency voltage converter (4) output signal relative to a refrence value, a control signal generating circuit (5) for deriving a control signal for the variable capacitance diode (D) of the controllable oscillator (6) from the output signal of the frequency voltage converter (4), which at least partly compensates the asymmetrical diode capacitance-voltage characteristic.

Abstract: An AFC/AGC circuit utilized in a receiving apparatus of a ground station for the satellite communication system comprising a digital AFC/AGC controller functioning such that;when the pilot signal is not received, the gain control voltage and the frequency control voltage are respectively set to appropriate values based on the predetermined data;when the pilot signal starts to be received, the gain and frequency control voltages are switched from the set values to the values obtained from the digital AFC and AGC processings, respectively;so long as the pilot signal is being received, the signal generated in the digital AFC and AGC processings are sampled by respective sampling clock signals and the gain and frequency control voltages are determined in accordance with the sampled data; andwhen the pilot signal stops being received, each of the gain and frequency control voltages is held at the value sampled by a last pulse of the sampling clock signal immediately before the stopping, respectively.

Abstract: A receiver for frequency modulated signals, having down-conversion to a baseband, zero intermediate frequency for selectivity, followed by up-conversion to a non-zero IF for amplification, limiting, and demodulation.A phase-lock loop locks the frequency of the down-conversion source to the center frequency of the signal coupled to the baseband IF, converting the signal to precisely zero frequency. This avoids the beat note often found in direct conversion systems. The phase-lock loop additionally provides inherent demodulation of the FM signal.The received FM signal is coupled to the baseband IF through a radio frequency amplifier for improved sensitivity and local oscillator isolation, or through a first IF comprising a mixer, local oscillator, filter, and amplifier.

Abstract: A color subcarrier generator for PAL uses a one-quarter horizontal frequency signal from a sync generator to sample the subcarrier signal. The sampled signal is phase and frequency compared with a 25 Hz (one-half vertical frequency) signal from the same sync generator to control the frequency of the subcarrier signal. Thus the required 25 Hz PAL offset is obtained. The one-quarter horizontal frequency sampling signal can also be used in NTSC and SECAM subcarrier generators.

Abstract: Disclosed is a pulsed FM receiver with automatic centering of the intermediate frequency at the true center of the input filter passband. The frequency standard of the frequency discriminator which controls the local oscillator frequency is adjusted to produce zero discriminator output during the period between signal pulses. The discriminator frequency standard remains automatically aligned with the center of the input filter passband and the input bandwidth may then be reduced for optimum receiver sensitivity.

Abstract: A chrominance subcarrier regeneration network having high stability, the network being adapted for use in a video tape recorder and including a phase detector for comparing the phase of a gated subcarrier burst of a video signal with that of a subcarrier regenerated signal to develop an error signal; a voltage controlled oscillator driven by the error signal to develop a corrected signal at a frequency substantially below that of the subcarrier burst; and a crystal oscillator, mixer and filter for translating the frequency and filtering the corrected signal to develop the regenerated signal.

Abstract: A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A programmable frequency divider counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator in the tuner also is applied. The phase comparator output provides a tuning voltage for controlling the tuning of the local oscillator. A microprocessor is used to control the count of the programmable frequency divider and initially to set a count corresponding to the selected channel in a counter connected between the output of the local oscillator and the phase comparator. The AFT discriminator signal is used to sense the presence or absence of a properly tuned condition and to control the operation of the microprocessor for establishing the count in the programmable frequency divider counter.

Abstract: A frequency-tracking feedback circuit for acquiring a communication carrier signal from a relatively noisy environment. The circuit includes a digital phase-frequency detector, a limiter, a mixer, and a voltage-controlled oscillator, connected in a long control loop in such a manner that an input band of signals is translated in frequency until the desired carrier is centered within a relatively narrow acquisition window. The characteristics of the loop are such that acquisition may be achieved even when the total power of the noise in the input signal band exceeds the carrier power, provided that the noise is relatively uniformly distributed over the input band. A technique is also disclosed for compensating from any unbalance in the noise spectrum, so that relatively low carrier-to-noise ratios can be tolerated.

Abstract: A downconverter having a voltage controlled local oscillator supplied with a control DC voltage, obtained from a frequency discriminator and responding to variations of the difference between a reference produced by a stable oscillator and an output signal frequency of the downconverter is employed for facilitating output channel alterations without changing local oscillator stability characteristics. When used as a television channel converter, it changes a channel in the UHF or SHF band to VHF channels.

Abstract: An interface circuit that couples the output of a differential AFC detector to a tuner and in so doing provides a single-ended control signal and a substantially constant reference signal. A bridging circuit combines the differential outputs to effect a substantially constant signal which is appropriately scaled by a referencing circuit so as to develop the reference voltage required. A dividing circuit coupled to one of the differential outputs develops an AFC control voltage having the range required to accommodate the tuner's AFC-responsive circuitry.

Abstract: An electronic digital channel-selecting apparatus wherein a digital signal corresponding to a selected television channel is read out of a digital memory to be converted into an analog tuning voltage by a digital-analog converter; and the analog tuning voltage is applied to a voltage-controlled tuner which in turn is made to tune with the selected television channel. An AFT circuit is coupled to the tuner to detect its tuning condition. When the tuner does not accurately tune with the selected television channel, AFT clock pulses are supplied to an AFT counter to correct the analog tuning voltage depending on varying count numbers in the AFT counter. A clock changer is provided to switch AFT clock pulses having different frequencies such that the AFT clock pulses are successively applied to the AFT counter in the decreasing order of their frequencies during the AFT control.

Abstract: In a radar or radio frequency signal regenerator an incoming RF signal is mixed with the output of a single-side-band generator to produce a derived IF signal. The single-side-band generator operates to mix together the outputs of two local oscillators to provide the signal mixed with the incoming RF signal. A frequency lock loop circuit is used to compare the frequency of the derived IF signal with a reference IF frequency and the frequency of one of the local oscillators is varied to correct any frequency error and thus to make the frequency of that local oscillator equal to the incoming RF frequency.

Abstract: A digital tuning receiver having an electrically tuneable tuner and an AFT circuit is driven in a unidirectional sweep by the D/A converted output of a reversible counter. The reversible counter continues to count input pulses, and the unidirectional sweep continues until stopped by the reception of a signal which produces a first signal from an AFT frequency discriminator followed within a predetermined time by a second signal of opposite polarity from the AFT frequency discriminator. The number stored in the stopped reversible counter may be further adjusted by AFT signals and stored for later recall. If the second signal is not received within a predetermined time, as occurs with spurious beat signals, the sweep is not stopped but continues until a proper signal is received.

Abstract: The local signal generation arrangement employed in a radio communication system for transmitting and/or receiving an upper sideband (USB) and a lower sideband (LSB) signal, but not simultaneously, employs a method in which the generation and/or detection of both USB and LSB signals is accomplished by utilizing only one bandpass filter, a so-called single sideband (SSB) filter, together with a balanced modulator arranged to receive a carrier signal produced from an oscillator whose frequency is accordance with the characteristic frequency of either of a pair of crystal resonators, which correspond to the upper cut-off and the lower cut-off frequencies of the SSB bandpass filter, respectively. The output signal from the said SSB filter is referred to herein as the intermediate frequency (IF) signal.The local signal generation arrangement includes a phase-locked loop (PLL) including at least a phase comparator, a low pass filter, and a voltage-controlled oscillator (VCO).

Abstract: A heterodyne phase lock system is disclosed having a plurality of oscillator circuits, a similar plurality of heterodyne (mixer-filter) circuits representing an input circuit, and a similar plurality of heterodyne circuits representing a control circuit, at least one of the oscillator circuits being a voltage controlled oscillator (VCO) circuit. The heterodyne circuits of the input circuit are cascaded, i.e., linked each to the other, successively, and the heterodyne circuits of the control circuit are likewise cascaded. Each oscillator is linked to a pair of heterodyne circuits, i.e., to one heterodyne circuit in the input circuit and to one heterodyne circuit in the control circuit, and applies a common output signal to said pair of heterodyne circuits.