Stereolithography Patents (Class 700/120)
  • Patent number: 6760641
    Abstract: A lithography system and method for calculating an optimal discrete time trajectory for a movable device is described. A trajectory planner of the lithography system calculates an optimal discrete time trajectory subject to maximum velocity and maximum acceleration constraints. The trajectory planner begins by calculating a continuous time, three-segment trajectory for a reticle stage, a wafer stage or a framing blade, including a first phase for acceleration at the maximum acceleration to the maximum velocity, a second phase for travel at the maximum velocity and a third phase for deceleration at the negative maximum acceleration to a final velocity. Next, the trajectory planner converts continuous time, three-segment trajectory to a discrete time trajectory. The time of execution of the resulting trajectory is at most three quanta greater than the time of execution of the continuous time trajectory. One advantage of the system is the reduction of scanning times of a lithography system.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: July 6, 2004
    Assignee: ASML Holding N.V.
    Inventor: Roberto B. Wiener
  • Patent number: 6742168
    Abstract: The present invention is generally directed to a method and a structure for calibrating a scatterometry-based metrology tool used to measure dimensions of features on a semiconductor device. In one illustrative embodiment, the method comprises measuring a critical dimension of at least one production feature formed above a wafer using a scatterometry tool, measuring at least one of a plurality of grating structures formed above the wafer using the scatterometry tool, each of the grating structures having a different critical dimension, and correcting the measured critical dimension of the at least one production feature based upon the measurement of the at least one grating structure.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: May 25, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Homi E. Nariman
  • Patent number: 6721939
    Abstract: Electron beam (e-beam) shot linearity monitoring is disclosed. A pattern is written that has a predetermined size and a predetermined form in a predetermined position on a substrate, such as a semiconductor wafer, a reticle, or a photomask. The pattern writing fixes the e-beam shot size, as located along one or more critical dimensions of the pattern. The critical dimensions are then measured, where their variations reflect the e-beam shot size linearity. Thereafter, deficiencies in the e-beam shot size linearity can be compensated for, to allow for properly produced semiconductor patterns.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: April 13, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Wen-Chuan Wang, Tyng-Hao Hsu, Chin-Hsiang Lin
  • Patent number: 6678571
    Abstract: An improved slicing technique is disclosed that employs micro-slicing or intermediate slices by identifying intermediate triangle vertices in the STL data and passing slice layers through each intermediate vertex to create a final build object or part that has smoother contouring, greater accuracy and an improved surface appearance than parts obtained using prior slicing methods.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: January 13, 2004
    Assignee: 3D Systems, Inc.
    Inventors: Chris R. Manners, Rajeev B. Kulkarni
  • Patent number: 6665570
    Abstract: A computer-implemented method for generating a computer model of one or more teeth by receiving a digital data set of meshes representing the teeth; creating a parametric representation of the digital data set; and displaying the computer model of the teeth using the parametric representation. The model can be modified or transmitted for viewing or for fabricating dental appliances.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: December 16, 2003
    Assignee: Align Technology, Inc.
    Inventors: Elena Pavloskaia, Huafeng Wen
  • Patent number: 6665574
    Abstract: There is provided a method of forming a tool for performing a desired tooling task upon an unfinished part to form a finished part. The method may comprise the step of creating a computer model of the tool corresponding to the unfinished part. Moreover, the method may further comprise using the computer model to stereolithographically create the tool.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: December 16, 2003
    Assignee: Northrop Grumman Corporation
    Inventor: Chris E. Farren
  • Patent number: 6660209
    Abstract: A variety of support structures and build styles for use in Rapid Prototyping and Manufacturing systems are described wherein particular emphasis is given to Thermal Stereolithography, Fused Deposition Modeling, and Selective Deposition Modeling systems, and wherein a 3D modeling system is presented which uses multijet dispensing and a single material for both object and support formation.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: December 9, 2003
    Assignee: 3D Systems, Inc.
    Inventors: Richard N. Leyden, Jeffrey S. Thayer, Bryan J. L. Bedal, Thomas A. Almquist, Charles W. Hull, Jocelyn M. Earl, Thomas A. Kerekes, Dennis R. Smalley, Christian M. Merot, Richard P. Fedchenko, Michael S. Lockard, Thomas H. Pang, Dinh Ton That
  • Patent number: 6658641
    Abstract: An object of the present invention is to accurately verify errors, etc., in programs when corrections of mask data are carried out by the programs. In order to correct the mask data based on predetermined conditions, a method for mask data verification according to the present invention comprises the steps of preparing corrected mask data by using a plurality of programs each of which has a different algorithm, comparing each of corrected mask data which is prepared in the previous step and as a result of the comparison, if there are differences among the corrected mask data, extracting errors which cause problems as mask data from the differences.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: December 2, 2003
    Inventors: Isao Ashida, Kazuhisa Ogawa
  • Patent number: 6652797
    Abstract: A method for determining the areas of resin to be cured in an optical stereolithography process for rapid prototyping using sequential laser curing of layers of a resin having a selected thickness to produce a desired shape of cured resin. The method includes the steps of generating a computer model of desired shape and dividing the model into layers of thickness equal to the thickness of the layers each defining an area of resin to be cured. A set of layers including and sequentially adjacent an intermediate layer is selected and the areas in the intermediate layer of resin which would be oversized by laser curing of layers later in the curing sequence is determined. The 2-D layer data used to build a 3-D model is modified to compensate for the oversizing and the steps repeated by sequentially selecting sets of layers to include substantially all of the layers as the intermediate layer.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: November 25, 2003
    Assignee: National University of Singapore
    Inventors: Ying Kit Chew, Yoke San Wong, Ying His Jerry Fuh, Han Tong Loh, Yeh Ching Andrew Nee, Yoo Sang Choo, Li Lu, Kah Bin Lim, Chee Leong Teo, En Tang Kang, Tetsuo Miyazawa
  • Patent number: 6654656
    Abstract: The disclosure relates to rapid informational prototypes of three-dimensional objects and systems having three or more dimensions, wherein the informational prototype includes information beyond outer physical shape, such as stress contours, thermal gradients, internal structures and elements, and elements varying with time. One preferred manner for indicating information is through the use of differently colored regions in the prototype. According to a rapid prototyping method of the present invention, a series of slices through the object or system are defined by an ordinal number, overall contour information for describing shape of the slice in an X-Y plane, slice thickness information for describing thickness of the slice in a Z direction, and slice image information for providing useful information other than the overall contour information, preferably through color images.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: November 25, 2003
    Assignee: The Research Foundation of State University of New York
    Inventors: Thenkurussi Kesavadas, Kirk C. Stalis
  • Patent number: 6647543
    Abstract: A method for manufacturing a pair of complementary masks for use in an electron projection lithographic (EPL) technique uses an algorithm for distributing the design data to a pair of EPL masks. The algorithm allocates a positive sign or negative sign to each of the pattern data, summation of the areas of the pattern data having positive signs while subtracting the areas of the pattern data having negative signs, for obtaining a minimum of the sum. One or more of initial combination of the signs is prepared and the vicinity of the initial combination is calculated therefrom for obtaining an optimum combination.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: November 11, 2003
    Assignee: NEC Corporation
    Inventors: Yasuhisa Yamada, Kenichi Takada
  • Patent number: 6647308
    Abstract: A method of making duplicate keys employs the use of a scanning device for capturing the physical profile of a master key or alternately, formulating the profile as a data construct without the use of a master key. This data construct can be assigned a unique code and stored on a database for later retrieval. Once the key profile has been captured or formulated in a data base memory device, a key may be fabricated without the need for traditional key blanks in accordance with the profile data by, for example, a three-dimensional modeling device such as a fused deposition modeling device or stereolithographic device. Alternately, a milling device or high energy beam in conjunction with a metal slug can construct the duplicate key, or an injection molder using high density molding resin can be used to construct the duplicate key.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: November 11, 2003
    Inventor: Ronald Martin Prejean
  • Patent number: 6630093
    Abstract: A method for making freeform-fabricated core composite articles using freeform-fabricated machine. The articles are capable of being utilized as end products rather than prototype models by creating a core having an interior structure to provide strength to the core and to enhance the strength to weight ratio of the article.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: October 7, 2003
    Inventor: Ronald D. Jones
  • Patent number: 6623687
    Abstract: A three dimensional object having a first one-piece build style lattice including a plurality of substantially uniform build style units and a second one-piece build style lattice integrally formed with and interlaced with the first lattice, the second lattice including a plurality of substantially uniform build style units.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: September 23, 2003
    Assignee: Milwaukee School of Engineering
    Inventors: Vito R. Gervasi, Robert S. Crockett
  • Patent number: 6622062
    Abstract: Rapid prototyping and manufacturing (e.g. stereolithography) methods and apparatus are disclosed that form objects with enhanced accuracy and small feature retention. Techniques for offsetting cross-sectional boundary data to at least partially accommodate for solidification width induced in a medium by a beam of radiation are provided. One technique uses repeated small offsets to yield an effective offset of a desired amount. A second technique uses displacement vectors to determine where and to what extent to offset the boundary segments. The offset amount for each vertex is determined based on a combination of the (1) the vertex angle, and (2) a predefined variable offset criteria which is different for at least two predefined ranges of angles. A third technique converts a single boundary segments into a plurality of offset boundary segments when the single boundary segment can not undergo the full desired offset without violating another offsetting rule.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 16, 2003
    Assignee: 3D Systems, Inc.
    Inventors: Jocelyn M. Earl, Chris R. Manners
  • Patent number: 6600965
    Abstract: An improved stereolithography system for generating a three-dimensional object by creating a cross-sectional pattern of the object to be formed at a selected surface of a fluid medium capable of altering its physical state in response to appropriate synergistic stimulation by impinging radiation, particle bombardment or chemical reaction, information defining the object being specially processed to reduce curl and distortion, and increase resolution, strength, accuracy, speed and economy of reproduction even for rather difficult object shapes, the successive adjacent laminae, representing corresponding successive adjacent cross-sections of the object, being automatically formed and integrated together to provide a step-wise laminar buildup of the desired object, whereby a three-dimensional object is formed and drawn from a substantially planar surface of the fluid medium during the forming process.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: July 29, 2003
    Assignee: 3D Systems, Inc.
    Inventors: Charles W. Hull, Stuart T. Spence, David J. Albert, Dennis R. Smalley, Richard A. Harlow, Phil Stinebaugh, Harry L. Tarnoff, Hop D. Nguyen, Charles W. Lewis, Tom J. Vorgitch, David Z. Remba
  • Patent number: 6578190
    Abstract: A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: June 10, 2003
    Assignee: International Business Machines Corporation
    Inventors: Richard A. Ferguson, Mark A. Lavin, Lars W. Liebmann, Alfred K. Wong
  • Patent number: 6574523
    Abstract: An improved process for forming photocurable three-dimensional objects using an improved curing process is disclosed. The build object is formed by using differential curing of the photocurable media material to form cured solid regions with discrete mechanical properties at selected locations to tailor a part's properties to individual needs.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: June 3, 2003
    Assignee: 3D Systems, Inc.
    Inventors: Stephen D. Hanna, Khalil M. Moussa
  • Patent number: 6571008
    Abstract: A reverse engineering technique allows the creation of 3-D CAD files from a solid model. A solid model of a part to be reverse engineered is created from polymers having an index of refraction matching that of an immersion liquid. Over the immersion liquid is a masking liquid that is substantially opaque. The generally clear polymeric model of the part is moved through the immersion/masking layer interface while images of the cross section of the model are acquired at the interface layer. The images are then used to create digital solid models from a physical model or to compare an existing physical model with its digital model.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: May 27, 2003
    Assignee: Washington State University Research Foundation
    Inventors: Amit Bandyopadhyay, Jonathan C. Christensen
  • Patent number: 6571371
    Abstract: The present invention provides for a method and an apparatus for using a latency time period as a control input parameter. A manufacturing run of semiconductor devices is processed. Metrology data from the processed semiconductor devices is acquired. A latency analysis process is performed using the acquired metrology data. A feedback/feed-forward modification process is performed in response to the latency analysis process.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: May 27, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Elfido Coss, Jr., Michael R. Conboy, Bryce Hendrix
  • Publication number: 20030093173
    Abstract: A stereolithographic method and apparatus for applying packaging material to workpieces such as preformed electronic components, including semiconductor dice, with a high degree of precision, and resulting articles. A machine vision system including at least one camera is operably associated with a computer controlling a stereolithographic system for application of material so that the system may recognize the position and orientation of workpieces, such as semiconductor dice, to which the material is to be applied. The requirement for precise mechanical workpiece alignment is eliminated, and the ability of the system to recognize size, configuration and topography of different workpieces affords greater manufacturing flexibility. The method includes stereolithographic application of material for packaging electronic components, and the electronic components so packaged are also part of the invention.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 15, 2003
    Inventors: Warren M. Farnworth, Mark S. Johnson
  • Patent number: 6549821
    Abstract: A stereolithographic method and apparatus for applying packaging material to workpieces such as preformed electronic components, including semiconductor dice, with a high degree of precision, and resulting articles. A machine vision system including at least one camera is operably associated with a computer controlling a stereolithographic system for application of material so that the system may recognize the position and orientation of workpieces, such as semiconductor dice, to which the material is to be applied. The requirement for precise mechanical workpiece alignment is eliminated, and the ability of the system to recognize size, configuration and topography of different workpieces affords greater manufacturing flexibility. The method includes stereolithographic application of material for packaging electronic components, and the electronic components so packaged are also part of the invention.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: April 15, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Mark S. Johnson
  • Patent number: 6546306
    Abstract: A method comprising determining a polishing profile produced by a polishing tool and manufacturing a process layer with a surface profile prior to polishing operations based upon the determined polishing profile of the polishing tool.
    Type: Grant
    Filed: August 11, 1999
    Date of Patent: April 8, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott Bushman, William Jarrett Campbell
  • Patent number: 6532394
    Abstract: A method of manipulating data in a method for forming a three-dimensional object layer by layer from an ink jettable, solidifiable material by providing data corresponding to a plurality of polygons defining the outer surfaces of a plurality of three-demiensional objects and providing sets of x, y, and z coordinates corresponding to each layer and identifying x and y coordinates with each z coordinate such that directional values and counter values are determined for each y coordinate in a first set of coordinates generated. A second set of y coordinates are generated according to a formula that permits the determined layers to be processed to form a three-dimensional object.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: March 11, 2003
    Assignee: 3D Systems, Inc.
    Inventors: Jocelyn M. Earl, Chris R. Manners, Thomas A. Kerekes, Paul H. Marygold, Jeffrey S. Thayer
  • Patent number: 6526327
    Abstract: A one-step rapid manufacturing process is used to create three dimensional prototyping parts. Material such as metal, ceramics and the like powder, and wire, and the like, is delivered to a laser beam-material interaction region where it is melted and deposited on a substrate. The melted and deposited material is placed on a XYZ workstation. Three dimensional parts are created by moving the XYZ workstation relative to the laser beam while simultaneously feeding powdered alloys, first in the XY and then in the Z plane. Beam shaping focusing optics can be used to tailor the intensity distribution of the laser beam to the requirements of the deposition layers, and can be used to create parts with desired mechanical or thermodynamic properties. Additional beam splitting and recombining optics can be used to allow powder to be fed at a perpendicular angle to the substrate.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: February 25, 2003
    Assignee: University of Central Florida
    Inventors: Aravinda Kar, Srikanth Sankaranarayanan, Franz-Josef Kahlen
  • Patent number: 6523164
    Abstract: Grouping is performed by classifying the data of features having same shapes and sizes in the same layer into the same group. In the grouping, a feature size having lengths of two adjacent sides of a rectangle inscribed by the feature is obtained to attach the size to the feature data, and if feature data has the same kind, layer and size, the same group name is attached to the feature data. When a feature data is selected by an operator to modify it, the other feature data having the same group name are automatically modified in the same manner.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: February 18, 2003
    Assignee: Fujitsu Limited
    Inventors: Shunji Igarashi, Kazunori Koike
  • Patent number: 6513151
    Abstract: A method for new product mask evaluation is provided. Focus exposure matrices are printed at one or more layers (e.g., active gate) on full flow production wafers. The focus exposure matrices are then analyzed to produce data that facilitates detecting printed defects. The full flow production wafers are also subjected to end of line electrical testing to determine bit level errors. Print defects can be correlated with bit level errors to increase confidence in detected defects. The method includes a hierarchy of testing layers, each of which produce data that can be employed in detecting defects in a reticle and/or producing a yield analysis. The method involves scanning a reticle upon which the new product mask is etched and performing a printability simulation to determine what affect, if any, detected reticle defects will have on printing defects on a wafer.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: January 28, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeff Erhardt, Khoi Phan
  • Patent number: 6508971
    Abstract: A variety of support structures and build styles for use in Rapid Prototyping and Manufacturing systems are described wherein particular emphasis is given to Thermal Stereolithography, Fused Deposition Modeling, and Selective Deposition Modeling systems, and wherein a 3D modeling system is presented which uses multijet dispensing and a single material for both object and support formation.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: January 21, 2003
    Assignee: 3D Systems, Inc.
    Inventors: Richard N. Leyden, Jeffrey S. Thayer, Bryan J. L. Bedal, Thomas A. Almquist, Charles W. Hull, Jocelyn M. Earl, Thomas A. Kerekes, Dennis R. Smalley, Christian M. Merot, Richard P. Fedchenko, Michael S. Lockard, Thomas H. Pang, Dinh Ton That
  • Patent number: 6510241
    Abstract: The process comprises a calibration of the apparatus, in which a virtual volume surrounding the object is generated and broken down into voxels, an acquisition of the set of numbered projected two-dimensional images, and a reconstruction of the three-dimensional image from the projected acquired two-dimensional images, and from an iterative algebraic image reconstruction algorithm. A first iteration of the algorithm is performed with a predetermined initial image resolution so as to obtain, at the end of this first iteration, first density values for the voxels of the volume, at least one part of the voxels of the virtual volume is subdivided into several sets, respectively, corresponding to different image resolutions that are multiples or sub-multiples of the initial resolution, and during each subsequent iteration of the algorithm, the algorithm is successively aplied to each of the sets of voxels.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: January 21, 2003
    Assignee: GE Medical Systems SA
    Inventors: Regis Vaillant, Laurant Launay, Rene Romeas, Yves Lucien Marie Trousset
  • Patent number: 6507944
    Abstract: A data processing apparatus comprises a grid pattern area calculation section (24) for calculating the minimum grid and the present area of a circuit element for each layer of circuit patterns given by CAD data (1); an overlap area calculation section (25) for calculating an overlap area of present areas; and a composition/division optimization judgment section (26) for judging by a criterion whether the layers including the overlap area should be processed according to a single common grid or different grids. Each layer can be assigned the grid with the minimum accuracy required for the layer. A grid with more minute accuracy than it requires may not be used. Operation load in making reticle mask data and processing load in actually performing exposure or the like are thereby considerably relieved.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: January 14, 2003
    Assignee: Fujitsu Limited
    Inventors: Kenji Kikuchi, Yoshimasa Ilduka, Tomoyuki Okada, Masahiko Minemura
  • Patent number: 6487712
    Abstract: Disclosed is a method of manufacturing a mask for conductive wirings in a semiconductor device, wherein the conductive wirings are formed on a semiconductor substrate of the semiconductor device, comprising the steps of: (a) calculating data for the entire regions of the semiconductor substrate on which the conductive wirings are formed; (b) reading the size, shape and position of the conductive wiring patterns for the conductive wirings to generate data for conductive wirings, and storing the generated conductive wirings data; (c) extending the conductive wirings data by a predetermined size to generate data for the extended conductive wirings; (d) subtracting the extended conductive wirings data from the data for the entire regions of the semiconductor substrate to calculate a differential data between the extended conductive wirings data and the entire regions data, and to generate data for dummy conductive wiring pattern; (e) adding the conductive wirings data to the dummy conductive wiring pattern data t
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: November 26, 2002
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae Kap Kim
  • Patent number: 6483596
    Abstract: The invention refers to a method for calibrating the control of a radiation device producing electromagnetic radiation or particle radiation in a rapid prototyping system.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: November 19, 2002
    Assignee: EOS GmbH Electro Optical Systems
    Inventors: Jochen Philippi, Andreas Lohner
  • Patent number: 6484306
    Abstract: A method for performing scanned defect inspection of a collection of contiguous areas using a specified false-alarm-rate and capture-rate within an inspection system that has characteristic seek times between inspection locations. The multi-stage method involves setting an increased false-alarm-rate for a first stage of scanning, wherein subsequent stages of scanning inspect only the detected areas of probable defects at lowered values for the false-alarm-rate. For scanning inspection operations wherein the seek time and area uncertainty is favorable, the method can substantially increase inspection throughput.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: November 19, 2002
    Assignee: The Regents of the University of California
    Inventors: Jeffrey Bokor, Seongtae Jeong
  • Publication number: 20020165635
    Abstract: There is provided a method of forming a tool for performing a desired tooling task upon an unfinished part to form a finished part. The method may comprise the step of creating a computer model of the tool corresponding to the unfinished part. Moreover, the method may further comprise using the computer model to stereolithographically create the tool.
    Type: Application
    Filed: May 2, 2001
    Publication date: November 7, 2002
    Inventor: Chris E. Farren
  • Patent number: 6463577
    Abstract: There are independently made data of a device pattern, an identification and scribe pattern including a scribe pattern surrounding the device pattern, identification patterns formed in a scribe region indicated by the scribe pattern and outer periphery of the scribe region, and an outer peripheral pattern formed outside the scribe region except the identification pattern. From the data, data for an exposure system or a mask inspection apparatus are produced. The outer peripheral pattern is divided into a plurality of patterns each is a unit of a exposure region.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventors: Taketoshi Omata, Mitsuo Sakurai, Shuji Osada
  • Patent number: 6453458
    Abstract: The present invention provides a method for segmenting and mapping a two-dimensional conventional circuit pattern to a flat mask for projection onto a three-dimensional surface. The circuit pattern is first segmented into a plurality of circuit segments enclosed in a plurality of base units of an imposed grid system. Subsequently, locations and the boundary conditions for a plurality of mask segments on the mask are determined such that no unneeded overlapping at the boundaries of the projected image on the spherical shaped semiconductor device is possible. The mask, along with a photolithography system having a plurality of mirrors, projects the circuit pattern onto the spherical shaped semiconductor device.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: September 17, 2002
    Assignee: Ball Semiconductor, Inc.
    Inventors: Atsuyuki Fukano, Zhiqiang Feng, Hideki Koide
  • Patent number: 6421820
    Abstract: A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method (see e.g., FIG. 4A) based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured (404). A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements (406). This modification can be performed on some or all of the original shapes (408). For each of the modified shapes, a normalized space and correct number of assist features can be computed (410). The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape (412). This modified layout can then be used in producing a photomask, which can in turn be used to produce a semiconductor device.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: July 16, 2002
    Assignees: Infineon Technologies AG, Internation Business Machines Corporation
    Inventors: Scott M. Mansfield, Lars W. Liebmann, Shahid Butt, Henning Haffner
  • Patent number: 6415431
    Abstract: A method and apparatus are provided for repairing clear defects in photomasks such as attenuated photomasks having a patterned MoSi film on a glass substrate. The method and apparatus use an energy source in the form of an energy beam to undercut the sidewalls of the clear defect forming a clear defect having angled sidewalls. A repair material is then deposited in the angled opening to repair the clear defect. In a preferred embodiment, two repair steps are used with the first repair step using a first repair material to deposit a first repair material on the angled sidewalls of the clear defect and a second step using a second repair material to contact the first repair material and to fill the remainder of the clear defect opening. An apparatus for repairing clear defects and photomasks repaired by the method and apparatus of the invention is also provided.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: July 2, 2002
    Assignee: International Business Machines Corporation
    Inventor: Timothy E. Neary
  • Patent number: 6406658
    Abstract: A rapid prototyping and manufacturing (e.g. stereolithography) method and apparatus for making three-dimensional objects on a layer by layer basis by selectively exposing layers of material to prescribed stimulation, using a beam having a first smaller diameter and a beam having a second larger diameter, to form laminae of the object. The power of the smaller beam is typically lower than the power of the larger beam. Object formation is controlled by data representing portions of the layers to be exposed with the larger beam (large spot portions) and those portions to be exposed with the smaller beam (small spot portions). In a preferred embodiment, portions exposed with the larger beam are formed first, for a given layer. Portions are exposed with the small beam next. Thereafter the entire perimeter of the laminae is traced using the small beam.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: June 18, 2002
    Assignee: 3D Systems, Inc.
    Inventors: Chris R. Manners, Michelle D. Guertin, Hop D. Nguyen, Jouni P. Partanen, Nansheng Tang, Michael A. Everett
  • Patent number: 6399010
    Abstract: A rapid prototyping and manufacturing (e.g. stereolithography) method and apparatus for making three-dimensional objects on a layer-by-layer basis by selectively exposing layers of material to prescribed synergistic stimulation including forming portions of a lamina using a first exposure, allowing a time delay, and then applying a second exposure. The time delay is sufficient to allow shrinkage of the material to occur that results from the first exposure. It is preferred that the solidified portion resulting from the first exposure does not adhere to the previously formed lamina. It is also preferred that the portion solidified by this first exposure does not adhere to any boundary region that may have been exposed and adhered to the previously formed lamina. The time delay associated with a given cross-sectional region may be occupied by exposing other cross-sectional regions. The delay may occur between two exposures of overlaying hatch or fill vectors.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: June 4, 2002
    Assignee: 3D Systems, Inc.
    Inventors: Michelle D. Guertin, Charles W. Hull, Hop D. Nguyen
  • Patent number: 6401001
    Abstract: A solid freeform fabrication process and apparatus for making a three-dimensional object.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: June 4, 2002
    Assignee: Nanotek Instruments, Inc.
    Inventors: Bor Z. Jang, Junsheng Yang, Junhai Liu, Lijun Pan
  • Patent number: 6401002
    Abstract: A solid freeform fabrication process and apparatus for making a three-dimensional object. The process comprises the steps of (1) operating a multiple-channel material deposition sub-system for dispensing droplets of selected liquid compositions and solid powders at predetermined proportions; (2) providing an object platform in close working vicinity to the deposition sub-system to receive the deposition materials therefrom; and (3) during the material deposition process, moving the deposition sub-system and the platform relative to each other in an X-Y plane defined by first and second directions and in a Z direction orthogonal to the X-Y plane so that the materials are deposited to form a first layer of the object. These steps are repeated to deposit multiple layers for forming a three-dimensional shape.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: June 4, 2002
    Assignee: Nanotek Instruments, Inc.
    Inventors: Justin Jang, Wen C. Huang, Weiltong Zhong
  • Publication number: 20020062206
    Abstract: The present invention provides a method and apparatus for simulating an aerial image projected from an optical system, wherein the optical system includes a pupil and a mask. In general, the method comprises the steps of obtaining parameters for the optical system, calculating a kernel based on an orthogonal pupil projection of the parameters of the optical system onto a basis set, obtaining parameters of the mask, calculating a vector based on an orthogonal mask projection of the parameters of the mask onto a basis set, calculating a field intensity distribution using the kernel and the vector, and obtaining aerial image data from the field intensity distribution.
    Type: Application
    Filed: September 10, 2001
    Publication date: May 23, 2002
    Inventor: Armin Liebchen
  • Patent number: 6393604
    Abstract: Plural patterns of cell projections made in an aperture are stored in a register. Cells in designed data are compared with the cell projections stored in the register by an interlayer operation, to judge whether or not a cell which coincides with any one of the cells in the designed data is present among the patterns of the cell projections stored in the register. In the case that the judgement that the coinciding cell is present is given, the coinciding cell projection is e acted and outputted as data for direct-writing. In the case that the judgement that no coinciding cell is present is given, if a cell whose reference frequency is over a given value is present, this cell is extracted and registered as a new cell projection.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: May 21, 2002
    Assignee: NEC Corporation
    Inventors: Yasuhisa Yamada, Yuzo Ogawa
  • Patent number: 6374397
    Abstract: A lot determination apparatus and method and a recording medium having the lot determination method recorded thereon, wherein there can be realized a reduction in the number of times wafers are re-subjected to photolithography and prevention of elimination of a chip lot in a subsequent step, by determination of whether or not a chip is conforming through comprehensive determination of results of a plurality of inspections such as an overlay inspection, an etched pattern inspection, and a resist pattern inspection. A determination is made as to whether or not a lot is defective by comprehensive determination of results of a plurality of inspection processes, thereby preventing elimination of the lot as being nonconforming. As a result, specifications for inspections can be relaxed, which in turn enables a reduction in a reprocessing ratio.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: April 16, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuki Miyamoto, Takeo Ishibashi
  • Publication number: 20020042664
    Abstract: For a wafer earlier than a n'th wafer (n>2) in a lot, a method (and an apparatus) of this invention detects positions of all shot areas, separates a nonlinear component and linear component of each of position deviation amounts, evaluates nonlinear distortion of the wafer based on the position deviation amounts and an evaluation function, and calculates nonlinear components of the position deviation amounts of all shot areas according to a complement function determined based on the evaluation results. On the other hand, for the n'th or later wafer, the method (and the apparatus) calculates position coordinates, of all shot areas, having linear components of position deviation amounts thereof corrected by using EGA, and detects positions of the shot areas based on the position coordinates having linear components thereof corrected and the nonlinear components calculated in the above.
    Type: Application
    Filed: May 31, 2001
    Publication date: April 11, 2002
    Applicant: Nikon Corporation
    Inventor: Takahisa Kikuchi
  • Patent number: 6366825
    Abstract: A method and apparatus for making high resolution objects by stereolithography utilizing low resolution materials which are limited by their inability to form unsupported structures of desired thinness and/or their inability to form coatings of desired thinness. Data manipulation techniques, based on layer comparisons, are used to control exposure in order to delay solidification of the material on at least portions of at least some cross-sections until higher layers of material are deposited so as to allow down-facing features of the object to be located at a depth in the building material which is equal to or exceeds a minimum cure depth that can effectively be used for solidifying these features. Similar data manipulations are used to ensure minimum reliable coating thicknesses exist, above previously solidified material, before attempting solidification of a next layer. In addition, horizontal comparison techniques are used to provide enhanced cross-sectional data for use in forming the object.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: April 2, 2002
    Assignee: 3D Systems, Inc.
    Inventors: Dennis R. Smalley, Thomas J. Vorgitch, Chris R. Manners, Jocelyn M. Earl, Bryan J. L. Bedal, Charles W. Hull, Stacie L. VanDorin
  • Patent number: 6336204
    Abstract: A method and apparatus for handling deadlocks in a multichamber semiconductor wafer processing system known as a cluster tool. A plurality of software routines execute upon a sequencer of a cluster tool to perform deadlock avoidance, deadlock detection and deadlock resolution towards achieving optimal wafer throughput for a cluster tool.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: January 1, 2002
    Assignee: Applied Materials, Inc.
    Inventor: Dusan Jevtic
  • Patent number: 6334209
    Abstract: Disclosed is an exposure mask inspecting method for use in manufacturing semiconductor devices. This inspecting method calculate gradients of a correlation curve of a variation in critical dimension of an exposure mask and a variation in critical dimension of a resist, extracts portions having large slopes of the correlation curve, and slopes the portions having large slopes of the correlation curve as to-be-measured portions at the time of verifying the specifications of the surface critical dimension of the exposure mask.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: December 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hashimoto, Shigeki Nojima
  • Patent number: 6325961
    Abstract: A rapid prototyping and manufacturing (e.g. stereolithography) method and apparatus for producing three-dimensional objects by selectively subjecting a liquid or other fluid-like material to a beam of prescribed stimulation. In a preferred embodiment a source of prescribed stimulation is controlled to reduce or inhibit the production of the prescribed stimulation during at least some periods when the prescribed stimulation is not needed to expose the material. In another preferred embodiment, the source of stimulation is controlled to vary the quantity of prescribed stimulation that is produced and allowed to reach the material. In an additional preferred embodiment control of laser output occurs based on a combination of supplying a regulated amount of voltage to an AOM in conjunction with temporary sensing of laser power and a known desired power to attain.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: December 4, 2001
    Assignee: 3D Systems, Inc.
    Inventors: Ross D. Beers, Jouni P. Partanen, Nansheng Tang