Having Judging Means (e.g., Accept/reject) Patents (Class 702/82)
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Patent number: 7974801Abstract: By performing a two-step approach for predicting a quality distribution during the fabrication of semiconductor devices, enhanced flexibility and efficiency may be accomplished. The two-step approach first models electrical characteristics on the basis of measurement data, such as inline measurement data, and, in a second step, an appropriate distribution for the electrical characteristics may be established, thereby obtaining modeled wafer sort data which may then be used for predicting a quality distribution of the semiconductor devices under consideration.Type: GrantFiled: February 5, 2009Date of Patent: July 5, 2011Assignee: Advanced Micro Devices, Inc.Inventor: Richard Good
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Patent number: 7970565Abstract: A measurement apparatus that measures a signal under measurement, including a strobe timing generator that sequentially generates strobes arranged at substantially even time intervals, a level comparing section that detects a signal level of the signal under measurement at a timing of each sequentially provided strobe, a capture memory that stores therein a data sequence of the signal levels sequentially detected by the level comparing section, a frequency domain converting section that converts the data sequence into a spectrum in the frequency domain, and a jitter calculating section that calculates jitter of the signal under measurement based on a value obtained by integrating levels of frequency components in a predetermined frequency range of the spectrum.Type: GrantFiled: August 25, 2008Date of Patent: June 28, 2011Assignee: Advantest CorporationInventors: Harry Hou, Takahiro Yamaguchi
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Patent number: 7966152Abstract: A method for automatically monitoring the performance of equipment includes compiling current operating conditions associated with current conditions (PMc). A historical database including a plurality of stored operating conditions and associated stored performance measure (PM*) is searched, each stored operating condition including at least one stored sensor reading, wherein at least one similar operating condition is identified in the search using distances between the current operating conditions and the stored operating conditions. The performance measure (PM*) associated with the similar operating condition is fit to generate a regression model. The regression model is applied to the current operating condition to generate an estimate for the performance measure for the current operating condition (PMe). A difference between PMc and PMe is computed.Type: GrantFiled: April 23, 2008Date of Patent: June 21, 2011Assignee: Honeywell International Inc.Inventors: Petr Stluka, Jiri Rojicek
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Patent number: 7962302Abstract: Techniques for estimating a quality of one or more wafers are presented. One or more first wafers comprising one or more first dies are tested. A probability of wafer failure is determined in accordance with one or more first test measurements of the one or more first dies. A pass status and/or a fail status of one or more second wafers is inferred by testing a select one or more second dies of the one or more second wafers and evaluating one or more second test measurements of the select one or more second dies in accordance with the determined probability of wafer failure.Type: GrantFiled: December 8, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Robert Jeffrey Baseman, Susan G. Conti, William A. Muth, Michal Rosen-Zvi, Frederick A. Scholl
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Patent number: 7953503Abstract: A method for operating a process plant, in which a number of alarm notifications for indicating non-compliant operating events of the process plant are generated at process level. Alarm notifications which can be generated during the operation of the process plant are defined. At least a number of the generatable alarm notifications are assigned, in each case at least a first value or a second value as a dependency value. A current process state of the process plant is determined and depending on the determined process state, those alarm notifications to which the first value was assigned as a dependency value are not indicated.Type: GrantFiled: January 22, 2008Date of Patent: May 31, 2011Assignee: Siemens AktiengesellschaftInventor: Oliver Thurau
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Publication number: 20110119010Abstract: A method of determining characteristics of a DUT, in which test results indicating at least a pass/fail state of the DUT are used on a matrix in which plots defined by a combination of a first test parameter and a second test parameter for testing the DUT are arranged two-dimensionally, includes the steps of: (a) specifying at least one plot pair constituted by adjacent plots but indicating different test results on the matrix; (b) specifying test results of a plot pair constituted by adjacent plots and located next to both plots of the plot pair specified in the step (a); (c) selecting a plot pair constituted by adjacent plots but indicating different test results in a region including the plot pair specified in the step (a) and the step (b); and (d) specifying test results of a plot pair constituted by adjacent plots and located next to both plots of the plot pair selected in the step (c).Type: ApplicationFiled: January 15, 2009Publication date: May 19, 2011Applicant: ADVANTEST CORPORATIONInventor: Junichi Yuki
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Patent number: 7941233Abstract: System and method for controlling at least one device such as for example an operator for a door, a gate, a window, blinds, shutters, a curtain, an awning or a light source including a controllable unit associated with the at least one device and a plurality of nodes for transmitting control signals to the at least one controllable unit. The at least one of the plurality of nodes for transmitting control signals is configured for transmitting a signal imposing a limit for at least one parameter for the device. Further, the controllable unit is configured for registering the limit and establishing a resulting limit for the parameter.Type: GrantFiled: July 4, 2005Date of Patent: May 10, 2011Assignee: VKR Holding A/SInventors: Martin Sandal Nielsen, Bjarne Ravndal Andreasen
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Patent number: 7937234Abstract: Classification of spatial patterns on wafer maps is generally described. In one example, a method includes applying K-means type clustering to wafer maps comprising one or more spatial patterns to group one or more clusters comprising wafer maps having similar spatial patterns and producing a dendrogram using a clustering process to display the one or more clusters.Type: GrantFiled: August 29, 2008Date of Patent: May 3, 2011Assignee: Intel CorporationInventors: Eric R. St. Pierre, Eugene Tuv, Alexander Borisov
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Publication number: 20110093226Abstract: A fault detection and classification (FDC) method for wafer acceptance test (WAT) parameters includes the following steps. A plurality of fault detection and classification parameters is collected. A plurality of wafer acceptance test parameters that are corresponded by the fault detection and classification parameters is collected. The fault detection and classification parameters are grouped. A contingency table of the wafer acceptance test parameters corresponding to the fault detection and classification parameters is built. A probability model of the contingency table is built. Finally, a safety range of the probability model is determined.Type: ApplicationFiled: December 27, 2010Publication date: April 21, 2011Applicant: INOTERA MEMORIES, INC.Inventors: YIJ CHIEH-CHU, CHUN CHI CHEN, YUN-ZONG TIAN, CHENG-HAO CHEN
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Patent number: 7930053Abstract: A method of automating validation in a manufacturing facility is disclosed. The method comprises defining requirements, selecting and integrating automated devices for manufacturing. A hub-box with communication links is used to integrate the automated devices. The hub-box controls and facilitates communication between automated devices. The hub-box further collects and analyzes processing data for validation of the process. By interconnecting the automated devices to a hub-box, processing data may be collected substantially real-time and accessed remotely, facilitating continuous process validation.Type: GrantFiled: December 23, 2003Date of Patent: April 19, 2011Assignee: Beacons Pharmaceuticals Pte LtdInventors: Wee Song Steve Loy, Wei Chak Joseph Lam
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Patent number: 7925461Abstract: A quality control method using a plurality of analyzers and a control device connected to the analyzers via a network, the method comprising: (a) measuring quality control samples by the analyzers; (b) collecting a plurality of quality control data obtained by measuring the quality control samples; (c) implementing a quality control by the control device based on the collected quality control data; (d) obtaining uncertainty of measurement of analyzer based on uncertainty of analyzer calibration and the quality control data; (e) outputting a result of the quality control; and (f) outputting the uncertainty of measurement is disclosed. A quality control system and an analyzer are also disclosed.Type: GrantFiled: September 21, 2007Date of Patent: April 12, 2011Assignee: Sysmex CorporationInventors: Tadayuki Yamaguchi, Atsushi Shirakami, Etsuro Shinkai, Yasuhiro Ochi
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Patent number: 7916893Abstract: An image processing apparatus includes an image capturing section, a marker-image defecting section, a judging section and an output section. The image capturing section captures at least a part of a target image, which includes a plurality of marker images and a recognition target range defined by the plurality of marker images, to acquire a captured image. The marker-image detecting section detects the marker images from the captured image. The judging section judges based on a detection result, whether or not the recognition target range is included in the captured image. When the judging section judges that the recognition target range is not included in the captured image, the output section outputs guidance for capturing the recognition target range.Type: GrantFiled: September 11, 2006Date of Patent: March 29, 2011Assignee: Fuji Xerox Co., Ltd.Inventors: Katsuyuki Kouno, Hirofumi Komatsubara, Fujio Ihara, Kenji Ebitani
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SEMICONDUCTOR OUTLIER IDENTIFICATION USING SERIALLY-COMBINED DATA TRANSFORM PROCESSING METHODOLOGIES
Publication number: 20110071782Abstract: A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain electrical test data including at least one test parameter, applying at least a first data transform processing methodology to the electrical test data to generate processed test data, and applying a second data transform processing methodology that is different from the first data transform processing methodology to process the processed test data. The second data transform processing methodology applies an outlier test limit to identify non-outlier devices that comprise semiconductor devices from the semiconductor devices that conform to the outlier test limit and outlier devices that do not conform to the outlier test limit. The semiconductor devices are dispositioned using the outlier identification results. At least one of the data transform processing methodologies can include statistics.Type: ApplicationFiled: September 24, 2009Publication date: March 24, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: AMIT V. NAHAR, JOHN M. CARULLI, JR., KENNETH M. BUTLER, THOMAS J. ANDERSON, SURESH SUBRAMANIAM -
Patent number: 7912669Abstract: A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary.Type: GrantFiled: March 27, 2007Date of Patent: March 22, 2011Assignee: Honeywell International Inc.Inventor: Sumit K. Basu
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Patent number: 7908128Abstract: Modeling a tire model used for a computer simulation of a pneumatic tire with a toroidal main body and a tread pattern by setting a three-dimensional main body model by dividing the main body by an integer M not less than 2 equally in a circumferential direction of the tire using a finite number of elements, setting a three-dimensional pattern model by dividing the tread pattern by an integer M greater than N equally in the circumferential direction of the tire using a finite number of elements, coupling the pattern model with the main body model while aligning each tire rotation axis to make a three-dimensional tire model, and correcting by moving nodal points existing on a radially outer surface of the pattern model such that a thickness of the pattern model measured from a radially outer surface of the main body model in a normal direction becomes constant.Type: GrantFiled: November 6, 2007Date of Patent: March 15, 2011Assignee: Sumitomo Rubber Industries, Ltd.Inventor: Masaki Shiraishi
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Patent number: 7908026Abstract: A defect testing apparatus for testing defects of optical film sheet-shaped product of an optical displaying apparatus, which includes a defect detecting means for detecting defects of a monolayer body and/or a laminate body constituting the sheet-shaped product in a state in which a protective layer on a surface of the sheet-shaped product is not disposed and defect information preparing means for preparing defect information which is information related to the defects detected by the defect detecting means, and the defect information is used for producing the sheet-shaped product provided in a roll form or in separate sheets.Type: GrantFiled: October 10, 2007Date of Patent: March 15, 2011Assignee: NITTO DENKO CORPORATIONInventor: Hiromichi Ohashi
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Patent number: 7904845Abstract: Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.Type: GrantFiled: December 5, 2007Date of Patent: March 8, 2011Assignee: KLA-Tencor Corp.Inventors: Christophe Fouquet, Gordon Abbott, Ellis Chang, Zain K. Saidin
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Patent number: 7895008Abstract: A method of performing measurement sampling in a production process includes passing a lot through a manufacturing process, employing a set of combinational logistics to determine if sampling is indicated and, if sampling is indicated, establishing a sampling decision. The method further requires querying a set of lot sampling rules to evaluate the sampling decision, evaluating a statistical quality of the process if no lot sampling rules exist, and automatically determining whether the lot passing through the production process requires sampling based on the combinational logistics, statistical quality and lot sampling rules.Type: GrantFiled: March 17, 2008Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Gary W. Behm, Yue Li, Malek Ben Salem, Keith Tabakman
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Publication number: 20110040510Abstract: A film thickness measurement apparatus may include a spectrum acquisition unit that irradiates a light onto a film and acquires a spectrum of a reflection light or a transmission light, a power spectrum calculating unit that calculates a power spectrum, a film thickness calculating unit that detects a peak position of the power spectrum and calculates a thickness of the film, a measurement quality calculating unit that calculates a measurement quality of the thickness, a measurement quality determining unit that determines whether the thickness is valid or invalid, and a film thickness output unit that outputs the thickness if the measurement quality determining unit determines that the thickness is valid.Type: ApplicationFiled: August 16, 2010Publication date: February 17, 2011Applicant: YOKOGAWA ELECTRIC CORPORATIONInventor: Kazufumi NISHIDA
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Patent number: 7885782Abstract: A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad ICs on the wafer and the fuse IDs of the ICs on the wafer. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices. At the opens/shorts test at the end of assembly, the fuse ID of each IC in each device is automatically retrieved so the wafer map of the IC device may be accessed and evaluated to identify any IC devices containing bad ICs that have accidentally been assembled into IC devices. Any “bad” IC devices are discarded while remaining IC devices continue on to back-end testing.Type: GrantFiled: October 17, 2006Date of Patent: February 8, 2011Assignee: Micron Technology, Inc.Inventor: Raymond J. Beffa
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Publication number: 20110015887Abstract: A method is proposed for manufacturing and testing of complex products, in particular motor vehicles in series production, wherein all the data for the individual manufacturing stations in the manufacturing line is stored in a central computer. In this case, different models are manufactured on the manufacturing line, such that the correspondingly configured data is provided at each manufacturing and test station for this model, after identification of the model. A technical test is carried out in conjunction with the manufacturing installation by monitoring the vehicle functions or else the equipment for their function. An attributive test is carried out by the worker at the manufacturing stations, with all the recorded test data being supplied to the central computer for central evaluation, and with the data being stored on the basis of individual categories in the central computer, such that it is possible to evaluate the manufacturing process with respect to the individual manufacturing steps.Type: ApplicationFiled: July 9, 2010Publication date: January 20, 2011Applicant: DR. ING. H.C. F. PORSCHE AKTIENGESELLSCHAFTInventors: HERBERT HORST, HANS-CHRISTIAN SCHNABEL
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Patent number: 7869966Abstract: The present invention relates to a tool for analyzing by priority a defect having a high possibility of causing an electrical failure when inspecting a particle and a pattern defect in a piece of work which constitutes an electronic device such as a semiconductor integrated circuit, and relates to a system therefor. On the basis of the result of comparison between defect information which is the result of inspection by an inspection tool and layout data stored in an auxiliary storage device, or on the basis of the result of reinspection by comparison between a defect and a wiring pattern as a background by an inspection processing operation unit, an object to be reviewed is selected using review conditions stored in the auxiliary storage device.Type: GrantFiled: September 9, 2004Date of Patent: January 11, 2011Assignee: Hitachi, Ltd.Inventors: Takafumi Okabe, Shunji Maeda, Kaoru Sakai
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Patent number: 7856330Abstract: A measuring apparatus measures a signal-under-test having a signal level that changes at predetermined bit time intervals. A strobe timing generator sequentially generates strobes at even time intervals. A level comparator detects a level of the signal at a timing at which each strobe is sequentially provided. A capture memory stores a signal level output from the comparator. A signal processor calculates a measurement of the signal based on a data series including data taken at even time intervals, each larger than a bit time interval of the signal.Type: GrantFiled: January 15, 2007Date of Patent: December 21, 2010Assignee: Advantest CorporationInventors: Harry Hou, Takahiro Yamaguchi
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Publication number: 20100289902Abstract: A testing system for a video chip to be tested stores a video file in advance. At first, the testing system using a sample video chip to play the video file and outputs first video data. Then a video chip to be tested is installed into the testing system to play the video file and outputs second video data. The first video data and the second video data are compared to determine whether the video chip to be tested is acceptable or not and a control signal is outputted according to the comparison to control a robotic arm to place the video chip to be tested at a determined place.Type: ApplicationFiled: June 10, 2009Publication date: November 18, 2010Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Hou-Hsien Lee, Chang-Jung Lee, Chih-Ping Lo
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Patent number: 7822572Abstract: A method for calibration of a digital celestial sensor is disclosed. First, an integrated mathematic model for imaging of a celestial sensor is established according to external and internal parameters of the calibration system of the celestial sensor. Second, by rotating two axes of a rotator by different angles, calibration points data are acquired and sent to a processing computer through an interface circuit. Finally, a two-step calibration program is implemented to calculate the calibration parameters by substituting calibration points' data to the integrated mathematic model. An application device of the calibration method is also provided. The device may include a celestial simulator to provide simulated sunlight or starlight, a two-axis rotator to acquire different calibration points' data, and a processing computer to record the calibration points' data and calculate the calibration parameters.Type: GrantFiled: February 25, 2008Date of Patent: October 26, 2010Assignee: Beihang UniversityInventors: Guangjun Zhang, Xinguo Wei, Qiaoyun Fan, Jie Jiang
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Patent number: 7822566Abstract: Where substrates with components are produced through a series of production processes and inspected after each of these production processes, a method is provided for setting an optimum reference value for making judgments in these inspections such that the frequency of occurrence of disagreement between inspection results after an intermediate process and after the final results will come to within a specified range. After an initial value is assigned for a reference value, this value is sequentially varied while repeating specified processes of saving measured and judgment data on inspected portions of components in a memory and setting a reference value by using the data saved in the memory until a specified condition becomes satisfied.Type: GrantFiled: June 28, 2007Date of Patent: October 26, 2010Assignee: OMRON CorporationInventor: Kiyoshi Murakami
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Publication number: 20100268502Abstract: A test case for the application under test is determined for the quality assurance application where results for a test case can be received from a user. An interface is displayed to allow the user to enter a pass or fail indication for a manual test that has been performed for the test case. If a pass indication is received for the test case, the test case is marked as passed. Also, in response to receiving the pass indication for the test case, a plurality of steps for the test case are automatically marked as passed. If a fail indication is received for the test case, a request for the user to identify a step that failed the manual test is output. When the response indicating which step failed is received, that step is marked as failed.Type: ApplicationFiled: April 15, 2009Publication date: October 21, 2010Applicant: Oracle International CorporationInventors: Yedalla Jayasudha, Kalyani Subramanyan
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Patent number: 7813893Abstract: A method that involves matching the trend of process outcome with the trend of process variables to identify the variables that have an impact on the process outcome is disclosed. The method for process trend matching comprises processing of raw data of process outcome and of process variables using an outlier filtering method, smoothing these data using common smoothing algorithm like Kernel, dividing smoothed raw data equally into time intervals, computing the gradients of the points at both ends of the time intervals, and translating the gradients into a scale based on the magnitude of the gradients. The following steps comprise comparing the process outcome and each process variable independently for same time frame, and assigning a score for both outcome and variable. The sum of the scores is then computed which is used to determine the quality of fit. A real-time monitoring system is then set up to monitor these variables for any drifts.Type: GrantFiled: January 18, 2007Date of Patent: October 12, 2010Assignee: TECH Semiconductor Singapore Pte LtdInventors: Kien Hoong Fong, Wei Fu, Jun Shi
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Publication number: 20100250172Abstract: System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.Type: ApplicationFiled: March 26, 2009Publication date: September 30, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Andy Tsen, Sunny Wu, Wang Jo Fei, Jong-I Mou
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Publication number: 20100250173Abstract: The present invention is to provide a method for easily evaluating whether or not a relative positional shift generated between both surfaces of a bi-aspherical type lens is within an allowance during the manufacturing process of the bi-aspherical type lens. According to the evaluation method of the progressive-addition lens of the present invention, first, powers of the progressive-addition lens at a plurality of are measured to obtain an actually measured power distribution. Next, a comparison power distribution created based on the actually measured power distribution and a defective power distribution prepared in advance are compared with each other to perform similarity search between the both.Type: ApplicationFiled: August 29, 2008Publication date: September 30, 2010Applicant: Hoya CorporationInventor: Kazuma Kozu
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Publication number: 20100235125Abstract: An electric device includes a plurality of circuits that operate in synchronization with a clock signal, a plurality of flip-flops each of which acquires a data value of a signal from a corresponding one of the plurality of circuits in synchronization with the clock signal and stores the acquired data value therein until receiving a next clock signal, where each flip-flop enters into a clock-disabled state, when receiving a signal at a disable terminal thereof, in which the acquired data value continues to be stored in the flip-flop, a timing controller that outputs a hold signal to the disable terminal of each flip-flop at a timing at which a corresponding circuit is desired to be diagnosed, and a plurality of diagnosis lines that are respectively provided in correspondence with the plurality of flip-flops, each diagnosis line outputting as diagnosis data a data value stored in a corresponding flip-flop.Type: ApplicationFiled: February 24, 2010Publication date: September 16, 2010Applicant: ADVANTEST CORPORATIONInventor: Masahiko HATA
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Patent number: 7793412Abstract: A component-embedded board fabrication method includes detecting, before the board is covered with a first insulating layer, the actual position of a first electronic component formed on a surface of the board, calculating a displacement between the design position of the first electronic component on the surface of the board and holding the displacement as first displacement data, and correcting, based on the first displacement data, design data to be used for processing the board after the board is covered with the first insulating layer.Type: GrantFiled: July 3, 2003Date of Patent: September 14, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masatoshi Akagawa, Kazunari Sekigawa, Shinichi Wakabayashi
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Publication number: 20100228511Abstract: The present invention relates to a method for minimizing the effects of metamerism between a set of color standards (e.g., nitrocellulose lacquers) and inkjet printed color merchandise (e.g., paint chips) under a plurality of illuminants, including a balanced illuminant that emulates lighting conditions between cool (6500 K) and warm (2856 K) color temperatures. For each color standard, one selects an ink combination that best produces color merchandise having a minimal degree of metamerism. Innovatively, a combination of instrumental and visual tests is used to evaluate color difference for a set of color standards-color merchandise pairs under a plurality of illuminants. If a color standard-color merchandise pair fails either test then the ink combination may be adjusted.Type: ApplicationFiled: March 3, 2009Publication date: September 9, 2010Applicant: Columbia Insurance CompanyInventors: Bobby Chin, Carl Minchew, Patrick Tak Fu Chong, Anthony Joseph Calabria
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Patent number: 7792651Abstract: A method of computing gear modifications from a gear inspection chart is provided. The method includes extracting a gear profile from the gear inspection chart. The method also includes quantifying the gear profile. The method also includes determining a gear modification based on a quantified gear profile. The method also includes qualifying a gear based on the gear modification.Type: GrantFiled: April 26, 2007Date of Patent: September 7, 2010Assignee: General Electric CompanyInventors: Sheri George, Sivaramanivas Ramaswamy, Kongasary Krishnan Kutty, Abhinav Ramnath Bajpai
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Patent number: 7787164Abstract: A method to evaluate a holographic data storage medium, wherein the holographic data storage medium is evaluated by a manufacturer. In certain embodiments, the holographic data storage medium is evaluated by a customer prior to encoding customer information into the storage medium. In certain embodiments, the holographic data storage medium is evaluated by a customer after encoding customer information therein.Type: GrantFiled: February 26, 2007Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Allen Keith Bates, Nils Haustein, Craig Anthony Klein, Daniel James Winarski
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Patent number: 7783452Abstract: A signal measuring apparatus that measures a first input signal and a second input signal is provided, including a first measuring section that measures the first input signal at a plurality of strobe timings arranged in each cycle of a measurement cycle, a second measuring section that measures the second input signal at a plurality of strobe timings arranged in each cycle of a measurement cycle, a phase difference calculating section that calculates phase differences between the first input signal and the second input signal in each measurement cycle based on measurement results from the first measuring section and the second measuring section, and a distribution generating section that generates distribution information of the phase differences calculated in each measurement cycle by the phase difference calculating section.Type: GrantFiled: November 16, 2007Date of Patent: August 24, 2010Assignee: Advantest CorporationInventors: Tadahiko Baba, Masatoshi Ohashi
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Publication number: 20100208780Abstract: There is provided a transfer circuit including a transmitter that outputs a transmission signal and a receiver that receives the transmission signal. Here, the receiver supplies to the transmitter a feedback signal for controlling a common level of the transmission signal output from the transmitter, and the transmitter controls the common level of the transmission signal output therefrom, in accordance with the feedback signal received from the receiver. The receiver includes a receiving section that operates in accordance with the transmission signal, a reference level generating section that generates a reference level representing an expected level for the common level of the transmission signal input into the receiving section, and a comparing section that compares the common level of the transmission signal input into the receiving section against the reference level and generates the feedback signal in accordance with a result of the comparison.Type: ApplicationFiled: February 4, 2010Publication date: August 19, 2010Applicant: ADVANTEST CORPORATIONInventors: Daisuke WATANABE, Toshiyuki OKAYASU
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Patent number: 7777515Abstract: Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.Type: GrantFiled: December 30, 2008Date of Patent: August 17, 2010Assignee: OptimalTest Ltd.Inventor: Gil Balog
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Publication number: 20100204940Abstract: According to an embodiment of the present invention is to provide methods to evaluate the impact of scrapped wafers on the remaining wafers in a lot by using scrap codes and statistical models. An embodiment of the present invention provides a method to obtain a baseline lot population by using cluster analysis model and functional limited yields. The functional limited yields may be for example chain limited yield, dc limited yield, or ac abist limited yield. By utilizing statistical modeling it is possible to determine which failures have an impact on the lot yield and require rework for the lot. In addition by monitoring the impact of failures, it is possible to determine if corrective actions need to be taken for lots that passed through a process prior to correction of the fault.Type: ApplicationFiled: February 9, 2009Publication date: August 12, 2010Applicant: International Business Machines CorporationInventors: Gasner J. Barthold, Hari V. Mallela, Yunsheng Song
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Publication number: 20100198541Abstract: A management apparatus includes: a managing unit that manages production information corresponding to each of a plurality of information processing devices; a specifying unit that specifies, based on a defect notice for at least one component and the production information on the managed information processing devices, at least one of the information processing devices using the component; a state judging unit that judges whether each information processing device is in an operable state where a processing function of each information processing device is operable in an environment in which the processing function of each information proceeding device is provided; and a operation restricting unit that performs operation restriction for the processing function of each information proceeding device according to the defect notice if the state judging unit judges that each information processing device is in the operable state.Type: ApplicationFiled: August 7, 2009Publication date: August 5, 2010Applicant: Fuji Xerox Co., Ltd.Inventors: Noriyuki MATSUDA, Masayasu TAKANO, Akiko SETA, Koji ADACHI, Kaoru YASUKAWA, Tetsuichi SATONAGA
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Patent number: 7769561Abstract: A method for monitoring machine conditions is based on machine learning through the use of a statistical model. A correlation coefficient is calculated using weights assigned to each sample that indicate the likelihood that that sample is an outlier. The resulting correlation coefficient is more robust against outliers. The calculation of the weight is based on the Mahalanobis distance from the sample to the sample mean. Additionally, hierarchical clustering is applied to intuitively reveal group information among sensors. By specifying a similarity threshold, the user can easily obtain desired clustering results.Type: GrantFiled: November 27, 2006Date of Patent: August 3, 2010Assignee: Siemens CorporationInventors: Chao Yuan, Christian Balderer, Tzu-Kuo Huang, Claus Neubauer
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Patent number: 7761178Abstract: Provided is a method of designing an optical metrology system for measuring structures on a workpiece wherein the optical metrology system is configured to meet a plurality of design goals. The design of the optical metrology system is optimized by using collected design goal data in comparison to the set plurality of design goals. In one embodiment, the optical metrology system is used for stand alone metrology systems. In another embodiment, the optical metrology system is integrated with a fabrication cluster in semiconductor manufacturing. At least one parameter determined from a diffraction signal measured using the optical metrology system is transmitted to the fabrication cluster. The at least one parameter is used to modify at least one process variable or equipment setting of the fabrication cluster.Type: GrantFiled: June 18, 2008Date of Patent: July 20, 2010Assignee: Tokyo Electron LimitedInventors: Xinkang Tian, Manuel Madriaga, Ching-Ling Meng, Mihail Mihaylov
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Patent number: 7761250Abstract: Provided is a method of designing an optical metrology system for measuring structures on a workpiece where the optical metrology system is configured to meet two or more design goals. The design of the optical metrology system is optimized by using collected design goal data in comparison to the set two or more design goals. In one embodiment, the optical metrology system is used for stand alone metrology systems. In another embodiment, the optical metrology system is integrated with a fabrication cluster in semiconductor manufacturing.Type: GrantFiled: June 18, 2008Date of Patent: July 20, 2010Assignee: Tokyo Electron LimitedInventors: Xinkang Tian, Manuel Madriaga, Ching-Ling Meng, Mihail Mihaylov
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Publication number: 20100171494Abstract: A method for testing an MR element includes a step of obtaining a ferromagnetic resonance frequency f0 of the MR element to be tested by applying an external magnetic field in a track-width direction to the MR element, a step of calculating a stiffness magnetic field Hstiff from the obtained ferromagnetic resonance frequency f0 using a predetermined formula, a step of obtaining a relationship of a stiffness magnetic field Hstiff with respect to an external magnetic field applied in the track-width direction from the applied external magnetic field and the calculated stiffness magnetic field Hstiff, a step of obtaining a uniaxial anisotropic magnetic field Hk of a free layer of the MR element from the obtained relationship of the stiffness magnetic field Hstiff with respect to the external magnetic field applied, and a step of judging whether the MR element is good product or not by comparing the obtained uniaxial anisotropic magnetic field Hk with a predetermined threshold.Type: ApplicationFiled: January 7, 2009Publication date: July 8, 2010Applicant: TDK CorporationInventor: Takumi Yanagisawa
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Patent number: 7751998Abstract: A plurality of series circuits each consisting of a current-carrying element and an element to be measured are provided between a power supply potential VDD and a ground potential VSS. The current-carrying elements are supplied with a test signal commonly, and corresponding selection signals, respectively. After a mode is set so that power consumption of a main circuit unit included in a semiconductor device is substantially zero or almost constant, the elements to be measured are energized sequentially and, in this state, a power supply current that flows through the semiconductor device is measured sequentially. Accordingly, it is possible to accurately know the power consumption of the element to be measured and it is also possible to know the characteristics of the element to be measured based thereon.Type: GrantFiled: September 13, 2007Date of Patent: July 6, 2010Assignee: Elpida Memory, Inc.Inventor: Yasushi Matsubara
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Patent number: 7751921Abstract: In order to detect an abnormality of semiconductor manufacturing apparatus, a biaxial coordinate system having first and second axes respectively assigned two different monitoring parameters selected from plural apparatus status parameters representing statuses of semiconductor manufacturing apparatus is prepared. As monitoring parameters, for example, a cumulative film thickness for deposition processes that have previously been performed in deposition apparatus and an opening of the pressure control valve located in a vacuum exhaust path to control the internal pressure of a reaction vessel are selected. Values of monitoring parameters obtained when the semiconductor manufacturing apparatus was normally operating are plotted on the biaxial coordinate system. A boundary between a normal condition and an abnormality status is set around a plot group.Type: GrantFiled: December 22, 2005Date of Patent: July 6, 2010Assignee: Tokyo Electron LimitedInventors: Koichi Sakamoto, Minoru Obata, Noriaki Koyama
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Patent number: 7752581Abstract: A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is select to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.Type: GrantFiled: October 29, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Mary Lanzerotti, Emmanuel Yashchin, Christina Landers, Asya Takken, Brian Trapp
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Patent number: 7747404Abstract: A method for the analysis, control, automation, and information management of life-cycle processes of technical products includes an engineering process, an analysis process, a test process, and accesses an information system. The engineering process, the analysis process and the test process, which includes a plurality of test modules, have connections for information exchange exclusively to the control process and information system. For every test of the test modules, the scope and form of the input and output values are determined by data stored in the information system. The data that are input into the engineering process and determined, and the specified values, are processed by the process control, which determines all of the tests to be carried out. The results are passed on to the process control. The analysis process determines if data and specified values input in the engineering process have been reached by a numerical or numerical/statistical calculation.Type: GrantFiled: February 9, 2007Date of Patent: June 29, 2010Assignee: 7 Layers AGInventor: Hans-Jürgen Meckelburg
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Publication number: 20100161264Abstract: In a semiconductor test apparatus, a voltage source generates a power supply voltage to be supplied to a DUT. A decision processor makes the DUT execute a predetermined test sequence. A noise generator superimposes a periodic pulse-like noise voltage on the power supply voltage to be supplied to the DUT, while the test sequence is being executed. The noise generator superimposes a noise voltage synchronized with a clock signal to be supplied to the DUT.Type: ApplicationFiled: May 12, 2008Publication date: June 24, 2010Applicant: ADVANTEST CORPORATIONInventor: Mitsuo Matsumoto
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Patent number: 7742889Abstract: Provided is a method of designing an optical metrology system for measuring structures on a workpiece wherein the optical metrology system is configured to meet one or more signal criteria. The design of the optical metrology system is optimized by using collected signal data in comparison to the one or more signal criteria. In one embodiment, the optical metrology system is used for stand alone systems. In another embodiment, the optical metrology system is integrated with a fabrication cluster in semiconductor manufacturing.Type: GrantFiled: March 27, 2008Date of Patent: June 22, 2010Assignee: Tokyo Electron LimitedInventors: Xinkang Tian, Manuel Madriaga, Ching-Ling Meng, Mihail Mihalov