Abstract: Modeling systems and methods for constructing one or more models of a computing system using collected data. Certain model-based systems build topology models and/or model instances by transforming collected performance data into a collection-location independent form. In certain examples, systems include at least one agent for collecting performance data from monitored resource(s), canonical data transform (CDT) configurations, and a data transformation module for performing data transform operation(s) on the performance data based on at least one CDT configuration. The data transform operation may include generating and/or updating a topology model, assigning metrics to model object(s), updating properties of model object(s), creating associations between existing model objects, or the like. Certain systems and methods also allow for a single piece of data to be processed by multiple models or for pieces of data collected from different locations to be matched and/or associated with the same model object.

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Abstract: A method of predicting an electrochemical mapping parameter in a vehicle that derives at least a portion of its motive power from an energy storage system is provided. The method may comprise providing a plurality of electrochemical mapping parameter sources capable of rendering one or more electrochemical mapping parameters selected from the group consisting of resistance and capacitance and selecting at least one electrochemical mapping parameter source capable of rendering one or more electrochemical mapping parameters based on the state of the energy storage system. The method may also comprise determining an adaptive gain and determining an adaptive factor based on the operating state of the vehicle or the energy storage system. The method may also comprise adapting the one or more electrochemical mapping parameters based on the adaptive factor and adaptive gain to provide an adapted electrochemical mapping parameter value.

Abstract: A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin information for the module. Sensitivities of performance on yield to the variables in the subset combinations are determined. It is then determined whether yield of the target module is acceptable, and if the yield is not acceptable, a design which includes the target module is adjusted in accordance with the sensitivities to adjust the yield.

Abstract: A system for real-time three-dimensional (3D) visualization of an electrical system is disclosed. The system includes a data acquisition component, a power analytics server and a client terminal. The data acquisition component acquires real-time data output from the electrical system. The power analytics server is comprised of a virtual system modeling engine, an analytics engine, a machine learning engine and a 3D visualization engine. The virtual system modeling engine generates predicted data output for the electrical system. The analytics engine monitors real-time data output and predicted data output of the electrical system. The machine learning engine stores and processes patterns observed from the real-time data output and the predicted data output to forecast an aspect of the electrical system. The 3D visualization engine renders the virtual system model and the forecasted aspect into a 3D visual model.

Abstract: Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the polarization of each of the domains, as weighted by the weighting function. A time-dependent factor can be included in the polarization expression evaluated for each domain, to include the effect of relaxation. The effects of longer-term mechanisms, such as imprint, can be modeled by deriving a probability distribution function for the domains after an accelerated stress.

Abstract: In a method of computing the overall material constant of a composite material, a virtual composite material is defined as the one that a first material component is dispersed in a form of inner spherical particles in a matrix phase and each of the inner spherical particles is enveloped by the second material component, in a form of outer shell layers, as a coating layer. Based on this, a nonlinear equation is prepared, which has the material constant of the virtual composite material as an unknown. Next, the material constant of the virtual composite material is computed by solving the equation. In the equation, the material constant in each of the surrounding areas of the outer shell layers coating the inner spherical particles is defined as the overall material constant of the virtual composite material to be computed. The volume fractions of the material components in the composite material are computed using the equation.

Abstract: This invention relates to fault detection in electrical circuits, in particular it relates to fault detection for a plurality of adjacent input circuits. The invention provides a method and apparatus for detecting a control or communication fault on an analogue circuit by simulating said analogue circuit using a simulated circuit comprising digital circuit components; the simulated circuit receiving a control input to provide a first output; and the analogue circuit receiving said control input to provide a second output; and setting an error condition when the first output and the second output differ.

Abstract: A simulation apparatus of semiconductor device includes a first calculator, a second calculator, a third calculator, a fourth calculator, and a controller. The first calculator applies a voltage to an area which functions as a virtual electrode, and setting a pseudo-Fermi level of a first carrier in the area functioning as the virtual electrode to calculate a first carrier density. The second calculator analyzes continuous equation of a second carrier to calculate a second carrier density. The third calculator uses the first carrier density as a function of an electrostatic potential, and solving a first equation of the function and a Poisson's equation to calculate an electrostatic potential and the first carrier density expressed by the function. The fourth calculator calculates a current density of the first carrier to calculate a current flowing. The controller controls the voltage applied to the virtual electrode.

Abstract: Timing verification method includes processes wherein timing analysis is performed taking voltage drop of a laid out circuit into consideration and a changing instruction list for changing the laid out circuit is produced based on a result of the timing analysis. Then, in a first-time timing verification process, voltage drop analysis is performed for the laid out circuit so that a voltage drop list is produced based on a result of the voltage drop analysis and timing analysis is performed using the voltage drop list, and, in a later timing verification process, the voltage drop list is updated based on the changing instruction list and the timing analysis is performed using the updated voltage drop list.

Abstract: Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values from a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second set of general purpose register values on a bus.

Abstract: The present invention allows a user to graphically define a hierarchy of user-defined, executable classes of graphical objects that can be implemented in a graphical model. The present invention supports the features of inheritance, abstraction and polymorphism. Further, descendant classes of graphical objects can graphically extend the behavior and/or structure of ancestor classes of graphical objects.

Abstract: A system includes an input device, an output device, a printed circuit board, and a semiconductor device. The semiconductor device includes a semiconductor die. The semiconductor die includes a clock distribution network that distributes a primary clock signal. The clock distribution network includes a low RC local clock distribution structure. The low RC local clock distribution structure includes a conductor, a first clock signal incident on the conductor, a local gain buffer pair that receives the first clock signal and outputs a second clock signal corresponding to the first clock signal, and a shorting bar that shorts the second clock signal to a plurality of conductors.

Abstract: A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting tool shows the validation results and may be customized by the user. The tool can show in the original circuitry where the estimated results may be inaccurate.

Abstract: A method for modeling and simulating a system comprising first and second interrelated components is disclosed. The method comprises modeling the behavior of said first and second components using first and second specifications. Each of said first and second specifications includes a functional specification and an associated simulation element. The method further comprises simulating the behavior of said first and second components using said first and second specifications. The simulation elements communicate with one another to provide a simulation system.

Abstract: A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.

Abstract: Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal correlation represents a dependency relationship between a current logic state of a signal and a previous logic state of the signal. Other methods and apparatuses are also described.

Abstract: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.

Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.

Abstract: Some embodiments provide a system for accurately and efficiently modeling chemically amplified resist. During operation, the system can determine a quenched acid profile from an initial acid profile by applying multiple quenching models which are associated with different acid concentration ranges to the initial acid profile. One quenching model may be expressed as H=H0?B0, where H is an acid profile after quenching, H0 is an acid profile before quenching, and B0 is an initial base quencher profile. Another quenching model may be expressed as H=k·H0, where k is a constant. Next, the system can apply a smoothing kernel to the quenched acid profile to obtain a quenched-and-diffused acid profile. The smoothing kernel can generally be any weighted averaging function. The quenched-and-diffused acid profile can then be used to predict shapes that are expected to print on the wafer and to perform resolution enhancement techniques on a layout.

Abstract: In response to receiving HDL file(s) that specify a plurality of hierarchically arranged design entities defining a design to be simulated and that specify an instrumentation entity for monitoring simulated operation of the design, an instrumented simulation executable model of the design is built. Building the model includes compiling the HDL file(s) specifying the plurality of hierarchically arranged design entities defining the design and instantiating at least one instance of each of the plurality of hierarchically arranged design entities, and further includes instantiating an instance of the instrumentation entity within an instance of a particular design entity among the plurality of design entities and, based upon a reference in an instrumentation statement in the one or more HDL files, logically attaching an input of the instance of the instrumentation entity to an input source within the design that is outside the scope of the particular design entity.

Abstract: A logic simulation apparatus includes: a jitter detector generation section 21 that generates information concerning a jitter circuit for determining whether a time variation occurs in signal passing between a first circuit and a second circuit, the first circuit configured to output a signal with a clock output from a predetermined clock source and the second circuit configured to output a signal with a clock output from a clock source different from the above predetermined clock source; and a constraint solver generation section 22 that generates information concerning a solver that is configured to create a signal to be output at an observation point using a logical expression of an output signal of the second circuit and output, based on the logical expression and output signal of the jitter detector circuit, a signal constrained by the output signal of the jitter detector circuit and output signal of the second circuit.

Abstract: Some embodiments of the present invention provide a system that profiles a serial simulation of a circuit to estimate the performance of a parallel simulation of the circuit. During operation, the system profiles execution of module instances during a serial simulation of the circuit, wherein each module instance includes code which simulates signal propagation through a corresponding circuit module. Next, the system uses execution times for the module instances obtained from the serial simulation to estimate the performance of a parallel simulation of the circuit.

Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method performs circuit pruning for each of distinct vectors. The circuit pruning includes identifying an active circuit for each vector. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed. The circuit pruning and circuit simulations are repeated for remaining ones of the plurality of substantially distinct vectors. The results of the circuit simulations are then stored on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.

Abstract: Systems and methods for performing timing sign-off of an integrated circuit design are disclosed. In one example embodiment the integrated circuit design is divided into plurality of blocks based on a pre-determined logic. A timing model is extracted for each block using static timing analysis (STA), wherein the extracted timing model includes timing information. An integrated circuit design level STA is performed using the extracted timing model of all of the plurality of blocks to obtain first integrated circuit design timing. The first integrated circuit timing is compared with a predetermined performance criterion.

Abstract: Simulating hardware includes generating a data flow representation of the hardware, based on a hardware description language (HDL) description. The data flow representation including compatibility information that preserves behavioral and synthesizable characteristics of the HDL description. Simulating hardware further includes generating code from the data flow representation, and executing the code concurrently.

Abstract: A method of detecting differences between high level block diagram models using text based analysis. Previous methods of determining differences between high level block diagram models derive differences through traversal of the block hierarchy which is complex and cannot compare differences between models created with third party design environments. The present invention increases interoperability and capabilities of existing circuit design environments, and achieves an advance in the art, by converting high level block diagram models to a user readable text-based format and performing a text-based differential analysis on the converted models to determine differences.

Abstract: Embodiments that create parent-child relationships for reuse of 1×N building blocks in a closed-loop 1×N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1×N building block into the representation, and creating an association between the first 1×N building block and a second 1×N building block. The association enables the first 1×N building block to inherit alterations of attributes of the second 1×N building block and enables unique alterations of attributes of the first 1×N building block which differ from the second 1×N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1×N building blocks, an attribute creator that creates a set of attributes and enables one of the 1×N building blocks to inherit parent attributes and comprise child attributes.

Abstract: A method and apparatus for synthesizing pipelined input/output in a circuit design from high level synthesis is described. In one example, an operation is selected to be performed by a circuit, the operation including a plurality of partial operations of different types. The partial operations are ordered based on the ordering of the variables. A plurality of hardware components for performing the operations are represented with a data flow graph having edges and nodes, the edges and nodes being connected based on the ordering of partial operations. A plurality of solutions are simulated for performing the operations as hardware component combinations represented as paths on the data flow graph. For each solution, a cost including a number of edges and nodes traversed on the data flow graph is determined, and a solution is selected with the lowest cost as a hardware component combination for a circuit.

Abstract: A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.

Abstract: A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided. A pixel array includes one or more reference pixel sensor cells dispersed locally throughout active light sensing regions. The one or more reference pixel sensor cells provides a reference signal used to correct for photon generated leakage signals which vary by locality within the active light sensing regions.

Abstract: A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale.

Abstract: According to the illustrative embodiments, a data structure is accessed to determine a set of known data points surrounding a queried data point having an input value and an output value, the set of known data points including first, second and third data points. First and second curves are built from the first, second and third data points utilizing a first approximate model and a second approximate model. A weighting parameter value is determined by which the first curve and second curve are blended at the second data point. The output value of the queried data point is determined and stored by blending the first curve and the second curve utilizing the input value of the queried data point and the weighting parameter value.

Abstract: A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The initialized unknown Boolean states are then fed to one or more simulated logic elements and the simulator simulates the handling of the unknown Boolean state by the simulated logic elements. Examples of simulated logic elements include gates and latches, such as flip-flops, inverters, and basic logic gates. The processing results in at least one negative unknown Boolean state. An example of when a negative unknown Boolean state would result would be when the unknown Boolean state is inverted by an inverter. The resulting negative unknown Boolean state is then fed to other simulated logic elements that generate further simulation results based on processing the negative unknown Boolean state.

Abstract: Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.

Abstract: In one embodiment, a method comprising identifying a sub-network of the linear circuit, the sub-network having one or more internal nodes, one or more interface nodes, and branches connecting the one or more internal nodes and the one or more interface nodes, the sub-network having at least one of a capacitor and an inductor, is described. The method in one embodiment comprises determining a linear equation system for transient simulation of the linear circuit, the linear equation system containing no variable representing the one or more internal nodes.

Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functions, such as Gaussian distributions, are assigned for the respective values of slack, and are combined. The combination of probability distribution functions represents a measure of circuit performance. The measure is computed for alternative implementations of the circuit, and used to identify an alternative more likely to meet timing constraints.

Abstract: Approaches for preparing simulation models of an electronic circuit are disclosed. The design is partitioned into first and second clusters. The design includes a source module in the first cluster connected to a destination module in the second cluster. The first cluster is compiled into a first model for a software-based co-simulation platform for simulating behavior of the source module using the first model. The first cluster and the second cluster of the design are compiled into a second model for a hardware-based co-simulation platform that includes a programmable logic circuit configurable for emulating behavior of the design using the second model. An interconnection block is generated and stored in the second model. The interconnection block is switchable between coupling of the destination module in the second model to the source module of the first model or to a source module of the second model.

Abstract: Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification.

Abstract: The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing an environment for implementing the integrated circuit and a reference model of the integrated circuit, wherein the reference model may be prepared for running within the simulation environment. The test bench may further comprise a device for running a simulation on the reference model within the simulation environment. The reference model may be based on an original reference model provided for a formal verification.

Abstract: A method, system and computer program product for modeling variables in subprograms of a HDL program. A subprogram is provided with an initial value of a variable of an element being modeled and the subprogram is stored in memory of a data processing system. In response to a subprogram call, a copy of the stored subprogram is provided to the requesting HDL program. During execution, the initial value of the variable in the provided copy of the subprogram may be modified by the HDL program, but the value retains unchanged in the stored subprogram.

Abstract: Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

Abstract: A method and apparatus programmatically define structure within a physical modeling environment. The system and corresponding method of modeling, provides a computationally based modeling environment in which a physical entity can be modeled parametrically and hierarchically, if desired. A physical component of the physical entity is identified. The physical component is defined by a structural physical parameter and a behavior. The definitions combine to form a model element with the structural physical parameter using structural variables, and behaviors, that can be defined functionally.

Abstract: A data processor which includes: a circuit data providing section which provides circuit data including a character string; a replacement section which bijectively maps the character string of the provided circuit data to integer values; and a data developer which executes data processing including hierarchical development with respect to the circuit data of the integer values obtained by the replacement section.

Abstract: A semiconductor manufacturing method comprising, a data generating process including, acquiring a simulation light pattern that simulates a shape of a light exposure pattern formed on a substrate on the basis of design data of a semiconductor device, acquiring a simulation electron beam exposure pattern that simulates a shape of an electron beam exposure pattern formed by an electron beam exposure on the substrate on the basis of the design data, extracting difference information representing a shape difference portion between the simulation light pattern and the simulation electron beam exposure pattern, acquiring changed design data for modifying shape by changing the design data in accordance with the difference information, conducting the electron beam exposure on the substrate by use of the changed design data for modifying the shape.

Abstract: A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. In one embodiment, the timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, the power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

Abstract: A method of designing an integrated circuit includes performing a pre-layout simulation of the integrated circuit. The pre-layout simulation is performed using a netlist generated from a process design kit (PDK) file. The PDK file includes a plurality of device model cards that are assigned to plurality of devices. The plurality of devices include a first device having at least one parasitic diode that is associated with at least one isolation well, the PDK file including information of the at least one parasitic diode. A design layout of the integrated circuit corresponding to a result of the pre-layout simulation is generated.

Abstract: A method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models. The method includes collecting power supply noise monitor data from an integrated circuit having one or more power supply noise monitors connected between a power supply and respective scan cells of a scan chain and one or more functional circuits connected to the scan chain by scanning a power supply noise generation pattern into the scan chain and scanning a resultant pattern out of the scan chain; converting the resultant data into actual values of selected power supply parameters; generating simulated values of the selected power supply parameters using a power supply noise simulation model based on design data of the integrated chip; comparing the actual values of the selected power supply parameters to the simulated values of the selected power supply parameters; and modifying the power supply noise simulation model based on the comparing.