Abstract: A recording medium stores a verification program that causes a computer to execute detecting from a model circuit, a first circuit representing junction of a source region and a substrate region and including a junction resistance and a junction capacitance, a second circuit parallel to the first circuit, representing junction of a drain region and the substrate region, and including a junction resistance and a junction capacitance equivalent to the junction resistance and capacitance of the first circuit, and a connection resistance connecting the circuits and a substrate electrode; calculating, using the junction resistances and connection resistance, a first coefficient indicating impact of the junction resistances and connection resistance on amplitude variation; calculating, using the junction capacitances and connection resistance, a second coefficient indicating impact of the junction capacitances and connection resistance on phase variation; correcting the junction capacitances using a sum of the coef

Abstract: A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.

Abstract: A system, method, and software program for facilitating the assignment of cell specifications to a plurality of cells of a system design. The methods include generating a plurality of candidate cell specifications that meet the specification for the system design. In one embodiment, the method entails using information related to intra-range preference for cell specifications to generate a set of alternative system pareto-optimal solutions which define a boundary of a region of candidate cell specifications. In another embodiment, the method entails generating a substantially uniform set of candidate cell specifications using a prediction-based performance model, such as support vector regression model or cluster-weighted model, an optimizing algorithm such as conjugate-gradient or Markov Chain Monte Carlo Method, and a sample density model.

Abstract: An eye pattern is generated by: simulating a rising step response to a rising step signal input into the circuit and a falling step response to a falling step signal input into the circuit; analyzing a result of the simulating of the rising step response and the falling step response; generating, on the basis of a result of the analyzing, an upper-part test pattern that defines a shape of an upper part of an eye of an eye pattern and a lower-part test pattern that defines a shape of a lower part of the eye of the eye pattern; and simulating a response to the upper-part test pattern and the lower-part test pattern both input into the circuit. This procedure rapidly generates a precise eye pattern.

Abstract: The simulation information creating part 111 generates random numbers corresponding to the correlation coefficient data between the simulation model parameters, and also creates the simulation model library having correlated model parameters with variations, and the simulation net list for the objective characteristic, by Monte Carlo method using the typical simulation model library, the standard deviations for the plural simulation model parameters and the simulation net list for the typical objective characteristic. The simulation part 112 obtains samples having the objective characteristics with variations. The yield estimation part 120, estimates the yields by determining whether the samples satisfy the predetermined specification or not (Pass or Fail), wherein by repeating the determination by making the simulations again only for the samples on which the filter having the function of learning the boundary for decision of Pass or Fail did not determine as Pass.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.

Abstract: A method includes determining a mapping between model parameters and electrical parameters of integrated circuits. The model parameters are configured to be used by a simulation tool. A set of electrical parameters is provided, and the mapping is used to map the set of electrical parameters to a set of model parameters.

Abstract: An apparatus and method may be used for compiling a hardware logic design into data-driven logic programs to be executed on a data-driven chip. The apparatus may include storage with a library for defining a net-list synthesized by a synthesis tool. The apparatus may also include a data-driven logic verification chip comprising a plurality of logic processors. The apparatus may further include a code generator for adopting heuristics to convert the net-list into data driven logic programs and for allocating hardware resources to balance computing and storage loads across the plurality of logic processors of the verification chip.

Abstract: A method is disclosed for estimating states of a power electronic system, the system having a converter circuit. An exemplary method includes varying a system state vector x(k) and a system state vector x(k+1) for each of sampling times k=?N+1 to k=0 in such a manner that a sum formed by an addition of a first vector norm obtained by subtracting a first system model function f(x(k), u(k)) from the system state vector x(k+1), and another vector norm obtained by subtracting a second system model function g(x(k), u(k)) from the output variable vector y(k), becomes minimal over the sampling times k=?N+1 to k=0. A desired system state vector x(k) at the sampling time k=0 can then be selected.

Abstract: Circuit verification structures and techniques are disclosed that relate to both passive verification components and active verification components, including verification components that cannot (or cannot easily) be synthesized to emulator hardware. In one aspect, a computer system may record signals from a circuit under test, and then play back those signals to a simulated verification component (which may be a passive verification component) for testing purposes. In another aspect, a computer system may also construct a representative behavior model of a verification component (which may be an active component) by providing input signals to a simulated verification component, recording corresponding output signals of the simulated verification component, and using the input and/or output signals to construct a representative behavior model of that verification component.

Abstract: An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.

Abstract: A processor for use in simulating operation of a portion of an electrical circuit is provided. The processor is configured to receive at least one input indicative of electrical circuit data related to the electrical circuit being simulated, generate a model of the electrical circuit based on the at least one input, receive a user input that indicates the portion of the electrical circuit to be simulated, generate, based on the user input and the electrical circuit model, a partial circuit snapshot that corresponds to the portion of the electrical circuit, and apply at least one event to the partial circuit snapshot to simulate operation of the corresponding portion of the electrical circuit.

Abstract: Methods and apparatus disclosed herein operate to receive a plurality of cycles characterized by a set of time-domain aspects, to modify at least one of the time-domain aspects of at least some of the plurality of cycles to produce a plurality of modified cycles, to process at least some of the modified cycles to produce time-domain cycles, and to create a time-domain signal based at least in part on concatenating the time-domain cycles.

Abstract: Aspects of the invention relate to techniques for predicting circuit performance variations due to device mismatch. Circuit simulation is performed to generate circuit simulation results based on a circuit description and information of circuit element parameters. Based on the simulation results, sensitivity information for the circuit design and current/charge deviations caused by individual circuit element parameter variations may be computed. Based on the sensitivity information and the current/charge deviations, steady-state mismatch effect information is determined. The determination may comprise first computing output parameter deviations caused by the individual variations of the circuit element parameters and then computing a total output parameter deviation based on the output parameter deviations.

Abstract: A method and system for controlling granularity of transaction recording and visualizing system performance and behavior in a discrete functional verification software simulation environment is disclosed. According to one embodiment, a simulation of a model is run in a discrete event simulation system for a period of time. During the simulation, statistical values of attribute for a plurality of transactions occurring during the period of time are monitored. Based on a granularity setting, a group of consecutive transactions is grouped into a super transaction, and the statistical values representing the super transaction are recorded to represent the group of transactions. The super transactions are visualized in a visualization tool for analyzing the performance of the model.

Abstract: An electromagnetic field simulation apparatus disclosed herein replaces a predetermined region in printed circuit board CAD data to be subjected to electromagnetic field simulation with measurement data measured by a near-field measurement device and generates new printed circuit board CAD data. Subsequently, regarding a measurement data portion in the new printed circuit board CAD data generated by the data generating unit, the electromagnetic field simulation apparatus generates analysis model data by setting, as a wave source, an electric field or a magnetic field measured by the near-field measurement device. Then, the electromagnetic field simulation apparatus executes electromagnetic field simulation with respect to the analysis model data having a set wave source.

Abstract: Disclosed are apparatus, methods and software that implement a partial element equivalent circuit (PEEC) method having global basis functions on cylindrical coordinates to determine wide-band resistance, inductance, capacitance, and conductance from a large number of three-dimensional interconnections in order to provide for the electrical design of system-in-package (SIP) modules, and the like. The apparatus, methods and software use a modal equivalent network from mixed potential integral equation with cylindrical conduction and accumulation mode basis functions, which reduces the matrix size for large three-dimensional interconnection problems. Combined with these modal basis functions, the mixed potential integral equations describe arbitrary skin and proximity effects, and allow determination of partial impedance and admittance values. Additional enhancement schemes further reduces the cost for computing the partial inductances.

Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.

Abstract: The present invention relates to a system for performing a co-simulation and/or emulation of hardware and software. The system includes a hardware simulator with an integrated hardware model, a hardware and/or software environment for controlling the hardware simulator and performing a software simulation and/or a direct software application, at least one synchronization facility within the hardware model for indicating a request from the hardware and/or software environment, a receiver for setting the synchronization facility into a predetermined state, and a controller for switching the hardware simulator between a free-running state and a request-handling state.

Abstract: Enabling scheduling of single cycle as well as scheduling multi-cycle rules in a synchronous digital system whose behavior is governed by an asynchronous system specification (e.g., a TRS) provides a way to allow complex actions at state transitions of the asynchronous system without requiring that the complex actions be synthesized in logic that must be performed in a single clock cycle. For example, a relatively infrequent action may include a critical timing path that determines the maximum clock frequency of the system. By allowing that infrequent action to take multiple clock cycles, even if that action takes more absolute time, other actions may take less absolute time by virtue of being able to operate the synchronous system at a higher clock rate. The overall system may then operate more quickly (e.g., as measured by the average number of rules applied per unit of absolute time).

Abstract: A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (01) are clocked synchronously every cycle (19) of a functional clock (Clk). According to the invention, real digital circuit (01), i.e. chip or combinatorial logic (01), timing information is included in the cycle simulation by inserting delay latches (15, 16, 17) into the cycle based simulation model (34) of the digital circuit (01), wherein a non-functional clock (Sim clock) is used to clock the delay latches (15, 16, 17), so that each delay latch (15, 16, 17) delays the propagation of a signal (I, J, K) by a cycle (20) of the non-functional clock (Sim clock).

Abstract: Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

Abstract: A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract: A method is provided for providing a debugging tool for a hardware design specified in a hardware description language. The method includes receiving one or multiple source files of the specified hardware design; processing each source file in a way that hardware description language constructs from the hardware design are directly simulatable; wherein the processing process includes at least one of the following: restructuring procedural source code of the source file; preserving functional equivalence to unaltered source code of the source file; and adding debug information to the hardware description of said source file.

Abstract: A system and method are provided including a component in communication with a plurality of memory circuits and a system. The component is operable to interface the memory circuits an the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The component is further operable to perform a power saving operation.

Abstract: One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.

Abstract: A computer-readable recording medium stores therein a program causing a computer that accesses a simulator to execute receiving a measured yield distribution that expresses an actually measured yield distribution concerning leak current of a circuit-under-design, and model data for leak current of a cell of the circuit-under-design; providing the simulator with the model data and values for a normal distribution concerning variation components of the leak current of the cell; acquiring the leak current of the circuit-under-design; calculating, based on the acquired leak current, an estimated yield distribution concerning the leak current of the circuit-under-design; calculating values for the normal distribution that minimize error between the measured yield distribution and the estimated yield distribution; setting an initial value to the normal distribution and the calculated values for the normal distribution to the normal distribution; and outputting the estimated yield distribution that is based on the l

Abstract: A set of instructions executable at an integrated circuit is partitioned into multiple instruction blocks. A first and second instruction block are executed multiple times, including a first execution and a second execution. The first execution of the first instruction block is associated with a first set of executions, and the first execution of the second instruction block is associated with a second set of executions. A first amount of energy consumption representative of a member of the first set of executions is determined, and a second amount of energy consumption representative of a member of the second set of executions is determined. The first amount of energy is assigned to each member of the first set, and the second amount of energy is assigned to each member of the second set, and used to determine a total amount of energy consumption associated with execution of the set of instructions.

Abstract: A system and method of parallel processing includes a computer system including a first processor, the first processor being a control flow type processor, a second processor, the second processor being a data flow type processor. The second processor is coupled to a second memory system, the second memory system including instructions stored therein in an order of execution and corresponding events data stored therein in the order of execution. A first one of the instructions are stored at a predefined location in the second memory system. The system also includes a run time events insertion and control unit coupled to the first processor and the second processor. The first processor, the second processor and the run time events insertion and control unit are on a common integrated circuit.

Abstract: A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X?1 and at least one other matrix, with first equation including X?1Y, X?1A, and X?1P, and the second equation including X?1A and X?1P.

Abstract: A computer-implemented method for simulating an electrical circuit. The method includes (a) setting a first temperature distribution in the electrical circuit, (b) performing an electrical simulation across the electrical circuit taking into consideration the first temperature distribution, (c) performing a thermal simulation across the electrical circuit taking into consideration a result of the electrical simulation, to obtain a second temperature distribution, and (d) determining whether a criterion for termination the simulation is met. If the criterion is met, terminate the simulation. If the criterion is not met, assign the second temperature distribution to the first temperature distribution, and repeat steps (b), (c), and (d).

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: A method for simulating a chip is provided. The method initiates with defining a library of components for a processor. Then, the interconnections for a set of pipelined processors including the processor are defined. Next, a processor circuit is generated by combining the library of components and the interconnections for the set of pipelined processors. Then, a code representation of a model of the set of pipelined processors is generated. Next, the signals generated by the code representation are compared to the signals generated by the processor circuit. If the comparison of the signals is unacceptable, then the method includes identifying a cause of the unacceptable comparison of the signals at a block level of the processor circuit. A method for generating a netlist for a pipeline of processors, a method for debugging the processor circuit and computer code for simulating a chip circuit are also provided.

Abstract: In an analyzing apparatus, an input accepting unit accepts input information including an analysis condition of a circuit element (circuit) to be analyzed, an analysis-SPICE-file generating unit generates an analysis SPICE file based on the input information, and an analysis-SPICE-file executing unit executes the analysis SPICE file, thereby analyzing the characteristic of the circuit element.

Abstract: A method and simulator for generating phase noise in a system with a phase-locked loop (PLL) are disclosed. Each simulation block of the system with the PLL has its own predefined phase noise vector whose elements are injected consecutively at a trigger event. An element selection of the predefined noise vector of is steered from the master element block, which is usually the voltage or current-controlled oscillator. Some simulation blocks, called semi-master element blocks, are self-triggered and determines their own injection frequency rates, and are reset-steered and aligned with the master element block as a capturing data phase starts; while other simulation blocks, called slave element blocks, are directly steered with the master element block.

Abstract: Characteristics of a circuit element are predicted accurately by taking account not only of the temperature variation due to self-heating of the element but also of temperature variation due to heat transmission from an adjoining heater element.

Abstract: In an example embodiment, the system receives user inputs including: (1) a netlist that describes the circuit elements and connections of an integrated circuit; (2) a mathematical device model that corresponds to the integrated circuit and that includes an equation with a number of parameters and decision variables grouped into terms; and (3) a description of an input voltage. Based on these inputs, the system calculates an output such as a voltage or current. The system displays a GUI that includes a view which shows each of the terms of the equation after a value has been assigned to each parameter and to each decision variable and a view which shows each of the terms of the equation after reduction of the values assigned to each parameter and each decision variable. Upon receipt of a user's change to the value of a parameter, the system promptly updates the views.

Abstract: A method may include receiving an input from an optimization control that indicates a value along a scale, wherein the value is indicative of a design tradeoff between at least optimization for a first parameter of an electrical design and an optimization for a second parameter of the electrical design, wherein the value places an emphasis on the first parameter and an emphasis on the second parameter such that when the value on the scale is closer to the first parameter a larger emphasis is placed on the first parameter of the electrical design and when the value on the scale is closer to the second parameter a larger emphasis is placed on the second parameter of the electrical design. The method may further include choosing components for the electrical design based on the value indicated using the optimization control, the emphases affecting the components selected for the electrical design.

Abstract: A method and apparatus for testing the functionality of a circuit design uses working system data that is recorded in real-time to stimulate and/or verify a software simulation of the circuit design that does not run in real-time. In a selected embodiment, a system for simulating and verifying a software model of a baseband module circuit design is described in connection with using real-time input and output data captured from a corresponding circuit in a reference platform. The captured real-time data may include digital baseband I/Q samples and/or extracted control data pertaining to the signal level, channel frequency, gain, output power, frequency offset, DC offset, or the like. The captured data may be regenerated for use as a stimulus for the software model of the circuit design and/or to verify the functionality of the design.

Abstract: For application to analog, mixed-signal, and custom digital circuits, as well as other fields have use for high-dimensional regression, or symbolic modeling, a system and method to extract functions, where each function relates a set of input variables to an output variable (performance metric). The technique enumerates a large set of candidate basis functions, performs pathwise regularized learning on those basis functions to generate a set of candidate models, and finally performs nondominated filtering to identify models that trade off complexity versus error.

Abstract: Disclosed is a method and system for providing an improved and flexible approach for handling models of hardware and software designs for verification activities. The semantics of the software and hardware are mapped to allow correct interfacing between the hardware and software models. This allows designers to more efficiently and accurately perform hardware/software co-verification.

Abstract: In one embodiment of the invention, a method of simulating a circuit is disclosed including partitioning a circuit into a plurality of blocks, each of the plurality of blocks being radio-frequency blocks or non-radio frequency blocks; performing a first simulation of a first simulation type with the radio-frequency blocks to generate output waveforms of the radio-frequency blocks; performing a second simulation of a second simulation type with the non-radio-frequency blocks to generate output waveforms of the non-radio-frequency blocks where the second simulation type differs from the first simulation type; and synchronizing the first simulation and the second simulation together at one or more time steps to generate output waveforms for the circuit.

Abstract: Embodiments may include methods, systems, and computer-readable storage mediums that may be used to simulate phase noise for an oscillator circuit. In some embodiments, a method of simulating phase noise for an oscillator circuit may include providing an oscillator circuit description. A time-domain representation of a small signal phase noise of the oscillator circuit description may be determined. A shooting Newton matrix representation of the time-domain representation of the small signal phase noise may be generated. The shooting Newton matrix representation may be augmented to include a phase-shift factor and a pinning equation. The augmented shooting Newton matrix representation may be solved to determine a signal output of the oscillator circuit.

Abstract: A system on a chip comprises a plurality of circuit blocks, a programmable processor and a communication circuit. Design information includes connection data including an identification of the direct mutual connection and first and second circuit blocks coupled by the direct mutual connection. An additional register is added to the system on a chip coupled to the direct mutual connection. Verification programs are used includescomprising instructions for the processor to access registers in the second one of the circuit blocks, to use the connection data, or information derived therefrom to select the first one of the circuit blocks, and to issue the standardized call to the interface program of the selected further one of the circuit blocks.

Abstract: A system for controlling signals coming from or going to an aircraft simulator has a first slave circuit and a second slave circuit. The second slave circuit is used to monitor signals coming from the aircraft simulator. A multiplexer circuit is coupled to the first slave circuit. The first slave circuit sends control signals to the multiplexer circuit for controlling digital output signals being sent to the aircraft simulator. A master controller is coupled to the first slave circuit and the second slave circuit. The master controller is used for controlling operation of the first and second slave circuit. A computer system is coupled to the master controller. The computer system will display a listing of the aircraft simulator signals to be controlled. Selection of a desired aircraft simulator signal by an input device of the computer system will allow one to control the selected aircraft simulator signal.

Abstract: An integrated circuit including an I/O register, wherein based on the behavior level design data, I/O register access information is generated. Then, based on the I/O register access information and association of an SW address with an HW address, address map information is generated. The SW address being used when the processor device accesses the I/O register, and the HW address being used when the user logical circuit accesses the I/O register. Based on the behavior level design data and the address map information, behavior level design data is generated.

Abstract: Systems and method for providing a microgrid power analytics portal for mission critical power systems are provided. The techniques disclosed herein provides for real-time modeling, evaluation, and commodity market pricing and optimization for an electrical network that includes microgrids using data collected from virtually any digital data source. The portal is platform independent and can be configured to collect and aggregate real-time data from sensors interfaced with components of the electrical network regardless of proprietary architectures or vendor-specific limitations imposed by the sensors or data collection software.

Abstract: A device to simulate an integrated circuit (IC) includes a main body, a simulating signal generating module, and a converting module. The simulating signal generating module is positioned on the main body and generates signals indicative of signals of the IC. The converting module is positioned on the main body and converts the signals from digital to analog form. The connecting board is assembled to the main body and sends the converted signals to a printed circuit board (PCB).