Abstract: A computer-readable medium encoded with an instruction check program for making a computer to check a status of execution of an instruction by an I/O simulator that performs an operation simulation according to a structure of an I/O area of a microcomputer, the instruction check program when executed by a computer causes the computer to perform a method including obtaining specification information of the microcomputer describing an input and an output condition of a hardware resource in the I/O area, detecting a simulation of a reference instruction to the hardware resource executed by the I/O simulator, determining correctness of the reference instruction by comparing a content of the simulation of the reference instruction detected by the detecting with the input and output condition of the hardware resource included in the obtained specification information, and outputting an error signal when it is determined that the reference instruction is incorrect.

Abstract: A circuit verification method for a logic circuit is presented. The method includes developing a first hardware description language (HDL) code representative of the logic circuit and, for an embedded portion of the logic circuit, developing a second HDL code representative of the embedded portion. The second HDL code includes a process of forcing inputs of the embedded portion to one or more known values. The method further includes operating a processing device in conjunction with the first and second HDL codes and verifying operation of the embedded portion in response to forcing the inputs to the logic circuit.

Abstract: A processing architecture and methods are disclosed in which a simulation state vector can be contained in a common memory, formatted in a known form, distributed in a deterministic bus to a sea of logic processors, and returned to the common memory through the deterministic bus.

Abstract: A logic simulation program, method and system for obtaining a set of reachable states for a logic design that can be used to provide input to other algorithms that simplify the netlist describing the logic design or perform other types of processing, provides an efficient, compact behavior when simulating large designs. Rather than simulating using ternary input and state value representations that are restricted to true, false and unknown, the techniques of the present invention use input symbolic values that are retained in the set of reachable states retained as the output. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states can be detected in the simulation results and the netlist simplified using the results of the detection.

Abstract: A computer-implemented method for performing testing on executable logic includes providing, in a test framework, an instance of at least one object that is associated with an object-processing framework. The test framework has at least one interface that is common with the object-processing framework. The method includes calling a logic portion that is to be tested, the logic portion being called with at least one test parameter received from a user. The method includes recording a result of an operation that is performed as the logic portion causes the at least one object in the test framework to be accessed using the at least one interface. Also a related computer program product and graphical user interface.

Abstract: A method for digital circuit design. The first step of the process is the step of providing a circuit design in the form of a hardware definition language. Then, the process produces a binary simulation of the design by setting out for each unit of time during execution of the hardware design the a control state and a program state of the design and assigns a symbol to each signal of the design. The process proceeds by executing a symbolic simulation of the design, concluding with identifying and capturing the combinational logic expression of the simulation output and the next state functions of the simulation.

Abstract: Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.

Abstract: A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value.

Abstract: A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design. The method also includes determining a leakage current cumulative distribution function (CDF) for the first design. The method further includes preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design. Further, the method includes estimating leakage current for the second design. The method also includes determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design. Moreover, the method includes selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design.

Abstract: Method, system, and computer program product. The method may include: receiving a model of a circuit that includes logic that is designed to receive sequence information and/or constants from input modules of the circuit. Updating the model or generating a new model that includes an interface and an initialization module. The initialization module may provide, to a hardware accelerator and during an initialization of a simulation of the circuit, the constants and/or the sequence information. The interface may interface between a simulator and a hardware accelerator that includes one or more FPGAs. Generating FPGA code of an amended logic that includes the logic and a programmable module; wherein the programmable module may receive, during the initialization of the simulation, the constants and/or the sequence information, and to provide during the simulation and to the logic, at least one out of the constants and a sequence represented by the sequence information.

Abstract: A method and corresponding device provides for automatically detecting a protocol for a load testing routine. The method includes the steps of, for an application to be load tested, executing the application and recording communications between a first tier and a second tier during the execution. The recording step includes recording modules loaded by the application, recording network traffic and Web traffic, comparing the recorded modules, network traffic and Web traffic to a rule set, and based on the comparing step, selecting one or more protocols appropriate for load testing the application. Finally, the method includes the step of generating a script based on the recorded communications and the protocols, where the script specifies the protocols.

Abstract: A parametrically controlled model-based test generator automatically generates architectural compliance test suites for different implementations of a processor architecture, based on a set of architectural decisions chosen among optional behaviors for each implementation. Thus, different implementations of the same architecture can be easily supported by modifying the parameter values. In addition, ongoing changes to the architecture or comprehensive updates to the test suite can be easily handled by updating the architecture model or the coverage models, forgoing the need to review the whole, potentially huge, set of tests.

Abstract: A system and method are provided including an interface circuit in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the plurality of memory circuits and the system for simulating at leas one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The interface circuit is further operable to control refreshing of the plurality of memory circuits.

Abstract: An emulation system includes a first circuit for emulating a first logical part of a device, a second circuit for emulating a second logical part of the device that is different from the first logical part, wherein the first circuit is separate from the second circuit, and a third circuit connecting the first circuit and the second circuit to communicate signals between the first circuit and the second circuit.

Abstract: A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.

Abstract: A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.

Abstract: A high-level integrated circuit (“IC”) modeling system (400) includes a first co-simulator (418) modeling a first portion of an IC system and a second co-simulator (419) modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (426). A co-simulation synchronization interface (424) is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition (428) in response to a user-selected triggering signal.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.

Abstract: A computer-implemented method of finite state machine using constraint relaxation. A first expression having a plurality of variables is accessed. A second expression is accessed that describes a constraint with respect to a first variable of the plurality of variables. At least one of the variables from the second expression is eliminated to create a third expression with the constraint relaxed. The third expression is applied to the first expression to determine a finite state machine for the first expression.

Abstract: A method for building a magnetic bead mathematical model includes defining component elements of the model of the magnetic bead, building the model of the magnetic bead, obtaining a characteristic curve of an impedance of a magnetic bead in a standard magnetic bead specification of the magnetic bead, ascertaining parameters of the component elements, simulating the model of the magnetic bead, and comparing the characteristic curve with the characteristic curve in the standard magnetic bead specification, to further optimize the mode of the magnetic bead.

Abstract: A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: There is provided with simulation execution apparatus including: a receiving unit configured to receive a cyclic signal; registers; a simulation execution unit configured to execute simulation of a logic circuit model which operates with the use of the cyclic signal and the registers; a counter configured to count time based on the cyclic signal; a register value monitoring unit configured to monitor the values of the registers; a register data recording unit configured to record in a storage, register data made up of the values of the registers in association with the time of the counter when the value of at least one of the registers is changed; a cyclicity detection unit configured to detect a cyclicity of the register data based on the storage; and a stop unit configured to give a stop instruction signal which instructs stop of the simulation execution to the simulation execution unit.

Abstract: Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes a circuit reservoir, a circuit parser and a circuit evaluator. The circuit reservoir is configured to receive and store a model of a circuit having at least one memory storage device to be analyzed. The circuit parser is configured to identify nodes of the model. The circuit evaluator is configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes.

Abstract: Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.

Abstract: Method and apparatus for modeling processor-based circuit models are described. Some examples relate to designing a circuit model having a processor system and custom logic. A bus adapter coupled to a bus of the processor system is generated. A shared memory interface between the custom logic and the bus adapter is generated. The shared memory interface includes a memory map for the processor system. A clock wrapper having a first clock input and a second clock input is generated. The first clock input drives the custom logic and first shared memory of the shared memory interface. The second clock input drives the processor system.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: A computer-implemented method for verifying a design includes representing a verification directive, which pertains to the design and includes a local variable, by a finite state machine. The state machine includes multiple states, with transitions among the states, transition conditions associated with the transitions, and procedural blocks, which correspond to the transitions and define operations to be performed on the local variable when traversing the respective transitions. The finite state machine is executed by traversing the transitions in accordance with the respective transition conditions and modifying the local variable in accordance with the respective procedural blocks of the traversed transitions, so as to verify the design with respect to the verification directive.

Abstract: Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

Abstract: An information processing apparatus connected to an emulator to arrange a verification model and a verification target includes a compile unit configured to create a first data transfer unit arranged in a computer to transfer data from the computer to the emulator based on a description of a file function of a verification program and a generation unit configured to generate a second data transfer unit that receives the data from the first data transfer unit and transfers the received data to the verification target based on the description of the file function.

Abstract: A simulation environment is disclosed wherein both analog and RF signals are simulated in a single flow by a mixed-domain simulator. The simulator includes a simulator kernel with an analog solver and an RF solver to allow both analog- and RF-type of signals to be solved in an interrelated fashion. The simulator may also include a partitioner that divides the circuit into various RF and analog modules to be solved. User input may control the partitioning process, but the simulator may refine the partitions or generate sub-partitions to provide a higher probability of convergence.

Abstract: A logic simulation apparatus includes: a jitter detector generation section 21 that generates information concerning a jitter circuit for determining whether a time variation occurs in signal passing between a first circuit and a second circuit, the first circuit configured to output a signal with a clock output from a predetermined clock source and the second circuit configured to output a signal with a clock output from a clock source different from the above predetermined clock source; and a constraint solver generation section 22 that generates information concerning a solver that is configured to create a signal to be output at an observation point using a logical expression of an output signal of the second circuit and output, based on the logical expression and output signal of the jitter detector circuit, a signal constrained by the output signal of the jitter detector circuit and output signal of the second circuit.

Abstract: In response to receiving HDL file(s) that specify a plurality of hierarchically arranged design entities defining a design to be simulated and that specify an instrumentation entity for monitoring simulated operation of the design, an instrumented simulation executable model of the design is built. Building the model includes compiling the HDL file(s) specifying the plurality of hierarchically arranged design entities defining the design and instantiating at least one instance of each of the plurality of hierarchically arranged design entities, and further includes instantiating an instance of the instrumentation entity within an instance of a particular design entity among the plurality of design entities and, based upon a reference in an instrumentation statement in the one or more HDL files, logically attaching an input of the instance of the instrumentation entity to an input source within the design that is outside the scope of the particular design entity.

Abstract: Method and apparatus for profiling a hardware/software embedded system are described. In one example, a hardware co-simulation interface is generated between a programmable logic device (PLD) configured with the embedded system and a computer based on a plurality of events. The embedded system in the PLD is simulated. During the simulation of the embedded system, occurrence of at least one event is detected to produce profiling data. The profiling data is stored into shared first-in-first-out (FIFO) logic of the PLD and the computer. The profiling data is retrieved from the shared FIFO logic at the computer.

Abstract: A computer-implemented method of incorporating a module within a circuit design can include, responsive to identifying the module to be imported into the circuit design, automatically identifying each port of the module, displaying a list of the ports of the module, and receiving a user input selecting a plurality of ports of the module for inclusion in an interface through which the module communicates with the circuit design. Responsive to a user input specifying an interface type, the interface type can be associated with the plurality of ports. The interface type can be associated with a port list including standardized ports. Individual ones of the plurality of ports can be automatically matched with standardized ports from the port list. A programmatic interface description specifying the interface for the module can be output.

Abstract: An example method is provided and includes executing a functional test for an integrated circuit and observing a failure associated with the integrated circuit. The method also includes executing a functional scan mode in order to reproduce the failure associated with the integrated circuit. A functional state of the integrated circuit is locked when the failure occurs, and the functional state is subsequently recovered for a structure test for the integrated circuit. In more particular embodiments, particular states of the functional test are evaluated and compared against other states associated with a model circuit that did not experience any failure in order to identify a latest cycle of the integrated circuit that could trigger the failure and an earliest cycle of the integrated circuit that could observe the failure.

Abstract: In a method of displaying a waveform of a simulation result, a waveform file extractor which extracts information of voltage values in addition to simulation times, values, and signal names input as waveform information, and a waveform display unit which enables a display of the wave information with the voltage values added are included. Thus, when a waveform of a multiple power-supply simulation is displayed on a display, voltage information is displayed together with the waveform, thereby allowing the voltage information to be analyzed together with a change in value at each simulation time. Thus, efficient analysis is achieved.

Abstract: Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.

Abstract: A method for specifying and synthesizing a synchronous digital circuit by first accepting a specification of an asynchronous system in which stored values are updated according to a set of state transition rules. For instance, the state transition rules are specified as a Term Rewriting System (TRS) in which each rule specifies a number of allowable state transitions, and includes a logical precondition on the stored values and a functional specification of the stored values after a state transition in terms of the stored values prior to the state transition. The specification of the asynchronous circuit is converted into a specification of a synchronous circuit in which a number of state transitions can occur during each clock period.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: A device for monitoring events. The device may have a programmable event engine for detecting events and a memory array coupled to the event engine. The array may store data for programming the event engine to monitor for the events. The device may have an external pin coupled to the event engine. The event engine may monitor a signal on the external pin to detect events external to the device. Alternatively, the device may output a signal on an external pin in response to detecting one of the events.

Abstract: As a program tool of the embodiment estimating the peak of power consumption, primary processing is performed in which logic simulation is executed in a first time period to extract operation data of a gated clock for every predetermined section within the first time period, e.g. operation waveform data or data on the number of operations. Then, a narrowed section, which is composed of one or more sections and in which the switching activity per unit time is higher compared to other sections, is discovered, the switching activity being obtained from the operation data, and this narrowed section is taken as a second time period. Then, secondary processing is performed in which logic simulation is executed in the second time period to extract signal waveform data for every clock cycle and obtain power consumption data corresponding to the clock cycles from the extracted signal waveform data.

Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

Abstract: A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: A computer-readable recording medium configured to store a verification support program, the program causing a computer to execute logic verification operations for a system including a plurality of control circuits, and a plurality of hardware units that correspond to the control circuits. The logic verification operations are executed using a verification model of the system. The verification model includes a control circuit model which has a function of the control circuit, and a plurality of hardware models which have functions of the plurality of hardware units. The logic verification operations include accepting instructions from the plurality of hardware models by the control circuit model; selecting an instruction to be processed by one of the plurality of hardware models from the accepted instructions by the control circuit model; and reporting a processing request of the selected instruction to the plurality of hardware models by the control circuit model.

Abstract: Clock gating analysis of a target circuit having a plurality of clock gates, involves the calculation of a clock gate function for each of the clock gates. The clock gate functions indicate an activation state of the clock gates and a combination of output values from sequential circuit elements in the target circuit are substituted into each of the clock gate functions to obtained clock gate function values. Combinations of the clock gate function values form individual clock gating states. Each clock gating state indicates an activation state of each of the local clocks, collectively. A table indicating correlations between the combinations of output values and the clock gating states is generated and from the conversion table, a group that includes all of the clock gating states possible is output.

Abstract: A method for testing an integrated circuit includes simulating the integrated circuit and generating waveforms of signals at a plurality of nodes of the integrated circuit, generating a text file representing the signal waveforms by detecting a waveform change of the signals, and analyzing the text file.

Abstract: Apparatus for storing all logic simulation signal values generated by a logic simulator during a simulation run is provided. The apparatus includes a runtime array for storing a plurality of signal values for each time instance in a predetermined time period, and a checkpoint cache for selectively storing the plurality of signal values stored in the runtime array at selected time instances. A hyper-checkpoint array is further provided to checkpoint the signal values in the checkpoint cache. In addition, the time instances and values of memory writes are also checkpointed. A user may retrieve the value of any signal values generated during the simulation run and may additionally rewind the simulator to a user-specified time in the simulation run.

Abstract: At a simulation client, a design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a plurality of count event counters that count occurrences of count events in the design during stimulation by the testcase. At multiple intervals during stimulation of the HDL simulation model by the testcase, the simulation client records count values of the plurality of count event counters. The simulation client determines, for each of the multiple intervals, a temporal statistic regarding the count values of the plurality of count event counters and outputs a report containing temporal statistics for the multiple intervals.

Abstract: A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.

Abstract: Techniques for simulating operation of a connectivity level description of an integrated circuit design are provided, for example, to simulate logic elements expressed through a netlist description. The techniques utilize a host processor selectively partitioning and optimizing the descriptions of the integrated circuit design for efficient simulation on a parallel processor, more particularly a SIMD processor. The description may be segmented into cluster groups, for example macro-gates, formed of logic elements, where the cluster groups are sized for parallel simulation on the parallel processor. Simulation may occur in an oblivious as well as event-driven manner, depending on the implementation.