Abstract: A device maintenance apparatus includes a setting operator configured to allow for setting a test pattern, the test pattern being set to define a change of output signals output from a device over time, and an execution operator configured to make the device output the output signals based on the set test pattern.

Abstract: A controller system includes a microprocessor having a sequencer configured to output at least one spare multiplexor control signal, a memory, and a plurality of sensor inputs. At least one stimulation circuit is connected to a sensor signal line. The at least one stimulation circuit being connected to the at least one spare multiplexor control signal. The stimulation circuit is configured such that a state of the at least one spare multiplexor control signal controls a state of the stimulation circuit.

Abstract: The present disclosure relates to the field of device testing. In one embodiment, a method is provided for testing a resource constrained device. The method includes determining a test case for testing the resource constrained device, and accessing a test script corresponding to the test case. The test script includes a set of mutually independent primitive executables. The method further includes transmitting each of the set of primitive executables to the resource constrained device for execution, and receiving a result corresponding to the execution of the each of the set of primitive executables.

Abstract: A customer of a computing resource service provider may use an interface to access a graphical composer and generate one or more graphical representations of applications that may be provided to a variety of users of the customer's one or more resources. Once the customer has created a graphical representation of an application, a domain specific language model based at least on the graphical representation of the application may be created such that one or more simulations may be performed to determine whether the requested application includes any errors or conflicts. If the one or more simulations result in the application including no errors or conflicts, the domain specific language model may be compiled in an executable programming language to create the application. The application may then be provided to users who may utilize devices capable of understanding the executable programming language to install the application.

Abstract: Embodiments of present disclosure relates to a method and a system for implementation of user logic in a FPGA device. For the implementation, user logic is mapped onto cells of the FPGA device in implementation platform associated with FPGA device. The mapping is based on user logic constraints to be met and received for FPGA device. Further, mapped cells of FPGA device are placed in implementation platform based on local mapping optimization parameters. The placing also comprises of performing placement optimization on placed cells of FPGA device. Upon placement, placed cells of FPGA device are routed in implementation platform based on at least local mapping optimization parameters and local placement optimization parameters. The routing also comprises of performing routing optimization on routed cells of FPGA device.

Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.

Abstract: A technique relates a superconducting microwave cavity. An array of posts has different heights in the cavity, and the array supports a localized microwave mode. The array of posts includes lower resonant frequency posts and higher resonant frequency posts. The higher resonant frequency posts are arranged around the lower resonant frequency posts. A first plate is opposite a second plate in the cavity. One end of the lower resonant frequency posts is positioned on the second plate so as to be electrically connected to the second plate. Another end of the lower resonant frequency posts in the array is open so as not to form an electrical connection to the first plate. Qubits are connected to the lower resonant frequency posts in the array of posts, such that each of the qubits is physically connected to one or two of the lower resonant frequency posts in the array of posts.

Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.

Abstract: Systems and methods are provided for an automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.

Abstract: A microphone apparatus is provided. The microphone apparatus includes a microphone cover; a circuit board, an integrated circuit, a first microphone, and a second microphone. The integrated circuit is coupled to the microphone cover and the circuit board to form a first chamber and a second chamber. The first microphone is placed inside the first chamber and configured to capture a first acoustic signal from a sound source. The second microphone is placed inside the second chamber and configured to capture a second acoustic signal from the sound source. The first microphone and the second microphone have the same sensitivity, phase, and omni-directivity. The integrated circuit performs a time-delay process on the second acoustic signal and subtracts the time-delayed second acoustic signal from the first acoustic signal to generate a differential signal. The integrated circuit forms a polar pattern of the microphone apparatus according to the differential signal.

Abstract: Embodiments relate to pre-silicon device testing using a persistent command table. An aspect includes receiving a value for a persistent command parameter from a user. Another aspect includes determining whether the value of the persistent command parameter is greater than zero. Another aspect includes based on determining whether the value of the persistent command parameter is greater than zero, selecting a number of commands equal to the value of the persistent command parameter from a regular command table of a driver of a device under test. Another aspect includes adding the selected commands to the persistent command table of the driver. Another aspect includes performing testing of the device under test via the driver using only commands that are in the persistent command table of the driver.

Abstract: A device may receive one or more first objects and one or more second objects to be processed. The device may store, in a first queue, information identifying the one or more first objects, the one or more second objects, and an order in which the one or more first objects and the one or more second objects were received. The device may store, in a second queue, information identifying the one or more first objects based on the one or more first objects being associated with the first priority level. The device may process the one or more first objects and the one or more second objects based on the first queue and the second queue. The device may perform one or more actions based on processing the one or more first objects and the one or more second objects.

Abstract: A method for converting real number modeling to a cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, requesting a user input parameter, converting the file to a cycle-driven simulation interface file based on the user input parameter, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a computer readable medium to perform the above method are also provided.

Abstract: A method for converting real number modeling to cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, cleaning the real number modeling code in the file, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a non-transitory, computer readable medium to perform the above method are also provided.

Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.

Abstract: Circuitry for the simulation of partial reconfiguration of a logic design for an integrated circuit device using a hybrid model is provided. The circuitry may create a hybrid model by combining structural model netlists of one or more partial reconfiguration partitions of the logic design with a behavioral model of a static partition of the logic design. The hybrid model may undergo partial reconfiguration verification to ensure that undefined signals do not bypass a freeze bridge and pass from registers in the partial reconfiguration partitions to the static partition, and to ensure that these registers are each in a defined state after the partial reconfiguration operation and a register reset operation are completed.

Abstract: An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit. Execution of one or more scripts select the initialization sequence from a plurality of test cases, set the breakpoint, modify a state of the circuit design as the next action to perform, and capture a plurality of test results based on execution of the initialization sequence through the interface unit.

Abstract: A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.

Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.

Abstract: A method for converting a real number modeling to a synthesizable register-transfer level emulation in digital mixed signal environments is provided. The method includes verifying an input in a file including a real number modeling code and cleaning the real number modeling code in the file. The method also includes separating a clean register-transfer level code from the real number modeling code, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. The method further includes converting the cycle-driven simulation interface file into a register-transfer level file suitable to perform a circuit emulation in digital mixed signal environments, and verifying that the register-transfer level file is ready to perform circuit emulation in the digital mixed signal environments. A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

Abstract: Disclosed herein is a method for displaying a monitoring viewer in an HMI system. The method includes, upon receiving a request to display a monitoring viewer from a user, acquiring screen data to be displayed in the monitoring viewer; displaying a control area of the monitoring viewer on a display; displaying a view area of the monitoring viewer on the display; and displaying a monitoring screen in the view area by using the screen data. The view area includes one or more taps. Monitoring performance and efficiency of the HMI system can be increased.

Abstract: A device may receive input code that includes one or more input objects. The input code may be used in connection with generation of output code. The output code, when generated, may include one or more output objects, corresponding to and different than the one or more input objects. The device may receive or determine conversion information identifying a conversion operation to perform to generate the one or more output objects based on the one or more input objects. The conversion information may be received separately from the input code. The device may generate, based on the conversion information and the input code, an intermediate representation. The intermediate representation may include one or more annotations corresponding to the one or more input objects and defining the conversion operation. The device may compile, based on the intermediate representation, the output code. The device may execute or provide the output code.

Abstract: The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.

Abstract: Systems and methods are provided for a ZZZ coupler. A first tunable coupler is coupled to the first qubit and tunable via a first control signal. A second tunable coupler is coupled to the first tunable coupler to direct a flux of the first qubit into a tuning loop of the second tunable coupler, such that when a first coupling strength associated with the first tunable coupler is non-zero, a second coupling strength, associated with the second tunable coupler, is a function of a second control signal applied to the second tunable coupler and a state of the first qubit. The second qubit and the third qubit are coupled to one another through the second tunable coupler, such that, when the second coupling strength is non-zero it is energetically favorable for the states of the first and second qubits to assume a specific relationship with respect to the Z-axis.

Abstract: Approaches for debugging include receiving by a hardware debug server, a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input to a simulator. The simulator adds a conditional breakpoint on the finite state machine in response to the hardware debugging command and executes a simulation of the finite state machine representation. Execution of the simulation is suspended in response to the detecting the condition in the finite state machine.

Abstract: A testing system includes a vacuum pump, testing equipment and a vibration device. A vacuum tray is configured to provide relative movement between a DUT and the vacuum pump, testing equipment and the vibration device. The vacuum tray includes a vacuum chamber configured to define a sealed vacuum environment around the DUT, and a DUT support carried by the vacuum chamber and configured to support the DUT within the chamber during testing thereof. The DUT support includes a pedestal configured to hold the DUT within the chamber during vibration testing, and an extension that extends outside the vacuum chamber and is configured to connect to the vibration device. An electrical test interface unit is carried by the vacuum chamber and configured to connect between the DUST and the test equipment, and a vacuum interface is carried by the vacuum chamber and configured to connect to the vacuum pump.

Abstract: A method for formally verifying a hardware/software co-design includes providing in a co-design, a first model, and a second model, the first model is one of a hardware model, and the second model is one of a software model, or vice versa, providing a safety property expected to be satisfied by the co-design, combining an abstraction of the first model and the safety property to obtain an abstracted first model, composing the abstracted first model and the second model to obtain a composed model, checking if the composed model satisfies the safety property, and signaling that the hardware/software co-design violates the safety property if the safety property is violated in the composed model.

Abstract: A system for tracing an operation of an electronic circuit is provided. The system includes an electronic circuit, a trace buffer, and a trigger detection circuit. The trace buffer includes a plurality of segments configured to continually collect and store data signals of the electronic circuit. The data signals are collected in a current segment of the plurality of segments. The trigger detection circuit is adapted to provide a trigger signal when a trigger condition is met. Each time upon generation of the trigger signal when the trigger condition is met, the collection of the data signals is stopped in the current segment and subsequent data signals are collected in a new segment of the plurality of segments.

Abstract: A system for allocating field-programmable gate array (FPGA) resources comprises a plurality of FPGAs operable to implement one or more pipeline circuits, the plurality of FPGAs comprising FPGAs of different processing capacities, and one or more processors operable to access a set of data comprising a plurality of work items to be processed according to a pipeline circuit associated with each of the plurality of work items, determine processing requirements for each of the plurality of work items based at least in part on the pipeline circuit associated with each of the plurality of work items, sort the plurality of work items according to the determined processing requirements, and allocate each of the plurality of work items to one of the plurality of FPGAs, such that no FPGA is allocated a work item with processing requirements that exceed the processing capacity of the FPGA.

Abstract: An initial data state is obtained for an adaptive system. A simulation is started for the adaptive system on an electronic computing device. A first trial is run of the simulation of the adaptive system until a first stop point is reached. When the first stop point is reached, one or more recursive simulations are run from the first stop point. After the one or more recursive simulations have been run, an optimized set of modified data states for the adaptive system at the first stop point is automatically determined. Using the optimized set of modified data states, the run of the first trial of the simulation is continued from the first stop point until either additional stop points are reached or the first trial of the simulation is completed. An additional set of optimized modified data states is determined for at least one of the additional stop points.

Abstract: The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor. The multiple instances are evolved simultaneously in the presence of coupling between the qubits of different instances. Quantum processor architectures that are adapted to facilitate replica coding are also described.

Abstract: A power measurement circuit is disclosed. The power measurement circuit comprises a sampling register, a latch generator, an accumulation unit, a calculation unit and an output register. The sampling register samples an input signal based on a sampling clock to generate a binary digit. The latch generator generates a latch signal based on the sampling clock and a measurement interval. The accumulation unit accumulates the binary digit based on the latch signal to generate a sum value. The calculation unit calculates an ON-phase rate of the input signal according to the sum value and the measurement interval. The output register stores a power consumption value according to the ON-phase rate of the input signal.

Abstract: Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least one local memory unit that allows for data reuse opportunities. The first custom computing apparatus optimizes the code for reduced communication execution on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.

Abstract: Methods and systems are disclosed related to multi-rate parallel circuit simulation. In one embodiment, a computer implemented method of partitioning the circuit into a plurality of partitions, wherein each partition is represented by a set of linear differential equations, determining a simulation time step for each partition of the plurality of partitions, grouping the plurality of partitions into multiple groups, wherein each group includes one or more partitions having simulation time steps within a predefined range of each other, and solving the multiple groups with their corresponding simulation time steps in parallel.

Abstract: A method and system for automatically auditing an electronic component design process comprising a plurality of design steps. The method includes: extracting, optionally in parallel and in a single pass, a plurality of non-error data types from obtained electronic component design information to produce one or more summary files; and determining whether an audit failure exists in a current design step of the plurality of design steps based on a comparison of the one or more summary files with one or more stored failure indicators. The one or more stored failure indicators comprising a plurality of non-error triggers associated with later failures. The present disclosure simplifies the organization of the gathered data to prevent the automated electronic design process from generating an inferior design, which wastes time of both human and computing resources.

Abstract: The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation.

Abstract: An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit.

Abstract: A method can include receiving an input signal having multiple signal edges, performing an initial scan of the input signal to identify peaks corresponding to the signal edges, and determining whether each peak is a Uniformly Synchronous (US) edge or a Quasi-Synchronous (QS) edge. The method can also include generating a final waveform and displaying the final waveform on a display device.

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received. The design comprises a functional cell. A first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of the functional cell is provided. The first substitute functional cell comprises at least one pin moved by an amount of the first value. A determination is made as to whether an amount of shift of the set of routing tracks corresponds to the first value. The functional cell is replaced with the first substitute functional cell in response to a determination that the amount of shift of the set of routing tracks corresponds to the first value.

Abstract: Apparatus and method for accelerated testing of a multi-device storage system. In some embodiments, the storage system includes a server adapted to communicate with a user device, and a plurality of data storage devices adapted to store and retrieve data objects from the user device. The server maintains a map structure that describes the data objects stored on the data storage devices. A fault injection module is adapted to induce simulated failures of selected data storage devices in relation to a time-varying failure rate distribution associated with the data storage devices that indicates an observed failure rate over a first time interval. The simulated failures are induced by the fault injection module over a second time interval shorter than the first time interval. The server operates to modify the map structure responsive to the simulated failures.

Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.

Abstract: A graphical model may include a plurality of graphical objects representing physical elements, and connections between graphical objects may be represented by physical connection lines. A set of physical connections between two or more graphical objects may be configured as belonging to a group. A switching unit may toggle the graphical model between a single-line display mode and a multi-line display mode. In the multi-line display mode, each of the individual physical connection lines linking two or more graphical objects are displayed in the model. In response to user or other input, the switching unit may redraw the graphical model in single line mode in which the individual physical connections configured as a group are replaced with a single, composite connection line. The graphical model may be executable to simulate the physical system, and the execution may be unaffected by the display mode.

Abstract: A computer program product includes program instructions to: Receive a unit including register transfer level content for a component of an integrated circuit and one or more IP blocks; Select one or more input pins for each IP block; Assign a numerical value of either zero or one to each of the one or more input pins to yield at least one numerical sequence; For each numerical sequence, perform a check to yield a number of fails, wherein the check is formal verification of each of the one or more IP blocks; Determine a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails; Set the one or more input pins to the simulation condition for power modeling of the unit; and Determine a number of design errors of the unit based on the simulation condition.

Abstract: Embodiments of the present invention are directed to a method and system for developing an analytic process. The method includes displaying, within an electronic system, a plurality of components operable to be used for designing a data analysis process. A user makes a selection of a data access component from the plurality of components. The data access component is operable for configuring access to a data source. The method further includes the user making a selection of a data selection component from the plurality of components and a data display component. The data selection component is operable for selecting data accessed via the data access component. The data display component is operable for configuring display of data based on the data selection component. Configuration data corresponding to the data access component, the data selection component, and the data display component can then be stored.

Abstract: A method for identifying a value of an unknown circuit component for an analog signal having a known output profile in which a simulation list of the analog circuit is first created including the component with the unknown value. A transfer function for the known output value is then created using a programmed processor and the transfer function is then solved by the processor for the value of the unknown component. For nonlinear circuit components, a linear model is substituted for the nonlinear components prior to creating the simulation list.

Abstract: Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts digital logic circuits such as Boolean logic, flip flops, latches, and memory circuits to be operable with signals having unknown states. Thus, an unknown state of a signal is indicated and propagated through digital logic circuits represented in a disclosed semantic to enable prompt detection of improper operation of the DUT, for example, due to power shut down or inadequate initialization.

Abstract: Various example implementations are directed to methods and systems for simulating circuit designs having configuration parameters. According to one example implementation, code blocks of a circuit design for which execution of operations described by the code blocks is conditioned on a value of one or more of a set of configuration parameters, are identified. For each identified code block, a respective expression is determined that indicates whether or not the code block will be executed for different sets of values of the set of configuration parameters. The circuit design is simulated for a first set of values for the configuration parameters. The simulation is performed using a model that omits code blocks that describe sets of operations that will not be executed. The determined expressions are evaluated to determine whether or not each identified code block was realized in the simulation model.

Abstract: An obfuscation assisting apparatus assists in the obfuscation of a program. The obfuscation assisting apparatus includes an analyzer which identifies corresponding respective blocks in the source code and in the transformed code generated through the obfuscation of the source code. A browser obtains obfuscation information relating to obfuscation of the respective blocks of the source code and the transformed code, and causes an output device to display the respective parts of the source code and the transformed code, and the obfuscation information in association with each other.