Abstract: The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S2). The voltage fluctuation analysis step at the gate level is executed on an entire chip TP. Next, a step of obtaining waveforms of power supply voltage and ground voltage (Vss) according to the voltage fluctuation analysis step is executed (step S4). Subsequently, a signal analysis step at a transistor level is performed (step S6). The signal analysis step at the transistor level is performed in an area narrower than the entire chip TP, for example, on one or more functional modules. After that, a step of obtaining a signal analysis result according to the signal analysis step is executed (step S8).

Abstract: The present disclosure relates to a method of optimizing the area of series gate layout structures for FinFET devices. The method analyzes an integrated chip (IC) layout to determine a first gate material density along a first direction and to separately determine a second gate material density along a second direction based upon the first gate material density. A number of series gate stages for a FinFET (field effect transistor) device having a gate length along the second direction, is chosen based upon the second gate material density and one or more device performance parameters of the FinFET device. By analyzing the density of gate material in separate directions, the effective length of the gate of the FinFET can be increased without increasing the size of the transistor array.

Abstract: Provided is a circuit simulation model that can suitably represent capacitor characteristics, thereby realizing accurate circuit design and circuit analysis. A SPICE model is constituted of a capacitor unit in which a capacitor is replaced with a linear voltage dependent current source, a low-pass filter unit that has a function of extracting a DC bias voltage, a calculation circuit unit that is configured by combining an adder, a multiplier, and the like to perform a calculation of a circuit equation derived from an equivalent circuit for a capacitor such as an idealized C circuit model, an RC circuit model, or the like, and a linear voltage dependent voltage source that applies a total voltage applied across the capacitor to the calculation circuit.

Abstract: There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a plurality of pieces of cycle-based mapping information (21) for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit (10) and configuration selection information (22) for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus (1) includes a control unit (11) that reconfigures at least part of the logic region (10) using at least one of the plurality of pieces of cycle-based mapping information (21) according to a request in each cycle based on the configuration selection information (22).

Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for comparing results of performing a plurality of operations with results of simulating the plurality of operations. These mechanisms and methods for comparing results of performing a plurality of operations with results of simulating the plurality of operations can enable optimized performance of operations, reduced processing time, increased confidence in processing results, etc.

Abstract: A verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition is greater than the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in the test scenario group.

Abstract: The disclosure describes approaches for processing a circuit design. For each object of a plurality of objects of the circuit design, a respective key is generated as a function of a plurality of configuration parameter values of the object. Each object is renamed with a unique name that includes the key. A netlist of the circuit design is generated using the unique names and keys of the objects.

Abstract: Modeling and simulating behavior of a transistor are described. At least one sub-circuit model for modeling at least one second order effect associated with the transistor is obtained. At least one instance parameter for the at least one second order effect is obtained. Operation of a transistor behavior simulator is augmented with the at least one sub-circuit model populated with the at least one instance parameter such that the simulating of the behavior of the transistor produces data that takes into account the at least one second order effect. The at least one second order effect may be an LOD/eSiGe effect, a poly pitch effect, or a DSL boundary effect. Also described is a method for generation of a sub-circuit model.

Abstract: A hybrid simulation model includes a real model, a bus interface and an acceleration model. The real model simulates a group of instructions. The acceleration model includes a trace generation unit, a trace replay unit, a selection unit, a snapshot generation and load unit and a virtual breakpoint control unit. The trace generation unit records at least one trace file of the real model in a first simulation. The trace replay unit reads and accordingly accesses the at least one trace file. The selection unit dynamically switches to perform a real simulation or a trace simulation. The snapshot generation and load unit generates at least one status snapshot file and loads the at least one status snapshot file to the real model in repeated simulations. The virtual breakpoint control unit controls the selection unit to switch between the trace simulation and the real simulation according to a virtual breakpoint.

Abstract: A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels.

Abstract: Software for controlling processes in a heterogeneous semiconductor manufacturing environment may include a wafer-centric database, a real-time scheduler using a neural network, and a graphical user interface displaying simulated operation of the system. These features may be employed alone or in combination to offer improved usability and computational efficiency for real time control and monitoring of a semiconductor manufacturing process. More generally, these techniques may be usefully employed in a variety of real time control systems, particularly systems requiring complex scheduling decisions or heterogeneous systems constructed of hardware from numerous independent vendors.

Abstract: A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links.

Abstract: A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of design constraints by replacing the abstracted logical operations with uninterpreted functions; and property checking the abstraction model in relation to one or more design properties. When a violation in the electronic circuit is detected by the property checking step, the feasibility of the violation is then checked and, if the violation is deemed infeasible, the abstraction model is refined.

Abstract: Technologies relating to real time logic simulation within a mixed mode simulation network are described. Mixed mode simulation networks may comprise Boolean Processing Units (BPUs) and Real Time Processing Units (RTPUs). Mixed mode simulation networks may send an input simulation state vector to the processing units, and the processing units may process portions thereof to calculate portions of an output simulation state vector. BPUs may be adapted to calculate portions of the output simulation state vector without accounting for delay times attributable to operation of a simulated system, while RTPUs may be adapted to calculate portions of the output simulation state vector with accounting for delay times attributable to operation of the simulated system. The calculated portions of the output simulation state vector may be combined in a computational memory, and the resulting output simulation state vector may be used as an input simulation state vector in a next simulation calculation cycle.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: In one embodiment, a method to simulate an HDL specification is provided. For each call to a procedure, an intermediate process is dynamically created during simulation. The process containing the call to the procedure is replaced with the intermediate process in an active process list of processes scheduled for execution. The intermediate process is configured to call the procedure and, in response to completing execution of the procedure, cause the simulator to add the calling process to the front of the active process list and remove the intermediate process from the active process list.

Abstract: A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.

Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of related edges of a design graph to compute signal propagation delay. For each subcircuit stage, full timing delays of each edge can be concurrently computed. This includes concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.

Abstract: Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.

Abstract: A method may include generating logical transition data for the logic cell based on an analysis of a digital model for the logic cell, the logical transition data including at least one entry indicative of an output transition of the logic cell occurring in response to an input transition of the logic cell. The method may also include generating a parameterized transition based analog model for the logic cell, the parameterized transition based analog model including transition timing parameters associated with each entry of the logical transition data. The method may further include generating an analog model for the logic cell based on the parameterized transition based analog model and one or more analog netlists characterizing the logic cell.

Abstract: Systems and methods for run-time switching for simulation with dynamic run-time accuracy adjustment. In one embodiment, a computer implemented method performs a simulation of a computer instruction executing on a simulated hardware design by a first simulation model, wherein the first simulation model provides first timing information of the simulation. The first timing information is stored to a computer usable media. A pending subsequent simulation of the instruction is detected. Responsive to the presence of the first timing information in the computer usable media, the computer instruction is simulated by a second simulation model, wherein the second simulation model provides less accurate second timing information of the simulation than the first simulation model. The simulation run time information is updated for the subsequent simulation with the first timing information.

Abstract: A simulation system having multiple peripherals that communicate with each other. The system includes a weighted graph with weights set as communication times. The peripherals are represented as nodes and connection paths are represented as edges. Among the communication times in the loop, the minimum time is set as first synchronization timing. Timing with an acceptable delay added is set as second synchronization timing. Timing set by a user to be longer than the first and second timings is set as third synchronization timing. The third synchronization timing is used in a portion where the timing is usable, thus synchronizing the peripherals at the longest possible synchronization timing.

Abstract: Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains.

Abstract: A mechanism is provided in an integrated circuit simulator for tracking array data contents across three-value read and write operations. The mechanism accounts for write operations with data values and address values having X symbols. The mechanism performs writes to a tree data structure that is used to store the three-valued contents to the array. The simulator includes functionality for updating the array contents for a three-valued write and to read data for a three-valued read. The simulator also includes optimizations for dynamically reducing the size of the data structure when possible in order to save memory in the logic simulator.

Abstract: Software for controlling processes in a heterogeneous semiconductor manufacturing environment may include a wafer-centric database, a real-time scheduler using a neural network, and a graphical user interface displaying simulated operation of the system. These features may be employed alone or in combination to offer improved usability and computational efficiency for real time control and monitoring of a semiconductor manufacturing process. More generally, these techniques may be usefully employed in a variety of real time control systems, particularly systems requiring complex scheduling decisions or heterogeneous systems constructed of hardware from numerous independent vendors.

Abstract: Approaches for preparing a system that is reconfigurable to implement a plurality of optional hardware functions are disclosed. In one approach, a method includes simulating the operation of the system during a time interval. The system is reconfigurable to implement a subset of the optional hardware functions, and the simulating determines which of the optional hardware functions are active and which of the optional hardware functions are inactive during a plurality of subintervals of the time interval. Respective circuit resource sets are estimated for the subintervals of the time interval. For each of the subintervals, the respective circuit resource set implements the system including the optional hardware functions that are active during the subinterval. Information describing the respective circuit resource sets for the subintervals is stored for preparing partial reconfigurations of the system.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.

Abstract: Mechanisms are provided for controlling a fidelity of a simulation of a computer system. A model of the system is received that has a plurality of components. A representation of the plurality of individual components of the system is generated. A component is assigned to be a fidelity center having a highest possible associated fidelity value. Fidelity values are assigned to each other component in the plurality of individual components based on an affinity of the other component to the fidelity center. The system is simulated based on assigned fidelity values to the components in the plurality of individual components.

Abstract: A circuit interconnection structure for synchronizing a network of oscillators placed on a semiconductor substrate. One such structure comprises a first synchronizing circuit electrically coupled to a second synchronizing circuit through tunable delay circuits. Also disclosed are methods to tune oscillators placed in different regions of a circuit having multiple clock domains by estimating the relative slack of a first group of signals within the circuit with regard to the period of a first clock domain, and estimating the relative slack of the second group of signals within the circuit with regard to the period of second clock domain, wherein the estimating is performed at process and operational corners that cover the variability of the circuit at different speed conditions, then calculating tuning values for the oscillator delays for each region such that the oscillator delay slack matches the worst relative slack of the signals of the same region.

Abstract: Methods and systems for modeling a multiprocessor system in a graphical modeling environment are disclosed. The multiprocessor system may include multiple processing units that carry out one or more processes, such as programs and sets of instructions. Each of the processing units may be represented as a node at the top level of the model for the multiprocessor system. The nodes representing the processing units of the multiprocessor system may be interconnected to each other via a communication channel. The nodes may include at least one read element for reading data from the communication channel into the nodes. The node may also include at least one write element for writing data from the nodes into the communication channel. Each of the processing unit can communicate with other processing unit via the communication channel using the read and write elements.

Abstract: A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts.

Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.

Abstract: A simulation parameter extracting method of a MOS transistor according to an exemplary aspect of the present invention includes evaluating a measured value that includes a true gate-overlap capacitance by measuring a capacitance between the gate and the drain in each of a plurality of layout patterns at a predetermined bias voltage, only the number of contact plugs being different for each layout pattern, evaluating a gate-overlap capacitance calculation value of each layout pattern by subtracting a contact parasitic capacitance between the contact plug and the gate from the measured value, the contact parasitic capacitance being obtained by a simulation with varying a model parameter for evaluating a parasitic capacitance between the contact plug and the gate, and extracting the gate-overlap capacitance calculation value as the true gate-overlap capacitance at the model parameter when the gate-overlap capacitance calculation value is about constant regardless of the number of the contact plugs.

Abstract: A system and method are described for converting a circuit description into transaction-based description at a higher level of abstraction. Thus, a designer can readily view a series of transactions that occurred in the simulation of a circuit. In one aspect, the simulated signals are analyzed and converted into messages of a protocol used by the design. A combination of the messages represents a transaction. Thus, the simulated signals are then converted into a series of protocol transactions. In another aspect, a message recognition module performs the analysis of the simulated signals and converts the simulated signals into messages (e.g., request for bus, bus acknowledge, etc.). A transaction recognition module analyzes the messages and converts the messages into transactions (e.g., Read, Write, etc.). Using both the system and method the circuit description is converted into a higher level of abstraction that allows more comprehensive system-level analysis.

Abstract: A mechanism is provided for verifying a register-transfer level design of an execution unit. A set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system. The result checker compares the two results and, responsive to a mismatch in the results, a failure of the test case is indicted, the verification of the test case is stopped, and all data associated with the test case is output from the buffer for analysis.

Abstract: Systems and methods for simulating and verifying an analog mixed signal design provide an analog mixed signal testbench configured to verify analog parameters of the design. The testbench can include a mechanism to fetch a value of an analog object in an analog portion of a mixed signal design. The testbench mechanism can include an argument specifying the name of the object and the analog quantity to be fetched for that object. The testbench can retrieve estimated values and can further specify timing constraints specifying absolute times or events at which values are to be measured and returned.

Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system.

Abstract: A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure.

Abstract: A method for computing power consumption includes querying a software database for a key node and a gate comprising an input port, connected to the key node, and an output port. The software database is created from a net list associated with a design. The method includes calculating a probability of activity level at the output port based on a predetermined activity level at the key node, and querying the software database for next gate comprising a next input port, connected to the previous output port, and a next output port. The method includes calculating a probability of activity level at the next output port based on the probability of activity level at the previous output port. The method includes computing a sub-circuit gate power by sum of power of all the gates based on the probability of activity level at output ports of the gates.

Abstract: The present invention certifies control modules of engineered safety feature instruments for a power plant automatically. The control modules can be tested before storing or operating. The test is done with enhanced testing speed and saved cost. Thus, safety of the control modules is confirmed.

Abstract: A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.

Abstract: Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.

Abstract: An apparatus and method may be used for compiling a hardware logic design into data-driven logic programs to be executed on a data-driven chip. The apparatus may include storage with a library for defining a net-list synthesized by a synthesis tool. The apparatus may also include a data-driven logic verification chip comprising a plurality of logic processors. The apparatus may further include a code generator for adopting heuristics to convert the net-list into data driven logic programs and for allocating hardware resources to balance computing and storage loads across the plurality of logic processors of the verification chip.

Abstract: A computerized system comprising: a processor; a first interface configured to obtain a constraint; a second interface configured to obtain a first model, wherein the first model is configured to be utilized in model checking, and the first model, when constrained by the constraint, comprises at least one finite path; and a finite path removal module implemented in the processor and configured to generate a second model equivalent to the first model obtained by said second interface, wherein the second model excludes a portion of the at least one finite path, and the second model is configured to be utilized in model checking.

Abstract: A method for implementing production processes includes a step of programming a state machine for each production process. The programming step includes a definition of a plurality of states and a definition of a plurality of transitions between states, corresponding to possible actions which the corresponding production process may execute. The programming step further includes the steps of detecting whether or not one or more states to be defined for a state machine have already been defined for state machines already programmed for other production processes, and executing the definition of states only for states not detected in the detecting step.

Abstract: A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (01) are clocked synchronously every cycle (19) of a functional clock (Clk). According to the invention, real digital circuit (01), i.e. chip or combinatorial logic (01), timing information is included in the cycle simulation by inserting delay latches (15, 16, 17) into the cycle based simulation model (34) of the digital circuit (01), wherein a non-functional clock (Sim clock) is used to clock the delay latches (15, 16, 17), so that each delay latch (15, 16, 17) delays the propagation of a signal (I, J, K) by a cycle (20) of the non-functional clock (Sim clock).

Abstract: Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract: Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT.