Abstract: An apparatus for simulating the internal configuration of industry standard ROM and EPROM-type chips using other types of storage technologies, while still operating transparently with interfaces and mechanisms such as authentication devices adapted to EPROM-type media. The invention includes: an EPROM connector interface, a data presentation program; user access log display program; a user login/registration program; a software/data library; software/data selection program; and software/data loader program. These components work in conjunction to securely retrieve software images resident in mass storage media and to present them to an authentication device as if the images were resident in EPROM type media. The invention is particularly adapted to use in the gaming industry where regulation and fraud detection are performed using EPROM authentication techniques.

Abstract: A cache replacement system for extending the debugging capabilities of accelerated simulation by enabling enhanced cache data and state checking is provided. The system includes a Cell Broadband Engine Architecture (CBEA) compliant system implementing Replacement Management Tables in an accelerated simulation environment. The RMTs control cache replacement and allow the software to direct entries with specific address ranges at a particular subset of the cache. The RMTs further allow for locking data in the cache and are utilized to prevent overwriting data in the cache by directing data that is known to be used only once at a particular set. Using the locking mechanism in an accelerated simulation environment, a user is able to run code sets, which, when the microprocessor system being tested is correctly designed, generates identical and verifiable data and cache states in each of the different sets of the cache.

Abstract: An emulation technique adjusts the execution timing of instructions included in an application to be emulated. An emulator executes an instruction stream consisting of a plurality of instructions included in the application for an apparatus to be emulated to perform the object AP. This emulator performs successively the instructions included in the instruction stream at a predetermined period, and includes a speed controller for adjusting the emulation speed by intermittently inserting a wait into the instruction stream to emulate execution of the instruction stream. Preferably, this emulator includes a clock generator (145), in which the speed controller counts the clock input from the clock generator (145).

Abstract: An exemplary system includes a development subsystem configured to facilitate development of a software application and a simulation subsystem selectively and communicatively coupled to the development subsystem. The simulation subsystem is configured to emulate a plurality of processing device platforms, receive data representative of a selection of at least one of the plurality of processing device platforms, and simulate an execution of the software application by one or more processing devices associated with the at least one selected processing device platform.

Abstract: Multi-structured memory is described, including a first memory configured to emulate a first memory type, a second memory configured to emulate a second memory type, the first and second memories disposed in one or more third dimensional memory arrays, and an interface configured to access the first memory or the second memory for data operations. The one or more third dimensional memory arrays are formed on the same component and can be fabricated BEOL on top of a substrate (e.g., a silicon wafer or other semiconductor substrates) including active circuitry (e.g., CMOS devices) fabricated FEOL and operative to perform data operations on the memory arrays and to communicate with external systems configured to access the memory arrays. The third dimensional memory(s) can include two-terminal non-volatile re-writeable cross-point memory arrays including two-terminal non-volatile re-writeable memory cells having their respective terminals electrically coupled with a pair of conductive array lines.

Abstract: A method and apparatus for designing a processor-based emulation integrated circuit (chip) having a selectable fastpath topology. Included are initially designing an N-level fastpath topology comprising a plurality of processors, then reducing the N-level fastpath topology to an M-level topology such that the performance of the topology meets a design criterion, e.g., capable of evaluating data during a time of an emulation step. In this manner, an emulator chip designer may configure the fastpath topologies without redesigning the chip layout.

Abstract: A processor-based emulation system for emulating an integrated circuit design, the processor-based emulation system including emulation circuitry and capture circuitry. The capture circuitry is operable to capture processing results from the emulation circuitry. The captured processing results can be used to identify functional errors in the integrated circuit design. Because the processor-based emulation system includes capture circuitry, emulation circuitry is not used for capturing the processing results.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.

Abstract: This application generally describes techniques for dynamically updating trusted certificates and CRLs, generally referred to herein as certificate information. That is, techniques are described for updating trusted certificates and CRLs without terminating existing communication sessions. An exemplary method includes the steps of receiving an initial configuration that includes a trusted certificate authority, receiving certificate information that includes a certificate revocation list (CRL) and a first certificate from the trusted certificate authority, storing the certificate information in the configuration, initiating a communication session for an application, receiving an update to the certificate information, and updating the configuration to reflect the update to the certificate information without terminating the communication session.

Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.

Abstract: An apparatus, circuit arrangement and method for emulating a hardware design by time division multiplexing data communicated between an emulator and a runtime assist unit (RTAU), such as a behavior card. Data from the emulator may be received directly at the general purpose registers of the RTAU. A programmable delay may be used in conjunction with a step generator to initiate concurrent cycle processes. Code executed by the RTAU may be coded in assembly, and external interrupts that might otherwise affect the determined processing time of the RTAU task are disabled. The time multiplexing reduces card port, cabling and processing cycle requirements.

Abstract: A method and apparatus for coupling data between discrete processor-based emulation chips is described. The apparatus is a processor-based hardware emulation integrated circuits (chips) element comprising a plurality of discrete hardware emulation chips, each emulation chip coupled to another emulation chip by a crossbar for coupling data between the plurality of chips. The method comprises providing data to a crossbar from a first discrete emulation chip, selecting the data from the crossbar using a discrete second emulation chip, and storing the data in a data array in the second discrete emulation chip.

Abstract: A computing device hosts a virtual machine executing a guest that issues guest hardware requests by way of any of a plurality of paths. Such paths include a path to non-existent virtual hardware, where an emulator intercepts and processes such guest hardware request with a corresponding actual hardware command; a path to an instantiated operating system, where the instantiated operating system processes each such guest hardware request with a corresponding actual hardware request; and a path to device hardware, where the device hardware directly processes each such guest hardware request.

Abstract: Approaches for recovering state data between boot sessions of an emulated operating system (OS). An OS is emulated on a host OS. In response to each memory acquire request from the emulated OS, an interface to the host OS returns a memory area for use by the emulated OS and stores allocation data associated with the memory area. The allocation data includes an address referencing the memory area and a boot sequence number that indicates a boot session of the emulated OS. While booting the second emulated OS to a current boot session, the stored allocation data is retrieved from the interface, and in response to the stored allocation data including a selected boot sequence number, data from the memory area referenced by the address in the allocation data is stored in retentive storage by the second OS.

Abstract: A method for emulating a system call includes making the system call by a first process in a first operating system (OS) for interacting with a second process, wherein the first OS is emulated in a second OS, spawning an agent process, wherein the agent process is a child process of the first process, implementing a functionality of the system call using a general mechanism in the second OS between the agent process and the second process, passing a result associated with the system call from the second process to the agent process using the general mechanism, and relaying the result from the agent process to the first process using a system call in the second OS, wherein the result is stored by the first process.

Abstract: While PC trace is on, and the trace is in predication or general event profiling mode, trace hardware captures events in each cycle. Trace hardware inserts this information into data logs, and does a right shift to compact the data. The trace window will eventually close, either because tracing has been turned off, or because a periodic sync point is generated to reset the window. In either of these two cases, the data log may be incomplete, fully packed, or just overflow into the next packet. An index is generated pointing to the last valid location in the data log in order to save transmission bandwidth.

Abstract: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

Abstract: An in-circuit emulation system with a programming function includes a system power supply, a DC/DC converter, a processing device, a programmer socket and a connector. The system power supply produces a first DC voltage. The DC/DC converter converts the first DC voltage into a second DC voltage and a third DC voltage. The processing device has a processor and a parallel/serial converter. For executing a programming function, the processor uses the parallel/serial converter to convert programming codes into corresponding programming signals. The programmer socket receives the programming signals, the second DC voltage and the third DC voltage to accordingly execute a programming function on an IC plugged in the socket. The connector has one end connected to the processing device and the other end connected to a target board to thereby drive and receive electrical signals of the target board on performing an in-circuit emulation.

Abstract: A system and method for emulating SCSI reservations using network file access protocols is provided. The system and method enable applications or operating systems on a networked computer designed to utilize SCSI reservations on only locally attached storage to also access networked data storage. The emulation occurs transparently to higher levels of operating systems or applications so that the applications or operating systems which are designed to only access locally attached storage may be enabled to access networked storage.

Abstract: A mechanism for translating objects between applications that use different formats is described. As described, a source object is generated using a source application. The source object is then translated to a target object in a target application. The target application having a format that is not supported by the source application. A first modification, which is not supported by the source application, is then performed to the target object. A second modification is also performed to the source object in the source application. Based on the modifications, the target object in the target application is revised to reflect the second modification to the source object without removing the first modification to the target object.

Abstract: A circuit emulation system and method are provided, the system including at least one trace chain and a trace memory in signal communication with the at least one trace chain for sequentially receiving values and feeding them back through the chain to their original storage unit positions; and the method including modeling the circuit, providing at least one storage unit in the model, emulating the circuit with the model, extracting a state of the at least one storage unit during emulation, storing the extracted state, and restoring the stored state through a feedback loop.

Abstract: A method of tracing data processor activity includes trace data markers indicating initiation and termination of at least one trace function at a specified program counter address and emulation pause related markers indicating initiation and termination of an emulation halt state at a specified program counter. Each emulation pause related marker includes a conflict bit indicating the presence or absence of a simultaneous trace data marker having a different program counter address.

Abstract: Methods and apparatus for allowing different mapping implementations, including a many-to-one logical to physical block mapping, to be used within a memory system are disclosed. According to one aspect of the present invention, a method for mapping a plurality of logical blocks to a physical block includes identifying a first logical block meets at least one criterion. The method also includes identifying a second logical block which is substantially complementary to the first logical block, and providing contents associated with the first logical block and contents associated with the second logical block to the physical block.

Abstract: Systems and methods to emulate user network activity to change the profiling of users of the network are disclosed. A method includes monitoring network activity corresponding to a particular user. The method includes automatically generating emulated user network activity when a usage pattern is detected in the monitored network activity. The emulated user network activity may be detectable by a user tracking engine as the network activity of the particular user and the user tracking engine may attempt to profile the emulated user activity.

Abstract: In an embodiment, new traffic pattern data is received pertaining to a first time period having a first time increment. The traffic pattern data may be received as, or converted to, count information reflecting the probabilities that the user will select particular links services. An incremental table is accessed to determine stale traffic pattern count data, which is the traffic pattern count data in the incremental table over a second time period having the first time increment, wherein the second time period covers the oldest traffic pattern count data in the incremental table. Then a count table is updated to reflect removal of the stale traffic pattern count data, wherein the count table contains global count data at a higher level of granularity than the incremental table. The incremental table and count table are updated to reflect addition of the new traffic pattern data.

Abstract: The method according to the invention is characterized in that on the basis of an existing task model, which may be provided by an expert, it is enhanced with the current state of the user in his task, the events allowing a change of state of the user are described, and the interaction to be performed with the user to manage an event is described for this event occurring during a state of the user. Advantageously, before each interaction procedure, the list of constraints necessary for triggering the interaction is added, and after each interaction procedure, the values that this interaction should provide according to the result of the interaction and which should be presented to the user as feedback are added.

Abstract: An emulator for emulating a wireless network comprised of a plurality of RF nodes is comprised of a programmable controller for emulating the movements of the plurality of RF nodes within an emulated space. The controller provides both information and control signals based on the emulated movements. A programmable logic core receives a plurality of signals from the plurality of RF nodes and emulates signal propagation based on the information from the controller. A plurality of signal generation and conversion cards are interposed between the programmable logic core and the RF nodes. The signal generation and conversion cards are responsive to the control signals. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: Configuring reconfigurable interconnect resources employing a switch matrix and configuration bit look-up table are disclosed. Reconfigurable interconnect resources include multiplexors to decrease the number of bits needed to load a configuration. Distributed processing resources configure a selected reconfigurable interconnect resource, interconnecting each input of the reconfigurable interconnect resource with a particular output of the reconfigurable interconnect resource using configuration bits scalably extracted from a row of configuration bits of a look-up table. Use of a configuration bit look-up table allows for compression of the bits needed to load the configuration for a reconfigurable interconnect resource.

Abstract: Provided is a computer system comprising: a failure symptom detection unit for detecting a symptom of a failure in hardware of a computer based on a measurement of a sensor; and a plurality of the sensors each provided to a component of the hardware, for measuring a status quantity of the component. The failure symptom detection unit comprises: a failure symptom determination processing unit for obtaining, from a characteristic information for each application, an estimation of the status quantity of the each component, which corresponds to current load information, obtaining a current status quantity as a current value for the each component, and determining, when an absolute value of a difference between the estimation and the current value is equal to or more than a permissible error, that the symptom of the failure is present.

Abstract: The memory access capabilities of a host processor are used to facilitate the movement of instructions and data to an application-specific component having direct access to memory. Although the component executes code absent direct host processor control, the code may be uniquely tailored to the component's architecture. According to one embodiment, a flow of instructions requested by a host processor from a memory device is monitored. The flow of instructions is routed to an application-specific component in response to identifying code embedded in the flow of instructions targeted for execution by the component. While the instruction flow is routed to the component, a sequence of instructions is directed to the host processor that maintains instruction execution flow in the host processor, e.g., no-op instructions. When the end of the application-specific code is detected, the instruction flow is re-routed to the host processor for execution.

Abstract: A system apparatus and method for emulating a computing device are provided. Operational parameters of a server may be obtained and provided to an emulating computing device. An emulating device may emulate the server. While being emulated, a server may operate in a reduced functionality mode. Emulation of a server may be transparent to client or other machines associated with an emulated server. Conditions requiring a termination of an emulation of a server may be detected. Upon detecting conditions requiring a termination of an emulation of a server, operational or other parameters may be provided to the server and the server may assume full, or other, operational mode. Other embodiments are described and claimed.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate on platforms built using commodity processors the proprietary hardware systems of powerful older computers. High performance is typically a key requirement for a system even when built using emulation software. In a hardware design many special cases and conditions which may cause exceptions are detected by logic operating in parallel with the instruction execution. In software these checks can cost extra cycles of processor time during emulation of each instruction and be a significant detriment to performance. Avoiding some of these checks by relying upon the underlying hardware checks of the host system and then using a signal handler and special software to recover from these signals is a way to improve the performance and simplify the coding of the software emulation system.

Abstract: The present invention relates to a circuit arrangement with which a communication that is subdivided into functional layers is processable by a first layer for a higher layer and/or by a higher layer for the first layer, the first layer being formed by a physical layer and the circuit arrangement featuring at least one port which allows a communication directly with a layer that is higher than the first layer without the communication previously having to pass through the first layer.

Abstract: The present invention provides a system and method for controlling a web browser session. A system for controlling a web browser session comprises an emulating engine for automatic control of a web browser session by processing a script. The system further comprises a controlling engine for receiving a plurality of scripts and managing the distribution of the scripts to several emulating engines. A method for controlling a web browser session comprises providing a controller for receiving a script comprising unique tags and managing the script, including assigning the script to an emulator. The emulator then processes the script.

Abstract: Problems can occur when a controller is limited in ownership to one process. To minimize these problems, phantom Units can be used that are direct replicas of actual Units. Thus, multiple processes can own a single controller—one process can own the actual Unit while another process owns the virtual controller. At an appropriate time, such as when the actual Unit is no longer owned, bindings with the phantom Unit can transfer to the actual Unit.

Abstract: Software managing long names in an application programming interface receives a request to perform a requested operation on one or more fields, the application comprising a first operation operable to perform the requested operation on at least one field type. The software determines whether the field type of any of the fields is incompatible with the first operation. If the field types of the one or more fields are compatible with the first operation, then the software performs the requested operation on the one or more fields using the first operation. If the software determines that the field type of at least one of the fields is incompatible with the first operation, then it converts the request into a call for a second operation operable to perform the requested operation on the one or more fields and performs the requested operation using the second operation.

Abstract: A simulation apparatus, including a first simulator assigning an operating cycle number, a second simulator assigning an operating cycle number, and a control portion for synchronously controlling the first simulator and the second simulator, the control portion causing communication between the first simulator and the second simulator so as to control control-information and synchronous-information of the first simulator and the second simulator, the control-information controlling operations of the first simulator and the second simulator, wherein the control portion sets up the operating cycle numbers of the first simulator and the second simulator at a first cycle value when a synchronous condition of the synchronous-information is established, the control portion sets up at least one of the operating cycle numbers of the first simulator and the second simulator at a second cycle value being larger than the first cycle value when the synchronous condition of the synchronous-information is not established.

Abstract: A method and apparatus for ambiguous-state support in virtual machine emulators executes a suspect application in a core emulation model for all versions, variations, or generations of a given computer system component and then branches at the point where ambiguous behavior is detected, i.e., at the occurrence/request/trigger of a version variable behavior by the suspect application. The state of the emulation up to the version variable behavior branch point is then copied, and each variable behavior branch is further emulated using variable specific emulation models and only from the point of ambiguity, i.e., from the point of variable behavior, forward.

Abstract: A two-level transformation scheme to enable a practical fast mesh-free method is disclosed. The first level transformation transforms the original chosen mesh-free shape function to a first transformed mesh-free shape function that preserves Kronecker delta properties. The first transformed mesh-free function allows the essential boundary conditions to be imposed directly. The second-level transformation scheme employs a low pass filter function served as a regularization process that filters out the higher-order terms in the monomial mesh-free approximation obtained from the first-level transformation scheme with desired consistency and completeness conditions. This integration scheme requires only a low-order integration rule comparing to the high order integration rule used in the traditional mesh-free methods. The present invention simplifies the boundary condition treatments and avoids the usage of high-order integration rule and therefore is more practical than the traditional mesh-free methods.

Abstract: Methods, media, and systems for detecting anomalous program executions are provided. In some embodiments, methods for detecting anomalous program executions are provided, comprising: executing at least a part of a program in an emulator; comparing a function call made in the emulator to a model of function calls for the at least a part of the program; and identifying the function call as anomalous based on the comparison. In some embodiments, methods for detecting anomalous program executions are provided, comprising: modifying a program to include indicators of program-level function calls being made during execution of the program; comparing at least one of the indicators of program-level function calls made in the emulator to a model of function calls for the at least a part of the program; and identifying a function call corresponding to the at least one of the indicators as anomalous based on the comparison.

Abstract: An emulation system and emulation method for a no longer available microcontroller, having a supplyable microcontroller and emulation software able to be run thereon, and having an interpreter, the emulation software forming a software layer between the hardware of the available microcontroller and an operating software of the no longer available microcontroller, and the software being adapted in such a way that the hardware of the available microcontroller in conjunction with the additional emulation software behaves like the hardware of the no longer available microcontroller, and the interpreter is adapted in order to represent address, code and data information of the operating software of the no longer available microcontroller to functionally equivalent address, code and data information of the available microcontroller.

Abstract: A method and system for emulating an Ethernet link over a Sonet path to provide link integrity is disclosed. The method generally includes receiving an error code at a local Ethernet port upon detection of a link failure at a remote Ethernet port. The error code is received over a Sonet path in a Sonet path overhead. If the error code is still present after a specified period of time, the local Ethernet port is disabled. Methods for providing link stability and link availability are also disclosed.

Abstract: An interaction system for enabling a user of information systems to interact with the information systems and a method of transmitting user queries from a speech, image or handwriting recognition system to the information systems.

Abstract: A method and apparatus for storing a function specification file is described. In an exemplary method, the function specification field is capable for providing other software to facilitate execution of an application in a second operating system with the presence of a first operating system and the application is compiled for the first operating system. In another exemplary method, a preprocessor receives the function specification file comprising function definition data for a library function. The preprocessor processes the function definition data to generate header information and function code for the function. In another exemplary method, the preprocessor generates an automatic logging framework for the interposing library based on the function definition data. Further, a function in an interposing library logs calls to a corresponding library function.

Abstract: The present invention includes a system for simulating the performing of data storage operations. The system may include a storage manager component, at least one media management component directed by the storage manager component to manage storage operations to at least one storage device, and a storage emulation module adapted to simulate the characteristics of the at least one storage device. Under the direction of the storage manager, the emulation module may be adapted to simulate storage operations to one or more storage devices performed by one or more of the media management components.

Abstract: A device translates a script command related to teletype (TTY) communications in a network, and generates or receives a TTY signal based on the translated script to test the network.

Abstract: An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner apparatus. An LSI has a plurality of interfaces (IFs) for transmission/reception of data with an external device, and the LSI includes an emulation control unit for allowing one of the two of the plurality of IFs to perform an operation of emulating an IF of a connection partner device having operation specifications different from those of the LSI, when two IFs are connected to each other via a transmission line.

Abstract: Computer programs are preprocessed to produce normalized or standard versions to remove obfuscation that might prevent the detection of embedded malware through comparison with standard malware signatures. The normalization process can provide an unpacking of compressed or encrypted malware, a reordering of the malware into a standard form, and the detection and removal of semantically identified nonfunctional code added to disguise the malware.

Abstract: Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as HDD, DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane.