Abstract: A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out buffers. If a timing trace data first-in-first-out buffer is empty, timing trace data packet is transmitted. If a program counter overall data first-in-first-out buffer is not empty and the processor is at a data interruptible boundary, a program counter data packet is transmitted. If data first-in-first-out buffer is not empty, a data packet is transmitted. The program counter data packets include program counter sync data, program counter exception data, program counter relative branch data and program counter absolute branch data.

Abstract: A method and apparatus for provisioning a third party mobile device emulator from desktop provisioning software, the method having the steps of: designating a common file space between the third party mobile device emulator and the desktop provisioning software; writing files to the common file space from one of the third party mobile device emulator and the desktop provisioning software; and reading the files from the other of the third party mobile device emulator and the desktop provisioning software.

Abstract: Embodiments of the invention provide techniques for selecting rule engines for processing abstract rules based on functionality and cost. In general, an abstract rule is analyzed to determine which functions are required to process the rule. The abstract rule is assigned to a rule engine by evaluating metadata describing the functions and costs of the rule engines. The abstract rule is then translated to the format required by the selected rule engine.

Abstract: A system and method are disclosed for communicating in a programmable core. The programmable core is within a single integrated circuit and is divided into multiple independent sub-cores. The sub-cores are coupled together using a multiplexer based network. In another aspect, the multiplexer-based network includes multiplexers associated with some of the sub-cores for sending data and demultiplexers associated with other sub-cores for receiving data. In yet another aspect, a clock is included in the multiplexer-based network for synchronizing communication between the multiplexers and demultiplexers.

Abstract: A key which is a peripheral device which can directly connect to a host and stores multiple passwords and associated access data. The peripheral device includes an interface to a port of the host for establishing a connection. The peripheral device includes a processor and memory for storing the passwords and a program for both communicating with the host through the port, and for accessing the passwords and associated access data. Unlike the prior art, the present invention does not require the user to have a smart card reader or other token reader in order to access the passwords. In one aspect of the invention, the peripheral device incorporates a form of artificial intelligence to observe and later emulate a user's initial logon to a site. The software not only will recognize the site by storing characteristics of it, but will be able to automatically adapt to variations, if the login page is subsequently modified.

Abstract: An exemplary flexible network simulator and related methods test the ability of electronic devices to communicate with each other on a network, especially in real-time. The flexible network simulator can establish different connectivity protocols between multiple electronic devices and test the electronic devices using customized sets of network conditions.

Abstract: Method and apparatus for controlling power in an emulation system are described. In one example, a first interface is configured to receive requirement information for a logic module to be emulated from a host computer system. The requirement information includes at least one of a power requirement or a thermal requirement. A second interface is configured to receive measurement data from sensors in the emulation system. A controller is configured to control at least one of a synchronization system, a power regulation system, or a thermal system in the emulation system in response to the requirement information and the measurement data to reduce power load of the emulation system.

Abstract: An assurance system for evaluating a target application environment using a mixed environment including a virtual environment and the target environment. The assurance system emulates and evaluates the target environment. Information such as network configuration, interface information, and software packages or subsystems are imported into the virtual application environment. The assurance system may be used for purposes of testing, and delivering comprehensive reports of the likely results on the target system based on a comparison of the virtual application environment to the target environment, including such things as configuration changes to the environment, environment load and stress conditions, environment security, software installation to the environment, and environment performance levels among other things.

Abstract: A network device to maintain resource management within a network may comprise an emulator or watchdog that may send an emulation request to a resource manager for emulating a request of a client. Operability of the resource manager may be identified based on a reply of the resource manager to the emulation request. If the resource manager does not provide a response within a given time frame, then the watchdog may identify a failure condition for the resource manager. The watchdog may then initiate corrective actions for replacing the resource manager with a backup server responsive to identifying the fail condition.

Abstract: Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network on latch boundaries. Thus, management aspects of the simulation, such as management associated with the global simulation time, are simplified.

Abstract: Mechanisms are disclosed that allow for platform abstraction of a computing platform using a programming framework. The programming framework allows application programs to interact with different platforms in an identical manner by abstracting the platform. The application uses identical instructions to the programming framework across different platforms, with the programming framework modifying the instructions to fit platform specific requirements. The programming framework also emulates platform specific expected application behavior on behalf of the application. The programming framework may also provide an additional layer of security for the platform, limiting the access of the application program.

Abstract: Arrangement for bidirectionally transmitting information between a unit configured to emulate a data processing system and a data processing unit, wherein the data processing unit has a data input device and a data output device, the emulating unit is configured to generate emulator information, and the emulator information relates to a power budget for the emulated data processing system.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: A system of automated creation of a software interface between an operator and electronic device functional cores arranged in a target platform. The system includes a designing module comprising a designing window, wherein there are arranged interface visual elements corresponding to control members of the platform and a state machine wherein elements are functionally connected; a validation module for testing whether data issued from the designing module match the properties of the functional cores; and a simulation module of the target platform comprising a translation unit converting data issued from the validation module and transmitting them to a managing member of the target platform in order to simulate said functional cores by means of the control members.

Abstract: A network emulator provides both per-connection and non-connection-based emulation. The emulator includes a host computer, and a kernel-mode emulator driver and user-mode application component running on the host computer. The application component supplies configuration parameters to the driver. The driver includes a packet filter list that filters a captured packet, a virtual network link that receives the packet from the packet filter list, a link group list that applies an emulation procedure to the packet, a timer management component that manages a timer associated with the emulation procedure, and a packet dispatcher component that sends out the packet. A connection pool component facilitates per-connection emulation.

Abstract: A method for checking page size dependency including generating an interposing library comprising a first modified interface, wherein the first modified interface is dependent on a native page size, intercepting a call into a kernel by the interposing library, wherein the call is dependent on a non-native page size, modifying the call using the first modified interface to obtain a modified call, and generating a response to the modified call by the kernel using the native page size.

Abstract: An article of manufacture, method and system are provided for facilitating input/output (I/O) processing of at least one guest processing system. The article of manufacture includes at least one computer-usable medium having computer-readable program code logic to facilitate the I/O processing of the at least one guest processing system. The computer-readable program code logic when executing performing the following: emulating on a native system an I/O architecture for the at least one guest processing system, the emulating including: providing multiple device managers for a plurality of I/O devices of the I/O architecture; providing at least one communications adapter process interfacing the multiple device managers to the at least one network driver process; and wherein the multiple device managers translate I/O messages in at least one guest processing system format to messages in native system format for processing by the at least one communications adapter process, thereby facilitating I/O processing.

Abstract: A data backup system is provided that when coupled to a data source, such as a personal computer, and a media player, such an Apple Computer iPod, the data backup system blocks certain communications between the data source and the media player thus preventing the data source from recognizing the media player as such thereby avoiding the launching of synchronization software for the media player, the data backup system also causing the automatic launching of a backup application stored on the data backup system so that data files can be located on the data source and then backed up to the media player.

Abstract: A virtual universal serial port interface (“USI”) and a virtual storage device interface (“VSI”) interfacing with a host system and a remote console over a network link is provided. The USI includes a control register that receives control information from a processor and a legacy control register; and a status register that receives information from a legacy control register and based on that information, the processor formats information stored in a buffer destined for transmission over a serial port. The VSI includes, a first register that receives control information from a third register that stores control information sent by a processor used to update a fourth register that notifies the host system.

Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e.

Abstract: A system for interfacing hardware emulation to software simulation environments may include a simulation node configured to simulate a first portion of a system under test and a hardware emulation node configured to emulate a second portion of the system under test. The hardware emulation node may also be configured to exchange simulation information (such as representations of signal values obtained as output from the emulated portion of the system under test) with the simulation node. The hardware emulation node may contain a field programmable gate array devices (FPGA) configured to perform the hardware emulation. The FPGA may be mounted on an expansion board, such as a PCI (Peripheral Component Interconnect) board.

Abstract: A method for designing an integrated circuit having analog and digital circuit portions is disclosed. The method involves providing an emulation circuit, which preferably comprises a number of gates equivalent to a number of gates in the digital circuit portion, affixing the emulation circuit on a test substrate together with a version of the analog circuit portion having at least some of the defined functions of the analog circuit portion, and then testing the analog circuit version.

Abstract: Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.

Abstract: The present invention pertains to the field of electronic design automation (EDA). More particularly, this invention relates to using coherent state among multiple simulation models within an EDA simulation environment. Two related inventions are described. One invention selectively activates certain simulation domains in an electronic design automation (EDA) simulation environment at various times during the simulation of a circuit design and maintains timing synchronization among the various domains. The other invention makes state information accessible to simulation models in an EDA simulation environment without the necessity of simulating data transfers in the simulated circuit design. In various embodiments, the inventions increase efficiency and versatility of a simulation environment.

Abstract: Methods, systems, and computer program products for modeling a secure production network are provided. A method includes generating a test network for emulating production operations, capturing and analyzing data traffic occurring over the secure production network and a non-secure production network, and determining data flow requirements for isolating the secure production network and the non-secure production network from the test network. The data flow requirements are determined from results of data traffic capture and analysis. The method also includes generating business log from the data flow requirements and applying the business logic to a firewall associated with the test network. The business logic permits transmission of a subset of secure production data to the test network and prevents receipt of incoming transmission at the secure production network.

Abstract: A method for emulating the functionality of VGA hardware, wherein the emulator program of the present invention maintains a set of tables that permits the emulator program to branch to a function customized for both the instruction and the operating mode of the VGA hardware. When the customized function has already been generated, the emulator will automatically dispatch directly into the customized function. If an instruction is executed at a time when the VGA operating mode has changed, the addresses of the customized functions are loaded from a second table. If a customized function is not present, a customized function is generated and the tables are updated to point to the addresses of the newly created customized function. As the VGA hardware is switching among operating modes, a customized function is not generated until such time when an actual instruction is executed for the VGA hardware.

Abstract: First input device data is captured from a first input device coupled to a computing device. At least a portion the first input device data is mapped to an action of a second input device, wherein the second input device is not coupled to the computing device. Second input device data associated with the second input device is generated based at least in part on the first input device data.

Abstract: Decryption keys used in decrypting encrypted configuration data for a programmable logic device are erased following decryption of encrypted configuration data. A self-erasing key memory delivers a decryption key to a programmable logic device and then automatically erases itself. The keys are then no longer available outside the programmable logic device.

Abstract: A hardware and software co-simulation method for non-blocking cache access mechanism verification is provided. The method is applied for cache access mechanism verification. First, at least one way buffer is added into the software modeling, then the hardware and software modeling are simulated. Wherein, the hardware modeling issues a trigger event for reading request when one ‘outstanding miss’ occurs. At this moment, the software modeling stores the data of the address to be accessed into a way buffer. When the hardware modeling obtains the data from the main memory, it issues a trigger event for reading completion, and causes for writing the data from the way buffer into the data memory of the software modeling. The verification result of the software simulation is compared with the verification result of the hardware simulation.

Abstract: A system and method for allowing user access to software applications, data storage and retrieval, and electronic mail and messaging services in a networked computing environment are provided. The need for software installation, upgrade, and version control, and the need for certain hardware upgrades are eliminated by providing software and data storage and retrieval to a user or to groups of users from a remote terminal server via a networked computing environment. Software applications, data and electronic mail and messaging services are stored, maintained and operated at a remote terminal server and are provided to the user over the Internet or over an intranet of an organization such as a company or educational institution. Data is stored and secured at a remote file server, and web operations are provided by a remote web server. The backend of the system, including the terminal servers, file servers and web servers is managed and secured by a domain controller.

Abstract: A method for presentation of functional coverage includes representing a set of attributes of a design under test as a multi-dimensional cross-product space, which includes events corresponding to combinations of values of the attributes to be tested, the events including legal and illegal events. At least one test is run on the design, and responsively to the at least one test, a first group of the legal events that were covered by the at least one test and a second group of the legal events that remain non-covered after the at least one test are identified. One or more of the illegal events are grouped with at least one of the first and second groups so as to present a simplified model of the coverage of the events in the cross-product space.

Abstract: This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.

Abstract: A device emulator configured to emulate an electronic device to test a computing device. The device emulator includes a plurality of read-write registers that are user configurable to include a set of read registers and a set of write registers, wherein the set of write registers are configured to receive a plurality of requests from the computing device, and wherein the set of read registers are configured to transfer one or more conditional responses of a plurality of conditional responses to the computing device based on the requests; a set of control logic configured to receive the requests from the set of write registers and transfer the conditional responses to the set of read registers; and a circuit device that includes the read-write registers and the set of control logic, wherein the circuit device is configured to operate the control logic to emulate the electronic device.

Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

Abstract: Serializing and deserializing circuits are provided on an emulator circuit board to group input and output signals of programmable logic devices for routing through a cross point switch. In one instance, the input and output signals of the programmable logic devices are time-multiplexed signals of virtual interconnections. The cross point switch can be configured for static or dynamically scheduled operations.

Abstract: A method and system for simulating computer networks and computer network components to test computer network security is disclosed. A user specifies a desired configuration of a simulated computer network by using a configuration manager. The user also defines all the network components within the simulated computer network by specifying whether a component should be provided in hardware or should be simulated via software. Upon receiving the above-mentioned information from the user, the configuration manager acquires the required hardware resources from a hardware inventory. The configuration manager utilizes an interface switch that connects the hardware in the hardware inventory to produce the desired network layout. Next, the specified configuration for each of the network components is pushed into the acquired hardware resources. Computer network components to be simulated with software are subsequently initialized by the configuration manager.

Abstract: In order to avoid the need for upgrade software when enhancing the function of a digital product, e.g. PDA, and SD lookalike card or other removable device provided with an active function such as digital radio is able to create the appearance of a file structure relating to the radio functions so that the PDA can communicate with it in file system language.

Abstract: A method comprises displaying a model for an application program. The model includes an input interface, an output interface, and a plurality of variables. Addition of a new variable and placement of an annotation on the display unit for the new variable is detected. The annotation identifies the new variable as an individually definable object or an identification key. The identification key identifies an individual situation and the individually definable object copes with the individual situation. A new model with a new input interface and a new output interface is generated based, at least in part, on the annotation identifying the new variable as an individually definable object or an identification key.

Abstract: A method of copying virtual firmware smart card code from a first secured memory in a system and loading the virtual firmware smart card code into a second secured memory in the system so that the code may be run on a microprocessor to provide smart card services to the system.

Abstract: A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.

Abstract: A system and method are provided for accelerating development and debug of a printed circuit board (PCB) designed for use with a platform ASIC in advance of availability of a prototype sample of the platform ASIC. Aspects of the invention include a pin-out adapter card that implements a predefined pin-out of the ASIC and that hosts FPGA logic resources for emulating I/O functionality and some (or all) of the ASIC core logic; a PCB designed for use with the platform ASIC, wherein the PCB includes the predefined ASIC pin-out for eventually mating with the ASIC; and a socket having mating connectors on both sides for mating with the ASIC pin-out on the PCB and to the ASIC pin-out on the adapter card, respectively, for coupling the adapter card to the PCB, thereby enabling development and debug of the PCB prior to availability of ASIC samples.

Abstract: A system and method for computing dataflow in concurrent programs of a computer system, like device drivers which control computer hardware like disk drives, audio speakers, etc., includes, given a concurrent program that includes many similar components, initializing a set of reachable control states for interaction between concurrent programs. Based on the set of reachable control states, synchronization constructs are removed between the control states. The synchronization constructs are replaced with internal transitions. New reachable control states uncovered by the removal of the synchronization constructs are added where the new reachable control states are discovered using model checking for single threads. Data race freedom of the plurality of concurrent programs is verified by reviewing a complete set of reachable control states.

Abstract: A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.

Abstract: A method for emulating a logic circuit having at least one set of identical logic modules is disclosed. Each logic module in a set has logic elements and memory elements that store a module state of that logic module. The logic circuit is emulated by extracting a logic module from a set of identical logic modules, translating the extracted logic module for iterative representation of the module state of each of the logic modules with a single instance of the logic elements, and configuring a logic device with the translated logic module to emulate the logic circuit.

Abstract: An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buffer of the simulator to contain a desired input state for an emulation cycle. A target write to the interface is performed to indicate that the emulation cycle can proceed. The emulation cycle is completed using an instruction sequencer within the interface independent of the simulator.

Abstract: This invention is a system and method for simulating performance of one or more data storage systems. This invention may be used in many useful ways including for configuring or modeling a data storage environment, problem isolation, and general design.

Abstract: In a design system using virtual hardware models, a filtering manager for filtering execution results and determining which software instructions are candidates for restructuring. In some examples, illegal address range instructions are identified based on exception records and restructured software instructions may redirect memory access to an appropriate memory location thereby enabling the use of hardware device drivers in conjunction with hardware emulations, simulations or virtual models without requiring driver source code modifications. Using different filtering criteria, some or all legal and/or illegal memory access software instructions may be redirected to mapped memory locations enabling control over memory access functions. In some cases, debugging tools may be configured or altered to reduce, limit or disable exception handling trace messages, thereby improving overall processing performance by eliminating or reducing unnecessary or burdensome error or trace report generation.