Abstract: Multipurpose arithmetic functional units can perform planar attribute interpolation and unary function approximation operations. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x?xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for both classes of operations.

Abstract: An overall processing time to rasterize, at the first device, the electronic document to be rendered is computed. Also, a rendering time to render, at the first device, the electronic document to be rendered is computed. When the overall processing time to rasterize at the first device is greater than the rendering time to render at the first device, the electronic document to be rendered is parsed into a first document and sub-documents. A productivity capacity of each node is determined, the productivity capacity being a measured of the processing power of the node and the communication cost of exchanging information between the first device and the node. A sub-document is rasterized at a node when a productivity capacity of the node reduces the processing time to rasterize the electronic document to be rendered to be less than the computed overall processing time.

Abstract: A discrete time signal resampling circuit (200). A data sample processing module (260) removes selected samples from a sequential plurality of discrete time signal samples to implement fractional resampling where the data sample processing module stores fewer samples than the number of samples between samples to be removed. A coefficient generator (240) in the resampling circuit generates a sequence of finite impulse response filter coefficients, with each coefficient in the sequence being associated with a respective distinct portion of a plurality of discrete time signal samples. A coefficient multiplier (264) multiplies each of the sequential plurality of finite impulse response filter coefficients by its associated respective distinct portion of the plurality of discrete time signal samples. An adder (236) produces a resampled output sample that consists of a sum of elements of the product vector produced by the coefficient multiplier.

Abstract: A filter circuit includes: an adder/subtractor that performs at least addition; and a shifter that performs multiplication/division by a power of two through a shift operation. The adder/subtractors and the shifter are configured to obtain a first calculation result representing a pixel value of a target pixel included in image data multiplied by a first filter coefficient. At least the adder/subtractors and the shifter is configured to obtain a second calculation result representing pixel values of a plurality of peripheral pixels adjacent to the target pixel, with each of the pixel values being multiplied by a second filter coefficient. The adder/subtractor is configured obtain a third calculation result by adding the first and second calculation results. The shifter configured to divide the third calculation result by a power of two which is equivalent to a sum of the first and second filter coefficients, so as to output the division result.

Abstract: An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word.

Abstract: An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these blocks with the help of dedicated DSP lines is provided, which leads to a very simple and proficient implementation of n-stage MAC operations.

Abstract: A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.

Abstract: A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells. Each LUT logic cell is configured to receive three operand signals at three inputs of that LUT logic cell and to output two signals at two outputs of that LUT logic cell that are a sum and carry signal resulting from adding the operand signals. LAB internal routing logic couples the LUT logic cells such that the LUT logic cells collectively process the input signals to generate the output signals. The LAB internal routing logic is not part of the PLD routing architecture. By employing compressor LUT logic cells within the LAB, use of PLD routing architecture is minimized, and use of PLD resources is more efficient.

Abstract: The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of netlists generated by Boolean algebra to combinatorial geometry of CPLD architecture by reaggregating IP core elements and (d) used to effect continuous recalibration of IP cores with evolvable hardware in indeterministic environments for co-evolutionary reprogrammability.

Abstract: A configurable arithmetic block for implementing arithmetic functions in a device having programmable logic is described. The configurable arithmetic block comprises a first plurality of registers coupled to receive input data; a second plurality of registers coupled to receive input data; an arithmetic function circuit having a plurality of arithmetic function elements, each arithmetic function element coupled to at least one other arithmetic function element of the plurality of arithmetic function elements and coupled to receive outputs of at least one of the first plurality of input registers and the second plurality of input registers; and an output coupled to the arithmetic function circuit. A method of implementing a configurable arithmetic block in a device having programmable logic is also disclosed.

Abstract: A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers.

Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

Abstract: An embodiment of the invention provides a method of operating a Galois field multiplier in a processor. An n bit multiplier and an n bit multiplicand are received during a first group of one or more clock cycles. An (2n?1) bit product is calculated based on the n bit multiplicand and the n bit multiplier. The (2n?1) bit product is stored in a first memory element during the first group of one or more clock cycles. An n bit polynomial value is received during a second group of one or more clock cycles. During the second group of one or more clock cycles, the (2n?1) bit product is divided by the n bit polynomial value producing an n bit result. The n bit result is stored in a second memory element during the second group of one or more clock cycles.

Abstract: Provided is a programmable matrix element or “PME” (which may be part of an ASIC central processing unit) operable to manipulate a data set of real and complex numbers derived from an input signal. Specific operations may include: addition, subtraction, multiplication, accumulation, storage and scaling. Each PME includes a plurality of multi-stage signal processing modules, which may be two-staged modules. Each state, in turn, includes: at least one data manipulation module for manipulating the input signal; a crosspoint switch for facilitating the receipt and parallel distribution of an input signal/manipulated output signal; and a programmable control module operable to support data manipulation by controlling manipulation functions, storing data and routing signals. A given crosspoint switch may be programmed to interconnect data manipulation modules in “datapipe” fashion, which is to say via a specified number of parallel data pathways.

Abstract: A method for masking several identical functional processes manipulating digital data, including dividing the functional processes into steps at the end of each of which the process can be interrupted with the storage of at least one intermediary result, and successively executing the steps of at least two processes and selecting, at each step end, the process of the next step according to the result of a non-deterministic drawing of a number.

Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

Abstract: A reconfigurable circuit is provided, which includes a first arithmetic unit that performs addition or subtraction of a first input data and a second input data and outputs output data, and a first selector that selects an output data of the first arithmetic unit or a third input data and outputs the selected one as the first input data to the first arithmetic unit.

Abstract: In a determination as to similarity on parts of a piece of data, high-speed processing is performed without the need for a database. Division signal lines (L1 to Lk) that transmit signals corresponding to division data are used.

Abstract: An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(?1k), (?2k), (?3k), . . . } falls within a maximum period (2m-1), the group being produced as an element (?k) obtained by raising a root ? of a polynomial to a specified power value k (k?2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (?k) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (?k), the gate supplies the multiplication result as feedback bit data to the respective registers.

Abstract: A parallel residue arithmetic operation unit is provided to make it possible to reduce processing delay, and to make an additional multiplier or a residue arithmetic circuit unnecessary, so that a circuit can become small in size. In the parallel residue arithmetic operation unit, a parallel CRC calculation circuit (100) is comprised of input terminals (101)-(104) to which input data are divided into a plurality of sub-blocks and the sub-blocks are input in parallel, an initial value generating unit (110) for generating a part CRC corresponding to the forefront of each sub-block as an initial value, a part CRC generating unit (111)-(114) for receiving the part CRC corresponding to the forefront of each sub-block as the initial value and sequentially generating a residue part CRC in accordance with a recurrent equation, AND units (121)-(124) for calculating logical multiplications of part CRC values, and a cumulative adding unit (130) for cumulatively adding values output from the AND units (121)-(124).

Abstract: A look-up table which is required during looking up table for data transferring and a method for looking up table are provided. The method reduces the size of the look-up table used in the method for looking up table by simplifying the calculations. A reasonable error range is obtained for the required look-up table by adjusting appropriate modifiers. The method can be applied in the method for looking up table similar to the Q ? ( x ) = x B A calculation in the digital signal coder/decoder (CODEC), where both A and B are integers, and the calculation is more efficient if B/A is close to 1 or smaller than 1.

Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions on a set of inputs. The IC also includes several input select interconnect circuits for selecting the input set supplied to each configurable logic circuit. Each input select interconnect circuit is associated with a particular configurable logic circuit. When a configurable logic circuit is used to perform a multiplication operation, at least one of its associated input select interconnect circuits performs a logic operation that implements part of the multiplication operation.

Abstract: There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a crossbar switch (810), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.

Abstract: In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.

Abstract: A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the FIR mode, one real output is generated. The hardware accelerator may switch from FFT mode to FIR mode using three multiplexers. All FIR components may be utilized in FFT mode. Registers may be added to provide pipelining support. The hardware accelerator may support multiple numerical-representation systems.

Abstract: A method of computing arithmetic operations more efficiently than the conventional Arithmetic Logic Unit (ALU) is disclosed. By encoding both operands from Binary Coded Decimal (BCD) codes (0000, to 1001) into decimal digits (0 to 9), inputting them in the GerTh's™ look-up tables, which are made of an array of AND gates, the invention finds the answer more efficiently. This method finds the result in fewer steps than a traditional ALU by reducing the repetitive calculation steps and logic gates required. And this new method makes the unsolvable computerized binary floating-point multiplications and divisions back to the solvable GerTh's computerized decimal digits' (0-9) elementary arithmetic operations.

Abstract: A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format.

Abstract: An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving word conditioning operations from the critical path to the write datapath, the throughput of common DSP functional blocks such as multiplier-accumulator (MAC) blocks may be improved. Delays may be further reduced by combining analysis operations with write or move operations.

Abstract: Systems and methods are disclosed for deciding a satisfiability problem with linear and non-linear operations by: encoding non-linear integer operations into encoded linear operations with Boolean constraints by Booleaning and linearizing, combining the linear and encoded linear operations into a formula, solving the satisifiability of the formula using a solver, wherein the encoding and solving includes at least one of following: a. Booleanizing one of the non-linear operands by bit-wise structural decomposition b. Linearizing a non-linear operator by selectively choosing one of the operands for Booleanization c. Solving using an incremental lazy bounding refinement (LBR) procedure without re-encoding formula, and verifying the linear and non-linear operations in a computer software.

Abstract: A semiconductor device includes a configuration memory for storing configuration data, an arithmetic unit whose circuit configuration can be reconfigured in accordance with the configuration data, and a fixed value memory for storing fixed value data to be supplied to the arithmetic unit. Since the configuration data and fixed value data to be supplied to the arithmetic unit are stored in the different memories, no data area for storing the fixed value data need be set in the configuration memory. This makes it possible to supply a predetermined fixed value to the arithmetic unit by storing only information for reading out fixed value data from the fixed value memory.

Abstract: A dynamically reconfigurable processor is provided having a wiring structure which enables flexible mapping of a program to the processor with a small wiring area. A first wire permits a first arrangement of circuit blocks and a second wire provided for changing the arrangement order of the circuit blocks. A switch is provided to switch between the first wire and the second wire. By virtue of this arrangement, a greater variety of calculations can be performed in the circuit without the necessity for increasing the number of operation blocks.

Abstract: An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m?r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k1, k2, . . . , kr; a first arithmetic operation for performing polynomial multiplication on the (m?r) pieces of first blocks, and outputting r pieces of bit sequences having a length n; and a second arithmetic operation for performing a polynomial division and a polynomial multiplication on the r pieces of second blocks and r pieces of operation results of the first arithmetic operation, and outputting a bit sequence including redundant bit sequences having respective lengths n?k1, n?k2, . . . , n?kr.

Abstract: The disclosed invention is a technology for configuring a programmable logic device to perform a computation using carry chains. A computation having multiple input values can be decomposed into sub-computations that have a few input values each. The sub-computations may be organized into a tree topology that includes a chain of sub-computations. The chain of sub-computations can be associated with a carry chain in the programmable logic device. Logic elements in the carry chain can be configured to perform the sub-computations using the carry chain logic in the logic elements.

Abstract: In general terms, the invention provides a finite field engine and methods for operating on elements in a finite field. The finite field engine provides finite field sub-engines suitable for any finite field size requiring a fixed number of machine words. The engine reuses these engines, along with some general purpose component or specific component providing modular reduction associated with the exact reduction (polynomial or prime) of a specific finite field. The engine has wordsized suitable code capable of adding, subtracting, multiplying, squaring, or inverting finite field elements, as long as the elements are representable in no more than the given number of words. The wordsized code produces unreduced values. Specific reduction is then applied to the unreduced value, as is suitable for the specific finite field. In this way, fast engines can be produced for many specific finite fields, without duplicating the bulk of the engine instructions (program).

Abstract: Parallel hardware computation structures for integrated-circuit arithmetic and statistical signal averaging are described herein as an invention that is applicable to broad systems applications where a variety of analog-to-digital and digital-to-analog data interfaces occur. Signal values are improved to accommodate signal reconstruction of high quality and at high frequencies. The computation efficiency of the parallel hardware structures makes them useful in a broad set of applications where signal data is being converted from one electronics domain to another—in particular, from the analog domain to the digital domain and the reverse. Important application areas include video processing, music studios, telecommunications, voice communication and support systems, and information technology in general.

Abstract: An arithmetic and logic unit carries out arithmetic or logic operations on long operands. The unit comprises: an operation unit having a processing location, and configured for carrying out processing on bits at the processing location, the processing comprising any of a plurality of pre-defined arithmetic or logical operations, the processes being defined for a first number of bits determined by the operand word length; a fetch and write unit comprising direct memory access circuitry for fetching a second number of bits of operand data by direct access from an external memory and for writing results to memory, the second number being set by a predetermined memory access width; the second number being smaller than said operand word length, and the direct memory access circuitry being configured to deliver said second number of bits directly to the processing location without aggregation prior to processing.

Abstract: The present invention relates to a multiply apparatus and a method for multiplying a first operand consisting of na bits and a second operand consisting of nx bits. In one embodiment the multiply apparatus comprising a CSA (CSA) unit with nx rows each comprising na AND gates for calculating a single bit product of two single bit input values and adder cells for adding results of a preceding row to a following row and a last output row for outputting a carry vector and a sum vector, and logic circuitry for selectively inverting the single bit products at the most significant position of the nx?1 first rows and at the na?1 least significant positions of the output row in response to a first configuration signal before inputting the selectively inverted single bit products to respective adder cells for switching the CSA unit selectively between processing of signed two's complement operands and unsigned operands in response to the first configuration signal.

Abstract: A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to generate an invert control signal output. The first and second circuits receive the three-bit block as an input and generate their respective outputs based on the setting of each of the bits. The third circuit receives only the most significant bit of the three-bit block as its input and generates an invert signal output based on the setting of the most significant bit. In each of these circuits, the number of complex gates and transistors is minimized thereby reducing gate delay and power consumption in generating the control signals for performing a Booth multiplication operation.

Abstract: In a full-adder of complementary carry logic voltage compensation, two input terminals of a first multiplexer are connected to a carry input and a carry inverted phase input respectively; an add signal is connected to a select signal; an input terminal of a first inverter is connected to an output signal of the first multiplexer. Two input terminals of a second multiplexer output an addend and a summand; an output signal of the first inverter is selected; an output terminal of the second multiplexer produces a carry signal; an input terminal of the second inverter is connected to an output signal of the second multiplexer for producing a carry inverted phase signal; two input terminals of a third multiplexer input the summand and carry inverted phase signal; an output signal of the first inverter is a select signal; and an output terminal of the third multiplexer produces a sum signal.

Abstract: Systems, methods and media for implementing logic in the arithmetic/logic unit of a processor are disclosed. More particularly, hardware is disclosed for computing logical operations with minimal hardware by organizing the execution unit such that the propagate and generate functions required for the adder can be used as a basis to implement the bitwise logical instructions. The result of these functions is computed before execution of the instruction by an execution macro in the arithmetic/logic unit.

Abstract: Various methods and systems for implementing Reed Solomon multiplication sections from exclusive-OR (XOR) logic are disclosed. For example, a system includes a Reed Solomon multiplication section, which includes XOR-based logic. The XOR-based logic includes an input, an output, and one or more XOR gates. A symbol X is received at the input of the XOR-based logic. The one or more XOR gates are coupled to generate a product of a power of ? and X at the output, wherein ? is a root of a primitive polynomial of a Reed Solomon code. Such a Reed Solomon multiplication section, which can include one or more multipliers implemented using XOR-based logic, can be included in a Reed Solomon encoder or decoder.

Abstract: A dedicated processing module includes an input for data to be processed and an output for processed data. A block input and a block output are also included. A processing component for the module performs a digital processing operation on the data present at the data input and applies the processed data at the data output. The processor may further generate a block request. A control device within the module reproduces, at the block output, a block request applied to the block input or generated by the processing component. The control device thus may operate to block the application of processed data at the data output upon receipt of a block request at the block input. Two or more dedicated processing modules may be connected in series with each other to form a processing flow chain with the data output of one module connected to the data input of a subsequent module. Additionally, the block output of the subsequent module is connected to the block input of the preceding module.

Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.

Abstract: An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A[N?1:0] and a second N-bit vector B[N?1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N?1:0] & ˜B[N?1:0]) operation using A[N?1:0] and ˜B[N?1:0]. Further, a fourth N-bit vector is obtained by performing a bit-wise XOR (A[N?1:0]?˜B[N?1:0]) operation using A[N?1:0] and ˜B[N?1:0]. The difference between the first N-bit vector A[N?1:0] and the second N-bit vector B[N?1:0] is then declared as equal to a given number or to be within a given range of two numbers (+m and +n, m<n) based on bit patterns in the third N-bit vector and the fourth N-bit vector.

Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

Abstract: In this invention we describe a new type of computer—infinity computer—that is able to operate with infinite, infinitesimal, and finite numbers in such a way that it becomes possible to execute the usual arithmetical operations with all of them. For the new computer it is shown how the memory for storage of these members is organized and how the new arithmetic logic unit (NALU) executing arithmetical operations with them works.

Abstract: An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical operation, under the control of a control unit. By configuring the auxiliary computing units along the data path, additional processing to the operands could be carried out within the same instruction cycle. As such, a processing unit incorporating such an arithmetic and logic device is able to achieve significant performance improvement both in terms of code size and memory access overhead.