Abstract: An embodiment of a data pattern analysis optimizer includes a time sequence data memory, an estimator, a grouping unit, and a time sequence pattern extractor. The time sequence data memory stores a plurality of time sequence data made from items in time order. The estimator estimates the upper limit of the total number of types of time sequence patterns present in the time sequence data at a rate higher than a minimum support level, based on a respective rate of presence of each item, wherein each of the time sequence patterns present in the time sequence data is a predefined number of items. In case that the estimated upper limit exceeds an upper limit of the number of types of time sequence patterns as a maximum processing load to a computer, the grouping unit groups a plurality of time sequence data into sub-groups, based on a group of items having the increased number of items and gives the estimator instructions to perform estimation.

Abstract: A multi-level memory cell NAND structure of a memory device is utilized to extract uniqueness from the memory device. Certain unreliable characteristics of a NAND-based storage are used to generate a true random number sequence. A method for generating such sequence is based on a physically unclonable function (PUF) which is implemented by extracting unique characteristics of a NAND-based memory device using existing firmware procedures.

Abstract: Systems and methods for increasing security in a computer system are provided. The system includes one or more logic circuits. The one or more logic circuits receive a plurality of independent first entropy values from a hardware source, apply at least some of the plurality of independent first entropy values to a function to generate a second entropy value, and seed a pseudorandom number generator with the second entropy value. The one or more logic circuits also generate a random number using the pseudorandom number generator seeded with the second entropy value and may produce a block of ciphertext or message authentication code using the random number, or otherwise use the generated numbers as secure random numbers in applications such as cryptographic protocols.

Abstract: Embodiments of systems and methods for a multi-source true random number generator (TRNG) are disclosed. A set of values is generated from each of the sources of randomness and an extractor is applied each of the set of values to produce a set of random values from each source. At least one extractor for at least one of the sources is a multi-radix extractor. The sets of values generated from each source of randomness can be composited to generate a random bitstring as the output of the TRNG.

Abstract: A method, apparatus, and computer program product for improved pseudo-random number generation are provided. An example method includes receiving, by a computing device, a request for a pseudo-random number, selecting, by extraction circuitry of the computing device, a first parameter from a server parameter dataset, and obtaining a first value for the first parameter. The method further includes selecting, by the extraction circuitry, a second parameter, and obtaining a second value for the second parameter. The method includes generating, by transformation circuitry, the pseudo-random number based on the first value and the second value.

Abstract: Methods for modifying power use of a semiconductor device include receiving, at one or more processors, an activity stream of a simulation of a semiconductor device, the activity stream comprising a stream of signals. Using the one or more processors, integrated circuit actions are recognized from the activity stream, each integrated circuit action representing an abstraction of work done by the semiconductor device. The processor(s) determine one or more values associated with the integrated circuit actions. A model of power use is generated for the semiconductor device, the model based at least in part on the recognized integrated circuit actions and the associated values. Based on an output of the model, power use of the semiconductor device is modified. Other methods and systems related to determining, modeling, and predicting power/energy use of semiconductor devices are also disclosed.

Abstract: Systems, computer-implemented methods, and computer program products to facilitate updating, such as averaging and/or training, of one or more statistical sets are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can include a computing component that averages a statistical set, provided by the system, with an additional statistical set, that is compatible with the statistical set, to compute an averaged statistical set, where the additional statistical set is obtained from a selected additional system of a plurality of additional systems. The computer executable components also can include a selecting component that selects the selected additional system according to a randomization pattern.

Abstract: A random number generator, a random number generating circuit, and a random number generating method are provided. The random number generating circuit includes the random number generator and executes the random number generating method. The random number generator includes a shift register having N storage elements and a combinational logic circuit. The N storage elements receive a random seed in a static state and repetitively perform a bit shift operation in a plurality of clock cycles. The combinational logic circuit generates an output sequence based on the random seed and a random bitstream received from an external source.

Abstract: Provided are a random number generation device and the like capable of calculating a high precision random number using a memory capacity selected irrespective of the precision of the random number. A random number calculation device is configured to generate first random numbers based on given number and specify, for the given number of second random numbers in a target numeric extent, bin range depending on the first random numbers based on frequency information representing cumulative frequency regarding a frequency of numeric extent including respective second random numbers among given numeric extents, the numeric extent being determined in accordance with a desirable precision.

Abstract: A memory device that includes a memory array and a memory controller is introduced. The memory controller is configured to adjust a program strength of the program pulse according to the configurable ratio of the first bit value and the second bit value to generate an adjusted program pulse or to adjust a bias voltage pair according to the configurable ratio of the first bit value and the second bit value to generate an adjusted bias voltage pair. The memory controller is further configured to generate the random bit stream with the configurable ratio of the first bit value and the second bit value according to the data stored in the plurality of memory cells included in the memory array after applying the adjusted program pulse or according to the data stored in the plurality of memory cells after being biased by the adjusted bias voltage pair.

Abstract: A method for correcting spatially variable electron flux in a true random number generator (TRNG) is presented. The TRNG comprises a radioactive source and an array of detectors, and the method comprises: (a) segmenting the array of detectors into a plurality of groups; (b) for each group: (1) detecting via multiple detectors an electron signal from the decay of the radioactive source; (2) determining a number of detections based on the detection of step (b)(1); (3) determining a group median count based on the number of detections; (4) comparing the group median count to either (A) a detection count from a single detector within the group, or (B) a detection count from multiple detectors within the group; (5) based on the comparison, assigning a value to a string of values; and (c) determining a true random number based on the string of values. A TRNG implementing the method is also disclosed.

Abstract: A random number generator including: a first ring oscillator including a first inverter chain, the first inverter chain including a plurality of serially connected first inverters, the first ring oscillator configured to output a first random signal generated at a first sub-node between two neighboring first inverters among the plurality of first inverters; a second ring oscillator including a second inverter chain, the second inverter chain including a plurality of serially connected second inverters, the second ring oscillator configured to output a second random signal generated at a second sub-node between two neighboring second inverters among the plurality of second inverters; and a signal processing circuit for generating a random number by combining the first random signal with the second random signal.

Abstract: A random noise generator for generating a plurality of random noise samples per clock cycle, the noise samples having a distribution. The random noise generator comprises at least a first comparator unit and a second comparator unit, the first comparator unit configured to generate a first plurality of samples representing a high-probability part of the distribution and the second comparator unit configured to generate a second plurality of samples representing a low-probability part of the distribution; and a random selection unit connected to at least the first comparator unit and the second comparator unit. The random selection unit is configured to receive the first plurality of samples generated by the first comparator unit and the second plurality of samples generated by the second comparator unit, to output a random selection of samples from the first plurality of samples and the second plurality of samples.

Abstract: An integrated circuit chip includes a plurality of function blocks; a mode controller configured to convert an input signal, received from an external device through an input/output pin, into an input pattern and test mode setting data which include a plurality of bits, and to output the test mode setting data and a mode switching enable signal when a secure pattern generated therein is the same as the input pattern; and a mode setting module configured to control the plurality of function blocks to operate in a test mode according to the mode setting data, in response to the test mode switching enable signal.

Abstract: Disclosed herein is an apparatus for estimating randomness of a random number generator. The apparatus is configured to divide output data (302), generated by the random number generator (704), into blocks (310) of a length (L), estimate a Shannon entropy of a second sub-set (404) of the blocks (310), using a first sub-set (402) of the blocks (310) to initialize the estimating, solve an estimate function, that relates an argument parameter (?) to the Shannon entropy estimate, to determine a value for the argument parameter (?) that is indicative of a probability of a most probable block being generated by the random number generator (704) as a new block, and use the length (L) to tune an estimate of randomness of the random number generator (704) calculated based on the value for the argument parameter (?).

Abstract: A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.

Abstract: An apparatus includes a ring oscillator, a carry chain circuit, and a detector circuit. The ring oscillator produces a clock signal. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates the clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.

Abstract: A method is provided for preparing a plurality of distributed nodes to perform a protocol to establish a consensus on an order of received requests. The plurality of distributed nodes includes a plurality of active nodes, the plurality of active nodes including a primary node, each of the plurality of distributed nodes including a processor and computer readable media. The method includes preparing a set of random numbers, each being a share of an initial secret. Each share of the initial secret corresponds to one of the plurality of active nodes. The method further includes encrypting each respective share of the initial secret, binding the initial secret to a last counter value to provide a commitment and a signature for the last counter value, and generating shares of a second and of a plurality of subsequent additional secrets by iteratively applying a hash function to shares of each preceding secret.

Abstract: A system and method of generating a one-way function and thereby producing a random-value stream. Steps include: providing a plurality of memory cells addressed according to a domain value wherein any given domain value maps to all possible range values; generating a random domain value associated with one of the memory cells; reading a data value associated with the generated random domain value; generating dynamically enhanced data by providing an additional quantity of data; removing suspected non-random portions thereby creating source data; validating the source data according to a minimum randomness requirement, thereby creating a validated source data; and integrating the validated source data with the memory cell locations using a random edit process that is a masking, a displacement-in-time, a chaos engine, an XOR, an overwrite, an expand, a remove, a control plane, or an address plane module. The expand module inserts a noise chunk.

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.

Abstract: There may be provided a computer-implemented method. It may be implemented using a blockchain network such as, for example, the Bitcoin network.

Abstract: An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.

Abstract: Various embodiments relate to a method and system for securely comparing a first and second polynomial, including: selecting a first subset of coefficients of the first polynomial and a second subset of corresponding coefficients of the second polynomial, wherein the coefficients of the first polynomial are split into shares and the first and second polynomials have coefficients; subtracting the second subset of coefficients from one of the shares of the first subset of coefficients; reducing the number of elements in the first subset of coefficients to elements by combining groups of / elements together; generating a random number for each of the elements of the reduced subset of coefficients; summing the product of each of the elements of the reduced subset of coefficients with their respective random numbers; summing the shares of the sum of the products; and generating an output indicating that the first polynomial does not equal the second polynomial when the sum does not equal zero.

Abstract: An apparatus comprises a noisy bias voltage generator circuit, a random seed generator circuit, and a random series generator circuit. The noisy bias voltage generator circuit may be configured to generate a plurality of noisy bias voltages in response to a plurality of input voltage signals and a first bias current signal. The random seed generator circuit may be configured to generate a random seed in response to the plurality of noisy bias voltages and a second bias current signal. The random series generator circuit may be configured to generate a series of true random bits in response to the random seed and a clock signal.

Abstract: Systems and methods for integrated communication security are described. One aspect includes a clock generator configured to generate a clock signal at a first frequency, and a circuit utilizing the clock signal. The circuit may include a port configured to receive an encryption sequence at the first frequency, and a first unidirectional data path between the port and a memory configured to permit data transfer from the port to the memory. The memory may be configured to access the encryption sequence from the port via the first unidirectional data path and store the data. The circuit may further include a clock divider configured to divide the first frequency by a divisor deriving another clock signal at a second frequency, and an encryption/decryption module configured to read a portion of the encryption sequence from the memory, process input using the portion of the encryption sequence, and generate output responsive to the processing.

Abstract: A Physical Unclonable Function (PUF) based true random number generator (TRNG), a method for generating true random numbers, and an associated electronic device are provided. The PUF based TRNG may include a first obfuscation circuit, a cryptography circuit coupled to the first obfuscation circuit, and a second obfuscation circuit coupled to the cryptography circuit. The first obfuscation circuit obtains a first PUF value from a PUF pool of the electronic device, and performs a first obfuscation function on a preliminary seed based on the first PUF value to generate a final seed. The cryptography circuit utilizes the final seed as a key of a cryptography function to generate preliminary random numbers. The second obfuscation circuit obtains a second PUF value from the PUF pool, and performs a second obfuscation function on the preliminary random numbers based on the second PUF value to generate final random numbers.

Abstract: The disclosure provides a key generation method and apparatus. The key generation method comprises: encrypting a first key factor generated by a first device with an initial key, and sending the encrypted first key factor to a second device through a first secure channel, wherein the initial key is a key preset for the first device and the second device; receiving, through the first secure channel, a second key factor encrypted with the initial key, wherein the second key factor is generated by the second device; decrypting the second key factor encrypted with the initial key and received through the first secure channel, so as to obtain the second key factor; and generating a shared key between the first device and the second device according to the first key factor and the second key factor.

Abstract: An operation-side communication device that is operated by an operator and a machine-side communication device that is connected to an industrial machine mutually register each other as partners permitted to communicate with each other. A communication device receives a partner ID of a partner communication device intended to be registered as a partner. The communication device wirelessly transmits a signal including the partner ID to the partner communication device. The partner communication device determines whether the partner ID included in the received signal corresponds to the ID of the partner communication device itself, and if so, the communication device registers the partner ID as the ID of a permitted communication partner. The above operations are repeated with the communication device and the partner communication device interchanged.

Abstract: Embodiments of the disclosure provide a system for providing a true random number (TRN) or physically unclonable function (PUF), including: an array of voltage controlled magnetic anisotropy (VCMA) cells; a voltage pulse tuning circuit for generating and applying a stochastically tuned voltage pulse to the VCMA cells in the array of VCMA cells, wherein the stochastically tuned voltage pulse has a magnitude and duration that provides a 50%-50% switching distribution of the VCMA cells in the array of VCMA cells; and a bit output system for reading a state of each of the VCMA cells in the array of VCMA cells to provide a TRN or PUF.

Abstract: A method of performing division operations in an error correction code includes the steps of receiving an output ??F†{0} wherein F=GF(2r) is a Galois field of 2r elements, ?=?0?i?r?1?i×?i wherein ? is a fixed primitive element of F, and ?i?GF(2), wherein K=GF(2s) is a subfield of F, and {1, ?} is a basis of F in a linear subspace of K; choosing a primitive element ??K, wherein ?=?1+?×?2, ?1=?0?i?s?1 ?i×?i?K, ?2=?0?i?s?1 ?i+s×?i?K, and ?=[?0, . . . , ?r?1]T?GF(2)r; accessing a first table with ?1 to obtain ?3=?1?1, computing ?2×?3 in field K, accessing a second table with ?2=?3 to obtain (1+?×?2×?3)?1=?4+?×?5, wherein ??1=(?1×(1+?×?2×?3))?1=?3×(?4+?×?5)=?3×?4+?×?3×?5; and computing products ?3×?4 and ?3×?5 to obtain ??1=?0?i?s?1?i×?i+?·?i?i?s?1?i+s=?i where ?i?GF(2).

Abstract: A system and method for the analysis of log data is presented. The system uses SuperMinHash based locality sensitive hash signatures to describe the similarity between log lines. Signatures are created for incoming log lines and stored in signature indexes. Later similarity queries use those indexes to improve the query performance. The SuperMinHash algorithm uses a two staged approach to determine signature values, one stage uses a first random number to calculate the index of the signature value that is to update. The two staged approach improves the accuracy of the produced similarity estimation data for small sized signatures. The two staged approach may further be used to produce random numbers that are related, e.g. each created random number may be larger than its predecessors. This relation is used to optimize the algorithm by determining and terminating when further created random numbers have no influence on the created signature.

Abstract: Disclosed is a true random number generator and a method for generating a true random number. The true random number generator includes a sampling circuit and a random number generating circuit. The sampling circuit is configured to sample N voltage(s) of N capacitors according to a clock signal and thereby generate N sample value(s), in which the N is a positive integer. The random number generating circuit is configured to generate a random number according to at least a part of the N sample value(s).

Abstract: A controller is coupled to a non-volatile memory device and a host. The controller is configured to perform a cyclic redundancy check on map data associated with user data stored in the memory device, generate an encryption code based on a logical address included in the map data, generate encrypted data through a logical operation on the encryption code and the map data, and transmit the encrypted data to the host.

Abstract: A computer-implemented method for classification of an input element to an output class in a spiking neural network may be provided. The method comprises receiving an input data set comprising a plurality of elements, identifying a set of features and corresponding feature values for each element of the input data set, and associating each feature to a subset of spiking neurons of a set of input spiking neurons of the spiking neural network. Furthermore, the method comprises also generating, by the input spiking neurons, spikes at pseudo-random time instants depending on a value of the feature for a given input element, and classifying an element into a class depending on a distance measure value between output spiking patterns at output spiking neurons of the spiking neural network and a predefined target pattern related to the class.

Abstract: A system for verifying integrity of content of an integrated circuit's registers, the system being operative in conjunction with an integrated circuit including at least one memory, at least one processor, and a multiplicity of registers, the system comprising register content verification logic configured, when in a first mode aka “Study Mode”, to read at least some of the registers' content, to compute a first hash on the content, and to store the first hash thereby to provide an up-to-date reference hash, and, at least on occasion, when in a second mode aka “Verify Mode”, to compute at least one second hash on the content, to compare the second hash to the reference hash and, accordingly, to provide a content verification output (aka “fault detection” output) indicative of whether the reference and second hashes are equal.

Abstract: The exemplary embodiments of the present invention provide a quantum random number generation apparatus according to an exemplary embodiment of the present invention including: a space-division semiconductor detector including a plurality of cells, each individually absorbing a plurality of emission particles emitted from a radioactive isotope; and a signal processor that generates a random number based on an absorption event at which the plurality of emission particles are absorbed into the plurality of cells, and thus new type of random number conversion method that combines a spatial randomness and existing temporal randomness of the emission particle can be provided, there is no restriction generated due to the dead time, the random number generation rate can be remarkably increased, and it is possible to generate of a pure random number at high speed, which is required by a computer, a network processor, or an IoT device.

Abstract: A method of transmitting an On-Off Keying, OOK, signal which includes an ON waveform and an OFF waveform forming a pattern representing transmitted information. The method includes obtaining a basic baseband waveform; scrambling the basic baseband waveform by applying a first binary randomised sequence where one of the binary values cause transformation to a complex conjugate; modulating the information to be transmitted by applying the scrambled basic baseband waveform for the ON waveform and applying no waveform for the OFF waveform; and transmitting the modulated information.

Abstract: An execution unit configured to execute a computer program instruction to generate random numbers based on a predetermined probability distribution. The execution unit comprises a hardware pseudorandom number generator configured to generate at least randomised bit string on execution of the instruction and adding circuitry which is configured to receive a number of bit sequences of a predetermined bit length selected from the randomised bit string and to sum them to produce a result.

Abstract: A computer-implemented method for generating one or more random numbers includes configuring a mapper to feed inputs of a random number generation system using a subset of noise sources from multiple noise sources. The random number generation system generates a random number based on the inputs. The method further includes evaluating the subset of noise sources and detecting that a first noise source from the subset of noise sources has degraded in quality. The method further includes evaluating a second noise source from the available noise sources, the second noise source not being in the subset of noise sources. In response to the second noise source satisfying a predetermined threshold criterion, the first noise source is replaced with the second in the subset of noise sources for providing random bit streams to facilitate generating the random number by the random number generation system.

Abstract: An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. The IC includes a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address (wherein the memory address corresponds to a location in a memory block associated with the integrated circuit), and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal.

Abstract: A method, performed by a user application, of creating a trusted bond between a hearing device and the user application is disclosed, wherein the method comprises obtaining first authentication material; transmitting a first authentication request comprising a first authentication type identifier and first authentication data to the hearing device; receiving a first authentication response comprising a sound signal from the hearing device; deriving second authentication material based on the sound signal; determining second authentication data based on the second authentication material; transmitting a second authentication request comprising the second authentication data to the hearing device; receiving a second authentication response comprising an authentication key identifier from the hearing device; storing an authentication key and the authentication key identifier, wherein the authentication key is based on the first authentication material; and connecting the user application to the hearing device us

Abstract: A method of decomposing digital signals using non-negative matrix factorization by generating an initial set of values in a row in the weight matrix from a ratio of a first function of a first signal of a plurality of digital signals divided by a second function of at least two other signals of the plurality of the digital signals, wherein the row in the weight matrix determines a decomposition of the plurality of digital signals into signal components.

Abstract: Embodiments of the invention provide a computing device comprising one or more processors, each processor comprising one or more processing unit, said one or more processing units being configured to execute at least one program, each program comprising data and/or instructions, the computing device further comprising, for at least some of the processors, a processor cache associated with each processor, the processor cache being configured to access data and/or instructions comprised in the programs executed by the processor, the computing device comprising: an auxiliary cache configured to access metadata associated with the data and/or instructions comprised in said programs; a security verification unit configured to retrieve, from the auxiliary cache, at least a part of the metadata associated with data and/or instructions corresponding to a memory access request sent by a processor (11) to the processor cache (117).

Abstract: A photonic random signal generator includes an incoherent optical source configured to generate an optical noise signal, a filter configured to generate a filtered optical noise signal using the optical noise signal, a coupler, a photodetector, a filter, and a limiter. The coupler couples the filtered optical noise signal and a delayed version of the filtered optical noise signal to generate a first coupled signal and a second coupled signal. The photodetector generates an output signal representative of a phase difference between the filtered optical noise signal and the delayed version of the filtered optical noise signal using the first coupled signal and the second coupled signal. The filter filters the output signal representative of the phase difference to generate an analog random signal. The limiter thresholds the analog random signal based on a clock signal, to generate a digital random signal.

Abstract: The present disclosure provides a high-speed random number generation method and device, comprising an entropy source module and an entropy sampling module. The entropy source module is an autonomous Boolean network formed by digital logic gates, the network is formed by an XNOR gate and (N?1) XOR gates, wherein the value of N is equal to 3n (n is a positive integer), and the entropy source can generate chaotic signals having wide and flat frequency spectrum. The entropy sampling module of the present disclosure is formed by D flip flops used for sampling and quantizing the chaotic signals to generate random number sequences. The random number sequences generated by the present disclosure can pass test standards (NIST and Diehard statistic tests) of random number industry and have excellent random statistic characteristics.

Abstract: Multiple random numbers are generated. The multiple random numbers are N different random numbers. N is a positive integer. Generating the multiple random numbers includes generating a random number array including N storage units. The multiple random numbers are shuffled. A random number obtaining instruction is received. A random number is obtained from the multiple random numbers based on the random number obtaining instruction.

Abstract: A method of verifying randomness of a bitstream is disclosed. The method includes receiving a bitstream consisting of n consecutive bits and dividing the bitstream into a plurality of bit blocks. In this case, n is a natural number of two or greater, each of the bit blocks consists of m consecutive bits, and m is a natural number of two or greater and is smaller than n. Further, the method includes allocating the plurality of bit blocks to a plurality of core groups in a graphics processing unit (GPU), processing the allocated bit blocks in the plurality of core groups in parallel, calculating random number level values of the allocated bit blocks, and determining whether the bitstream has randomness based on the calculated random number level values. Each of the core groups includes a plurality of cores capable of performing identical or similar tasks without separate synchronization.

Abstract: A security test logic system can include a non-transitory memory configured to store measurements from a measurement apparatus, the measurement outputs comprising indications of presence or absence of coincidences where particles are detected at more than one detector at substantially the same time, the detectors being at the end of different channels from a particle source and having substantially the same length. The system can include a processor configured to compute a test statistic from the stored measurements. The test statistic may express a Bell inequality, and the system can compare the test statistic with a threshold. The processor can be configured to generate and output a certificate certifying that the measurements are from a quantum system if the value of the computed test statistic passes the threshold.

Abstract: Embodiments of a secure multi-party computation method applicable to any computing node deployed in a distributed network are provided. A plurality of computing nodes are deployed in the distributed network. The plurality of computing nodes jointly participate in a secure multi-party computation based on private data respectively held by the computing nodes. The method includes: generating a computing parameter related to private data held by one computing node based on a secure multi-party computation algorithm; transmitting the computing parameter to other computing nodes participating in the secure multi-party computation for the other computing nodes to perform the secure multi-party computation based on collected computing parameters transmitted by the computing nodes participating in the secure multi-party computation; and creating an audit log corresponding to the computing parameter, the audit log recording description information related to the computing parameter.

Abstract: A random number generator generates a random number by using at least two algorithms. A security device includes the random number generator. The random number generator includes a random seed generator and a post processor. The random seed generator is configured to receive an entropy signal and to generate a random seed of a digital region generated by using the entropy signal. The post processor is configured to generate a random number from the random seed by using a first algorithm and a second algorithm. A bias property represents unbiasedness of a result value, and a bias property of the first algorithm is different from a bias property of the second algorithm.