Abstract: An existing disk drive storage enclosure is converted into a standalone network storage system by removing one or more input/output (I/O) modules from the enclosure and installing in place thereof one or more server modules (“heads”), each implemented on a single circuit board. Each head contains the electronics, firmware and software along with built-in I/O connections to allow the disks in the enclosure to be used as a Network-Attached file Server (NAS) or a Storage Area Network (SAN) storage device. An end user can also remove the built-in head and replace it with a standard I/O module to convert the enclosure back into a standard disk drive storage enclosure. Two internal heads can communicate over a passive backplane in the enclosure to provide full cluster failover (CFO) capability.

Abstract: A system for synchronizing configuration information in a plurality of data processing devices using a common system interconnect bus. The present invention provides a method and apparatus for enforcing automatic updates to the configuration registers in various agents in the data processing system. A node controller is operably connected to a system interconnect bus and a switch. A plurality of interface agents are connected to the switch, with each of the interface agents comprising a configuration space register, a configuration space shadow register and a control and status register (CSR). A token ring connected to the node controller is operable to transmit data from the node controller to a plurality of interface agents connected to the token ring, thereby providing a system for updating the various configuration registers in each of the agents.

Abstract: In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU.

Abstract: A disk-array device includes an information managing database for acquiring link information among a server device, a switch device, and a storage device via the switch device so as to manage the link information in a combined manner, and a collection/analysis unit for retrieving and collecting desired combined information of the link information from the information managing database so as to analyze the desired combined information.

Abstract: A device control system is provided, in which a host device uploads optimal program code suitable for its own system environment from a target device for control. In the target device 2, a plurality of pieces of program code 231 through 23n used for different system environments and a header object 221 associated with the respective pieces of program code are stored in advance. The host device 1 obtains the header object 221 from the target device 2, and then parses the obtained header object 221 to determine program code 23x (x is one of 1 through n) optimal for its own system environment. The host device 1 then uploads the determined program code 23x from the target device 2 for interpretation, thereby controlling the target device 2.

Abstract: A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: A channel based network is provided that allows one or more hosts to communicate with one or more remote fabric attached I/O units. A split-model network driver includes a host module driver and I/O unit module driver. The host module driver and the I/O unit module driver each includes a messaging layer that allows the hosts and I/O units to communicate over the switched fabric using a push-push messaging protocol. For a host to send data, the host either initiates a RDMA write to a pre-registered buffer or initiates a message Send to a pre-posted buffer on the target. For the RDMA case, the initiator would have to send the target some form of transfer indication specifying where the data has been written. This notification can be done with either a separate message or more preferably with immediate data that is included with the RDMA write.

Abstract: Documents are processed collectively by multiple printing devices. A printing device receives a request to print a document, and partitions the document into one or more blocks. The printing device communicates, to each of one or more additional printing devices, at least one of the one or more blocks. The additional printing devices convert the portions they receive to a print-ready format, and return the portions in the print-ready format to the printing device. The printing device uses the portions in print-ready format received from the additional printing devices to print the document.

Abstract: Provided is a method, system, and program for sending notification to an Input/Output (I/O) device comprised of multiple components of an event from an originating device that transmits data to the I/O device. The originating device detects a notification event and generates a notification message in response to the detected notification event to transmit to the I/O device. In response to receiving the notification message, the I/O device activates at least one of the multiple components. The notification message may be transmitted to the I/O device on a first port at the I/O device, where data is received at a second port at the I/O device. In response to receiving the notification message on the first port, the I/O device activates at least one of the multiple components.

Abstract: Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

Abstract: A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device. Onset of the refresh procedure triggers diversion of shared signal paths away from the DRAM to the other device for the duration of the refresh the shared signal paths include at least some of the address and data signal paths.

Abstract: A low-level function which enforces logical partitioning establishes a set of virtual indicator lights for certain physical components, the virtual indicator lights being only data in memory, a separate set of virtual indicator lights corresponding to each respective partition. Processes running in a partition can switch and sense the virtual indicator lights corresponding to the partition, but have no direct capability to either switch or to sense the virtual lights of any other partition. The low-level enforcement function alone can switch the state of the physical indicator light, which is generally the logical OR of the virtual indicator lights of the different partitions.

Abstract: A host adapter uses a scatter/gather list that includes a plurality of sections. Each section of the scatter/gather list can have any desired size. A link element in one section of the scatter/gather list is used to link to another section in the list. The link element has a format that is the same as the data elements that represent data segments in the list. Each element in the scatter/gather list includes an end-of-list flag and an end-of-section flag. When the end-of-list flag is set, the host adapter knows that the end-of-the scatter/gather list has been reached. When the end-of-section flag is set, the host adapter knows that an address to another section of the scatter/gather list is available.

Abstract: A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Abstract: A method for supporting flow control by a SCSI initiator using a Packetized SCSI Protocol includes transmitting a data packet information unit in a Packetized SCSI Protocol Data Out phase. The SCSI initiator also receives a signal in said Packetized SCSI Protocol Data Out phase to indicate whether another data packet information unit is to be transmitted in said Packetized SCSI Protocol Data Out phase.

Abstract: A signal from a remote control is used to operate a device having a built-in communication port and a built-in microprocessor, even though the port does not normally recognize the signal. Specifically, even if the port flags an error during decoding of information from the remote control signal, the microprocessor ignores the error and uses the decoded information in the normal manner. Therefore, the microprocessor recognizes a pattern formed at the communication port by a signal emitted by the remote control, e.g. to identify a button on the remote control that has been pressed. During the recognition process, the port flags one or more errors (such as framing error, parity error), and such errors are ignored by the microprocessor. Programming the microprocessor to ignore errors from the port allows the device to operate with signals in a format different from the format normally recognized by the port.

Abstract: A computer system has a central processing unit, an input/output unit and two network units. The central processing unit is connected to the input/output unit via two network units. The central processing unit sends a frame, included in data, to the input/output unit via one network unit and simultaneously sends the same frame to the input/output unit via the other network unit. The input/output unit receives the same frames via both network unit. The input/output unit sends either of the same frames, whichever is received faster than the other, to the internal circuits.

Abstract: Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit for processing priority data. A method of managing access includes producing an access demand of a circuit for processing ordinary data to a bank of the memory, starting the realization of the demanded access, subsequently producing an access demand of the circuit for processing priority data to another bank of the memory, preparing, during the realization of the access demanded by the ordinary data processing circuits, the other bank of the memory, and interrupting the access in the course of realization as soon as said preparation is completed.

Abstract: A testing apparatus which, when resuming a test after interruption, makes it possible to determine whether or not an apparatus to be tested is the one for which the test has been interrupted. A controller acquires identification information for identifying the apparatus to be tested. The controller carries out a test comprised of a plurality of testing items to be executed on the apparatus to be tested. When the test is interrupted, a recording section is operable to record resuming information for carrying out the test on unexecuted testing items among the plurality of testing items, and the acquired identification information.

Abstract: A programmable controller has a multi-purpose processor such as an MPU and an application specific control device such as an ASIC (application specific integrated circuit). When the MPU requests the ASIC to execute a user program and the ASIC is activated, the MPU executes an event process while the ASIC executes the requested user program. When the MPU requests the ASIC to execute a DMA transfer process in an input/output refresh process and the ASIC is activated, the MPU executes an event process while the ASIC executes the requested DMA transfer process.

Abstract: A method for controlling communication. The method sends a first instruction from a first processor to a first device via a processor bus in electrical communication with a first bus, sends a control signal from the first processor to a selector, the selector switching electrical communication at least one signal line of the processor bus from the first bus to a second bus, sends a second instruction from the first processor to a second device, sends a control signal from the first processor to the selector, the selector switching electrical communication of the at least one signal line of the processor bus from the second bus to the first bus, and sends data from the first device to the first processor.

Abstract: A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise at least one Micro-Engine (ME) arranged to establish connections and support data transfers, via a switched fabric, in response to work requests from a host system for data transfers; interface blocks arranged to interface the switched fabric and the host system, and send/receive work requests and/or data messages for data transfers, via the switched fabric, and configured to provide context information needed for said Micro-Engine (ME) to process work requests for data transfers, via the switched fabric, wherein the Micro-Engine (ME) is implemented with a pipelined instruction execution architecture to handle one or more ME instructions and/or one or more tasks in parallel in order to process data messages.

Abstract: A CORBA Gateway between CORBA-based applications and an enterprise manager may be configurable to manage various networked objects, such as printers, scanners, copiers, telephone systems, cell phones, phone systems, faxes, routers, switches, etc., which may be interconnected via networks. Various embodiments of the CORBA Gateway may include an Event Gateway which manages object events. The CORBA Event Gateway is designed to leverage existing Event Distribution Server (EDS) sinks to provide EDS filtering functionality and EDS object level access control functionality. The approach leverages existing EDS solutions by providing a common sink for all events/notifications and using a unique Event Port Registry to manage the subscriptions of various TMN clients that subscribe for such events/notifications. Generally, the approach described provides the capability to filter events according to criteria presented by client event subscriptions.

Abstract: A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.

Abstract: A method and system for communicating to a sender an availability of receiving a new message includes providing buffers having at least one corresponding slot for storing a message and providing a credit signal that communicates to the sender only when all of the buffers have at least one of the corresponding slot available for storing a new message. Each of the buffers is monitored for whether at least one of the corresponding slots is available for storing the new message. A corresponding receiver counter is provided for each of the buffers. Each receiver counter is decremented when all of the buffers have at least one corresponding slot available for storing the new message. Each of the buffers is configured to receive a corresponding particular message type. The particular message type of the new message is determined. The new message is loaded into the corresponding slot of one of the buffers which is configured for receiving the particular message type of the new message.

Abstract: A new method and framework for implementing network protocol processing utilizing a combination of application threads and a dedicated thread to process IO completions in a completion queue that automatically detects and adjusts thread priorities to alleviate manual intervention. According to the present invention, as data transfer operations are completed by the network interface, completion information identifying the data transfer operations is posted on the completion queue. The completion information is read and processed by a combination of application and dedicated threads running in the system. A method monitors performance of the system to detect whether poor processor utilization or excessive context switches occurs, in which case a different thread is used to process the completion information.

Abstract: The method and apparatus presented are targeted to improve the performance of moving data between memory portions connected by a system bus where writes have higher performance than reads, such as the PCI bus. Due to the PCI bus design, read requests from memories connected across the PCI bus take a significantly longer time to complete than performing a write operation under the same circumstances. The present invention uses the faster write operations across the PCI bus, and queue management techniques, to take advantage of the relative speed of writes in a PCI system. The overall result is significant performance enhancement, which is especially useful in service aware networks (SAN) where operation at wired-speed is of paramount importance.

Abstract: In a computer system, a bridge element enabled module (102) includes a bridge element (106) that communicates with a communications network using a protocol (130) selected from a group of protocols (105) including an 2eSST protocol (480).

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.

Abstract: A method and apparatus for data transmission transmits both compressed and noncompressed data over each of a plurality of transmission paths. A data identification pattern is used to request a type of data from a memory having a plurality of data types stored within it. A handshaking control module is provided to select the correct type of data from the memory and place it on the output of the memory. The requested data type is then transmitted to a data decompression module via an interface. The data transmission can occur on any one of a plurality of data transmission paths when the data being transmitted is either Linework or Linework control data. When the data decompression module receives the data, it is then routed to any one of a plurality of data decompression systems based upon the results of the evaluation of the data identification pattern. The routing of the received data is wholly dependent upon the data identification pattern and independent of which transmission path the data was received on.

Abstract: A multifunction device includes a multifunction controller, a first interface for receiving input data from a document data source and a second interface for outputting processed input document data to a printer, and a touch screen that implements a graphical user interface for controlling the operation of the device. The device includes control over setting operational parameters for the document data source and the printer, and selecting a mode of operation of the multifunction device. Another interface is provided for coupling to a facsimile device for outputting processed document data to the facsimile device under control of the graphical user interface, while a further interface is provided for coupling to an e-mail port for outputting processed document data to the e-mail port, also under control of the graphical user interface. Users are able to search and access databases through a global data communications network.

Abstract: A method of scheduling the handling of data from a plurality of channels. The method includes accumulating data from a plurality of channels by a remote access server, scheduling a processor of the server to handle the accumulated data from at least one first one of the channels, once during a first cycle time, and scheduling the processor to handle the accumulated data from at least one second one of the channels, once during a second cycle time different from the first cycle time.

Abstract: An interface control device controls the packet-type transfer of data between one or more computers and one or more input/output devices. According to one embodiment of the present invention, when the interface control device receives the lead packet in a series of packets from an input/output device, it creates new device control data to control the transfer of the series of packets, and also determines an identification number for the particular series of packet transfers. The interface control device then sends a notification packet, containing the identification number, to the sending input/output device in response to receiving the lead packet. When the interface control device receives a packet that is a second or subsequent packet in the series of packets, it determines whether the data stored in the packet are normal by referring to the device control data corresponding to the identification number stored in the subsequent packet.

Abstract: A method and implementation is disclosed for messaging between components, preferably the controllers of peripheral devices in a network. The method and implementation includes providing a message from a first process and appending to the message a code indicating at least one descriptive parameter of the message. Steps and implementations are included for transmitting the message to a second process and interpreting the code so as to enable computation of the message by the second process across a plurality of different controller platforms.

Abstract: In an image input/output system, an image input/output control apparatus is interposed between an image input/output apparatus and an information terminal apparatus. Data exchange is performed between a first transmitting/receiving section of the image input/output control apparatus and a transmitting/receiving section of the image input/output apparatus as well as between the second transmitting/receiving section of the image input/output control apparatus and a transmitting/receiving section of the information terminal apparatus. The first transmitting/receiving section and the second transmitting/receiving section are isolated from each other physically. Under the control of the control section of the image input/output control apparatus, data received by one of the first transmitting/receiving section and the second transmitting/receiving section is transmitted by the other.

Abstract: The present invention is directed to an interface. An interface system suitable for coupling a first bus interface controller with a second bus interface controller includes a first bus interface controller and a second bus interface controller in which the second bus interface controller is coupled to the first bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data.

Abstract: Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache line. A buffer may store chunks of the first cache line in a first chunk order and may store chunks of the second cache line in a second chunk order. A control unit may present a requester via the second interface with one or more chunks of the first cache line from the buffer.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: A number of items of data from a data source (12) can be processed and supplied to a data destination (16, 17). The data can include image data, text data, numeric data or other types of data, or a combination of types of data. The processing of the data is controlled by a project definition (14, 71, 101) which includes a plurality of modules selected from a variety of available modules (Tables 1–4). The modules include input and output ports which are interrelated by binding information. One of the existing modules provides the capability for execution of a specified command in an independent and separate application program. Further, custom modules can be readily prepared, in order to supplement the default set of available modules.

Abstract: A device may include an upstream port and several downstream ports configured to transfer data at a different data transfer rate than the upstream port. The device may also include several downstream data handlers, each coupled to a respective one of the downstream ports, and an upstream data handler coupled to the upstream port. The data handlers are configured to implement a USB protocol. The upstream data handler is configured to provide data received via the upstream port to each of the downstream data handlers. Accordingly, the upstream data handler is shared between the various downstream data handlers.

Abstract: A distributed computer system and a method for replicating data in a distributed computer system. The system includes a plurality of processing nodes. A processing node comprises at least one processor and at least one local memory, where the local memory is in communication with each processing node. The system also includes maintenance software to determine whether data is read substantially more frequently than it is written and to replicate the data that is read substantially more frequently than it is written among the plurality of processing nodes. The method includes reviewing classes of data, identifying whether at least a portion of data of a certain class used by the processing nodes is read substantially more frequently than it is written and replicating copies of the data of that class in the local memories.

Abstract: The present invention is directed to a configurable input/output interface and method for data transfer between a host and a target in a network environment. A method for providing data transfer between a host and a target in a network environment by a configurable input/output interface includes providing a logical identifier. The logical identifier is configurable for operation in at least two modes, the at least two modes including at least two of referencing multiple data transfer routes between the target and the input/output device utilizing a single logical identifier, referencing a single route between the target and the input/output device utilizing a logical identifier, and referencing a physical address of the target utilizing a logical identifier. Communications between the host and the target are managed by selecting a mode of the at least two modes operable by the input/output interface.

Abstract: The invention includes a platform having a controller coupled to a central processing unit through a system bus. The platform also includes a register device coupled between the central processing unit and the controller. Moreover, the platform also includes a bus coupled to the controller having an end that is adapted to receive a device. The register device includes a depth that is adapted to hold all instruction packets from the central processing unit without presenting delays due to full conditions.

Abstract: A storage device (200) has a memory and a circuit (100) which has a data input (Din), a control input (CTRL) and a data output (Dout), and provides an address input from the data input (Din) to the memory in accordance with a control signal from the control input (CTRL), so that the storage device (200) stores the data at the address in the memory or outputs data at the address in the memory to the data output (Dout). The apparatus provides the control signal to the control input (CTRL) from the interface (PORTS, P0, P1, P2), address and the data to the data input (Din) from the interface (PORTS, P0, P1, P2), to store the data at the address in the memory or to output data at the address in the memory to the data output (Dout). The apparatus may have a microcontroller (MPU) in which the interface (PORTS, P0, P1, P2) is provided.

Abstract: Direct memory access (DMA) controllers are used in digital processing of image data in image processing devices such as digital copiers, scanners, printers and fax machines. The DMA controllers are controlled for memory access by a predetermined resume signal that is sent from one DMA controller to another.

Abstract: Various embodiments of a system and method for configuring a set of DMA resources as multiple virtual DMA channels are disclosed. In one embodiment, a system may include a context memory configured to store context parameters for each of the virtual DMA channels, a set of DMA resources, a DMA controller coupled to the context memory, and several I/O resources. The DMA controller is configured to configure the set of DMA resources as different virtual DMA channels using context parameters associated with different respective ones of the virtual DMA channels. Each virtual DMA channel corresponds to one of the I/O resources.

Abstract: A method and apparatus for the optimization of memory read operations via read launch optimizations in memory interconnect are disclosed. In one embodiment, a write request may be preempted by a read request.

Abstract: A data processing apparatus improves speed and efficiency of transfer of bit data, especially, multivalue data bit plane. For this purpose, a memory 50 holds four 8-bit multivalue data per 1 word, and bit plane coding processing is made by 4×4 (=16) multivalue data (processing block). In a memory area 51, the most significant bit (bit 7) of respective multivalue data (data 0 to 15 in FIG. 5) is collected in the order of multivalue data, and stored in one position (hatched portions in FIG. 5). Similarly, bit 6 is collected from the respective multivalue data and stored in one position.

Abstract: A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

Abstract: A configuration notification unit monitors internal messages generated by an operating system of a computer related to a device configuration process for plug and play devices coupled to the computer via a serial bus interface. The configuration notification unit outputs a real time warning to the user when it is unsafe to change the number of devices coupled to the computer. In a preferred embodiment, the configuration notification unit include a message handler coupled to an indication unit.