Abstract: A safety architecture system includes, in one aspect, a first stage comprising a primary unit that generates primary data for performing normal system functionality; a secondary unit that generates secondary data for performing alternative system functionality; a primary safety gate coupled to the primary unit, with the primary safety gate providing the primary data as a primary output responsive to a determination of validity of the primary data; and a secondary safety gate coupled to the secondary unit, with the secondary safety gate providing the secondary data as a secondary output responsive to a determination of validity of the secondary data. The system also includes an output selector that is coupled to both the primary safety gate and the secondary safety gate of the first stage, with the output selector providing a system output responsive to the determinations of the validities of the primary data and the secondary data.

Abstract: Aspects of the invention include receiving a request to transfer data from a first storage device, coupled to a sending server, to a second storage device, coupled to a receiving server. The data is transferred from the first storage device to the second storage device in response to the request. The transferring includes allocating a first temporary memory on the sending server and moving the data from the first storage device to the first temporary memory. The transferring also includes initiating a remote direct memory access (RDMA) between the first temporary memory and a second temporary memory on the second server. The RDMA causes the data to be transferred from the first temporary memory to the second temporary memory independently of an operating system executing on a processor of the sending server or the receiving server. The transferring further includes receiving a notification that the transfer completed.

Abstract: A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.

Abstract: Disclosed by the present invention are a running method for an embedded type virtual device and a system, an embedded type device being divided into a managing process, a plurality of real-time modules and a plurality of non-real-time modules. The managing process reading a configuration file, loading real-time and non-real-time module libraries of each processor and completing initialization interaction by means of a virtual controller area network (CAN) bus and first in, first out (FIFO) communication. The managing process starting a real-time thread and serially scheduling real-time task according to a task period setting relation. The managing process starting a plurality of non-real-time threads, calling a period task of a non-real-time module and carrying out parallel communication with a plurality of debugging clients. The real-time modules exchange data with each other by means of a virtual data bus, and the real-time modules exchange data with the non-real-time modules by means of a sharing memory.

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: Aspects of the present disclosure provide techniques for routing internet protocol (IP) and non-IP packets in cellular vehicle-to-everything devices that can be transmitted over the air via cellular or side-link device-to-device (D2D) communication systems without the need for the applications (e.g., automotive applications) to modify its operations. Specifically, an application (automotive application or web browser) may use default Application Programming Interface (API) that is typically used for regular cellular communication without modifying its operations to differentiate between IP and non-IP packets. Instead, in accordance with present disclosure, logical data paths may be dynamically adjusted to map services associated with the packets with an appropriate media access control (MAC) flow such that the modem receiving the packet may process and route the packet to target end-destination.

Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

Abstract: The invention introduces a method for executing host input-output (IO) commands, performed by a processing unit of a device side when loading and executing program code of a first layer, at least including: receiving a host IO command from a host side through a frontend interface; generating a slot bit table (SBT) including an entry according to the host IO command; creating a thread of a second layer; and sending addresses of callback functions and the SBT to the thread of the second layer, thereby enabling the thread of the second layer to call the callback functions according to the IO operation of the SBT for driving the frontend interface to interact with the host side to transmit user data read from a storage unit to the host side, or receive user data to be programmed into the storage unit from the host side.

Abstract: Systems and methods for providing capability of access to distributed memory blocks using a global address scheme in a programmable logic device. Each of the distributed memory blocks includes routing circuitry that receives data, and in a first mode, decodes whether the data is intended for a respective distributed memory block. In a second mode, the data may bypass routing circuitry. Furthermore, the data may be received at the distributed memory block via cascade connections of distributed memory blocks in a column and/or via register in the programmable fabric of the programmable logic device.

Abstract: A data processing system and method include processing circuitry configured to receive sensor data from a plurality of field devices and convert the sensor data to field data, receive a first source file having first field data exported from a first editor, receive a second source file having second field data exported from a second editor, filter the first and second field data according to one or more conditions, generate multiple worksheets based upon the one or more conditions of the filtered first and second field data, extract the filtered first and second field data from source fields of the first source file and the second source file and map the extracted first and second field data into related worksheet fields of the multiple worksheets, and export the multiple worksheets having the mapped and extracted first and second field data in an export file.

Abstract: Updating firmware in an programmable integrated circuit (IC) includes determining, using a processor of a computer, a base address register (BAR) of an accelerator card from a device data file, wherein the accelerator card includes a programmable IC and is connected to the computer via a communication bus, mapping, using the processor, a feature PROM and a flash programmer circuit of the programmable IC to local memory of the computer using the BAR, and reading, over the communication bus, the feature PROM on the programmable IC to determine a programming mode for programming an external flash memory coupled to the flash programmer circuit. Based on the programming mode and using the processor, firmware is provided to the flash programmer circuit on the programmable IC via the communication bus. The flash programmer circuit is configured to program the firmware into the external flash memory.

Abstract: A memory control method receives a read request data set including a management ID and requesting reading of data from a memory, transmits read data that is read corresponding to the read request, stores write data temporarily in a write buffer, stores the read data read from the memory temporarily in a read buffer, stores write control data and read control data in an arbitration queue, executes an arbitration that determines a priority order of processing taking the write control data and the read control data that are stored in the arbitration queue as targets, and matches an order of transmitting a plurality of pieces of read data that are read from the memory corresponding to the read control data selected based on the determined priority order and are associated with an identical management ID to an order of receiving the read request data set.

Abstract: A direct memory access controller, configured to be used in a computing node of a system on chip (SoC), includes: (1) an input buffer for receiving packets of data coming from an input/output interface of the computing node; (2) a write control module for controlling writing of data extracted from each packet to a local memory of the computing node shared by at least one processor other than the direct memory access controller; and (3) an arithmetic logic unit for executing microprograms. The write control module is configured to control the execution by the arithmetic logic unit of at least one microprogram including instruction lines for arithmetic and/or logical calculation concerning only storage addresses for storing the data received by the input buffer for a reorganization of the data in the shared local memory. Optionally, at least one microprogram may be stored in a register, and at least two operating modes (e.g.

Abstract: The invention relates to a method for transferring data between a computer program executed by a processor and an input/output device using a memory accessible by the computer program and the input/output device. An operating system provides a trigger address range in a virtual address space assigned to the computer program. A page fault is caused by accessing the trigger address by the computer program. A page fault handler handling the page fault acquires information for identifying the data to be transferred using the trigger address. The acquired information is provided to the input/output device and the identified data is transferred between the memory and the input/output device.

Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.

Abstract: Techniques and mechanisms for exchanging information between a solid state drive (SSD) and a write-in-place non-volatile memory via a host device. In an embodiment, access control information defines state of the SSD, where the access control information determines and/or is based on an access by the host device to other non-volatile memory of the SSD. The access control information includes address conversion information defining a correspondence of a logical address with a physical address for a location of the other non-volatile memory of the SSD. At least some of the access control information is stored by the SSD to the write-in-place non-volatile memory for later retrieval by the SSD. In another embodiment, the SSD signals that a commit operation is to be performed to flush any cached or buffered access control information into the write-in-place non-volatile memory.

Abstract: Example implementations relate to determining a device wear-rate. An example system for determining a device wear-rate can include a plurality of filter drivers to: monitor system requests for I/O associated with a device of the system and transmit information associated with the system requests to a filter manager. The system can also include the filter manager to catalog the information, a service to collate the information across a plurality of machine configurations and workloads, and a processor to determine a wear-rate of the device based on an analysis of the collated information.

Abstract: A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.

Abstract: When contents of UFSHCI standard are directly implemented in a UFS host, a problem may occur such that read/write operations of a UFS device stop or contents of data are destroyed. A semiconductor device has a UFS host controller that performs data transfer with a universal flash storage (UFS) device. The semiconductor device includes a Run-Stop register that sets the UFS host controller into a processing possible state, a Door bell register that instructs the UFS host controller to perform transfer, and a ready bit that indicates whether or not the UFS host controller can perform processing of transfer request. When the Run-Stop register is cleared while the data transfer is in process, the UFS host controller prevents a next data transfer from being registered until the data transfer is completed.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: Providing access to a data storage resource. A storage subsystem comprising one or more storage address units and is associated with one or more access interfaces is identified. An address-interface correlation guideline is identified that defines a combination of rules that govern which access interfaces are used to access storage address units. A target address unit identification is received from a requesting system. A processor determines which storage address units a requesting system requests to access to based on the received target address unit identification. The target address unit identification is associated with at least one of the storage address units. The requesting system is provided with access to the storage address units using access interfaces that are determined based on a target interface conclusion.

Abstract: A signature is generated to indicate a direct memory access (DMA) operation involving a transfer, by a DMA engine, of data between a host memory circuit and an endpoint memory circuit of an endpoint processor circuit. First descriptors of the DMA engine are defined relative to the endpoint memory circuit or host memory circuit. A signature is received that indicates that second descriptors have been configured by the endpoint processor circuit. In response to receiving the endpoint signature, the DMA engine is enabled to begin the DMA operation.

Abstract: A recording medium to be used by being connected to a digital device includes a local bus, a plurality of recording units, an information storage unit, and a communication unit. The local bus has a plurality of switches or bridges. The plurality of recording units are connected to the local bus. The information storage unit stores information indicating a bus configuration of the local bus. The communication unit is used for transferring the information to and from the digital device. After the recording medium is inserted into the digital device, the bus configuration of the local bus is reconstructed based on the information acquired from the communication unit via the information storage unit by the digital device.

Abstract: An efficient data storage device is disclosed, which uses a microprocessor and at least one volatile memory to operate a non-volatile memory. The microprocessor allocates the volatile memory to provide a cache area. According to an asynchronous event request (AER) issued by a host, the microprocessor uses the cache area to collect sections of write data requested by the host, programs the sections of write data collected in the cache area to the non-volatile memory together, and reports failed programming of the sections of write data to the host by AER completion information.

Abstract: A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.

Abstract: Method and system are disclosed for a programmable state machine controller in a parallel processing system. The programmable state machine controller includes a set of control registers configured to serve a set of application specific engines; a set of task engines configured to access a plurality of application resources in parallel; one or more processors configured to: receive multiple requests from the set of application specific engines, determine availability of the set of task engines and the plurality of application resources being requested, assign the set of task engines to serve the set of application specific engines based on the availability of the set of task engines and the availability of the plurality of application resources being requested, and serve the multiple requests from the set of application specific engines in parallel.

Abstract: System and techniques for error correction code (ECC) memory security are described herein. A write request that includes data is received. An integrity check value (ICV) is computed for the data. Then, the write request is performed, including writing a representation of the data to a data area in memory and writing the ICV into an ECC area in memory. Here, the data area is addressable by a host and the ECC area corresponds to the data area via hardware of the memory.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communica

Abstract: According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.

Abstract: A data processing method and a storage apparatus are disclosed. The data processing method includes: receiving, by a non-volatile memory express (NVMe) storage device, an NVMe write command sent by a host, where the NVMe write command carries a key and a value pointer, the value pointer points to first storage space, and the first storage space is used to store a value; obtaining, by the NVMe storage device, the key from the NVMe write command and a value length, and allocating second storage space to the value according to the value length, where the second storage space is in the NVMe storage device; and obtaining, by the NVMe storage device, the value from the host, and storing the value in the second storage space.

Abstract: Systems, methods, and/or devices are used to store metadata in a storage system. In one aspect, a first user space module sends a logical memory request to a memory management module of a kernel space module. The logical memory request includes data and metadata. A second user space module obtains the metadata of the logical memory request. A storage engine of the second user space module determines, in accordance with the obtained metadata, a location in non-volatile memory for the data. A second user space module generates a physical memory request including an indication of the non-volatile memory for the data. The second user space module transmits the physical memory request to the kernel space memory management module.

Abstract: A computer-implemented method, a computer program product, and a computer system for parallel task management. A computer system receives a new task that requests to access a resource may be received. In response to an access workload being above a first threshold, the computer system dispatches the new task to at least one predefined processing unit, wherein the access workload may be associated with the resource that is in parallel accessed by a plurality of existing tasks.

Abstract: Embodiments disclosed herein provide systems, methods, and computer readable media for storing data to a plurality of physical storage volumes. In a particular embodiment, a method provides identifying first data for storage on the plurality of physical storage volumes. Each of the plurality of storage volumes corresponds to respective ones of a plurality of data channels. The method further provides segmenting the first data into a plurality of data segments corresponding to respective ones of the plurality of data channels and transferring the plurality of data segments as respective bit streams over the respective ones of the plurality of data channels to the respective ones of the plurality of physical storage volumes. The plurality of storage volumes stores the respective bit streams in the exact condition in which the bit streams are received.

Abstract: A memory system may include: a nonvolatile memory device including a memory cell array and a page buffer coupled to the memory cell array; and a controller configured to interface with the nonvolatile memory device, wherein the controller moves descriptors on a cache command from a command queue to a cache queue, the cache command being transferred to the nonvolatile memory device, and selectively moves the descriptors moved to the cache queue to a response queue.

Abstract: A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.

Abstract: Technologies for cryptographic protection of I/O audio data include a computing device with a cryptographic engine and an audio controller. A trusted software component may request an untrusted audio driver to establish an audio session with the audio controller that is associated with an audio codec. The trusted software component may verify that a stream identifier associated with the audio session received from the audio driver matches a stream identifier received from the codec. The trusted software may program the cryptographic engine with a DMA channel identifier associated with the codec, and the audio controller may assert the channel identifier in each DMA transaction associated with the audio session. The cryptographic engine cryptographically protects audio data associated with the audio session. The audio controller may lock the controller topology after establishing the audio session, to prevent re-routing of audio during a trusted audio session. Other embodiments are described and claimed.

Abstract: A storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a first region and a second region. The controller classifies a plurality of read requests for reading data from the nonvolatile semiconductor memory into first read requests for reading data from the first region and second read requests for reading data from the second region, pairs one of the first read requests with one of the second read requests to generate a third read request, and outputs the third read request to the nonvolatile semiconductor memory.

Abstract: Aspects of the present disclosure include a memory sub-system configured to reduce latency and power consumption during a read-write cycle. The memory system comprises a first memory component and a processing device operatively coupled to the first memory component. The processing device is configured to receive a request to write a first sequence of data bits from a first data block of a second memory component to memory media of the first memory component. In response to receiving the request, the processing device reads a second sequence of data bits from a second data block stored in the memory media of the first memory component, and compares the first sequence of data bits with the second sequence of data bits.

Abstract: A peripheral device controlling device according to an embodiment of the inventive concept includes a command queue for storing at least one Device to Device (D2D) command for data communication between a first peripheral device and a second peripheral device, a command parser for obtaining information related to the data communication from the at least one D2D command, and an orchestrator for controlling at least one of the first peripheral device and the second peripheral device to transfer data from the first peripheral device to the second peripheral device based on the acquired information.

Abstract: Disclosed herein are a virtual desktop server for supporting high-quality graphics processing and a method for processing high-quality graphics using the virtual desktop server. The virtual desktop server includes one or more virtual desktops for creating instructions for accelerated graphics processing by running a high-quality graphics application, one or more hardware-based graphics accelerators for creating screen data by executing the instructions for accelerated graphics processing and for storing the created screen data in a frame buffer, and a hypervisor for transmitting the screen data received from the virtual desktop to a client over a network, and the virtual desktop captures the screen data stored in the frame buffer, converts the captured screen data, and delivers the converted screen data to the hypervisor.

Abstract: A direct memory access (DMA) device provides for transforming source data as it is transferred to a destination memory space. The transformation can encompass a range of arithmetic logic unit (ALU) operations. The transformation can include discerning comparative matches in the source address space, such that matched-indice-reference-offsets are transferred to destination memory. A processor requesting the transfer can also configure the transformation to be completed by writing configuration data to memory and/or programming the DMA device. In transforming data as it is transferred, the DMA device can obviate time-consuming processing otherwise done after conventional DMA transfers.

Abstract: The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: Based on a request to identify a networking component, a first application programming interface (API) signature is selected from a plurality of API signatures within a priority list that associates the first API signature with a corresponding first API type, wherein the first API signature includes a first characteristic. A first API implemented by the networking component is tested to determining whether the first API implemented by the networking component exhibits the first characteristic. A determination is made of whether the networking component implements the first API type based on determining that the first API implemented by the networking component exhibits the first characteristic.

Abstract: Dynamically setting the order of optimization of physical hosts allows more efficient and varied optimization. An ordering policy mechanism utilizes ordering policies to set an order for the optimizer to optimize physical the hosts. The ordering policy mechanism may allow a system administrator to create and/or select ordering policies. The ordering policies may include fixed ordering policies or dynamic ordering policies.

Abstract: Dynamically setting the order of optimization of physical hosts allows more efficient and varied optimization. An ordering policy mechanism utilizes ordering policies to set an order for the optimizer to optimize physical the hosts. The ordering policy mechanism may allow a system administrator to create and/or select ordering policies. The ordering policies may include fixed ordering policies or dynamic ordering policies.

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.