Abstract: A storage device includes a nonvolatile semiconductor memory module, and a host interface for connection to a host that is external to the storage device. The host interface includes a first interface circuit conforming to Serial Peripheral Interface (SPI) and a second interface circuit conforming to an interface standard different from SPI. Output terminals of the first interface circuit are connected to input terminals of the second interface circuit, and output terminals of the second interface circuit are connected to input terminals of the nonvolatile semiconductor memory module.

Abstract: To realize DMA data transfer between a host computer and another computer even in the case that the host computer and the another computer are each equipped with a CPU, a memory, and so forth independently. A computer communicably connected with a first computer including a first memory and a driver for controlling a device, the computer comprising: the device; and a second memory, wherein a first DMA transfer is executed based on a DMA transfer request received from the driver, a second DMA transfer is executed to transfer data existing at a transfer destination address of the first DMA transfer between the first memory and the second memory, and the transfer destination address is detected as a result of executing the first DMA transfer.

Abstract: Metadata is stored within a database for each of a plurality of objects in different frames associated with a structure descriptor (e.g., a container directory entry, etc.). The frames are part of a metadata page and each comprising an object and a header specifying a version identifier for the object and a size of the object. The structure descriptor initially is built for a first build identifier. Thereafter, upon the structure descriptor changing from the first build identifier to a second build identifier, at least one of the objects that require migration is identified. The identification is based on the version identifier for the object being different from the second build identifier. In response, the identified objects are migrated from their corresponding frame to a new frame. The new frame includes the objects and new headers that include a version identifier equal to the second build identifier.

Abstract: A microcomputer is provided for each of industrial apparatuses to synchronously control them and includes a CPU, a peripheral module, and a communication interface. The peripheral module controls an external apparatus based on a specified control parameter. The communication interface includes a time register that is synchronized with the other apparatuses in time series. The communication interface issues a CPU interrupt and a peripheral module interrupt to the CPU and the peripheral module, respectively, if a successively settled correction time matches the time register. In response to the peripheral module interrupt, the peripheral module changes the control parameter from a current value to an update value. In response to the CPU interrupt, the CPU starts an update program to calculate the next update value for the control parameter and writes the calculated value to the peripheral module.

Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

Abstract: Methods and apparatuses are provided for processing audio data at an electronic device. Audio data is obtained. A type of the audio data is identified. An audio processing mode corresponding to the type of the audio data is selected. An audio track of the audio data is output, based on the audio processing mode.

Abstract: Techniques are disclosed for managing vector element ordering. One technique includes setting one or more control bits that determine a vector element ordering and a vector element numbering, where the one or more control bits are stored in a machine status register or in a page table entry. The vector element ordering includes one of a big-endian mode and a little-endian mode, and the vector element numbering includes one of a big-endian mode and a little-endian mode. The technique includes reading the one or more control bits to determine a big-endian or a little-endian mode for the vector element ordering and for the vector element numbering. The technique also includes performing a vector operation in the determined mode for the vector element ordering and the determined mode for the vector element numbering.

Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

Abstract: Valves, pumps, detectors, sample loops, fraction collectors and the like are individually incorporated into modules that are mountable at individual mounting sites on a base unit which also supports one or more chromatography columns. Each module includes fluid connections to other modules and a microcontroller joining the module to a computed and monitor through an electronic connector at each mounting site. The fluid connections between the modules and the column(s) are removed from the electronic connections and accessible to the user. A software platform may recognize the modules and their locations, coordinate fluid connections between the modules, and provide a variety of control, monitoring, data generating and data processing functions to generate chromatographic data. The software platform may also provide graphical tools for designing chromatographic methods from a library of phases.

Abstract: Systems and methods for operating a DMA unit with address alignment are disclosed. These may include configuring a bandwidth control setting for a read job that includes a data transfer size corresponding to a first number of bytes. A second number of bytes to reach a read address alignment is determined. In a first data transfer, a third number of bytes substantially equal to the first number of bytes plus the second number of bytes are transferred. In subsequent data transfers of the read job, the first number of bytes are transferred to the data buffer. After the third number of bytes are transferred to the data buffer, a fourth number of bytes from the data buffer are transferred to a destination.

Abstract: Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn't require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).

Abstract: An electronic device includes a first memory subsystem, a second memory subsystem and a direct memory access controller. In response to a first type of request from a processor, the direct memory access controller requests data from the first memory subsystem and provides the data to the second memory subsystem. In response to a second type of request from a processor, the direct memory access controller requests an uncompressed matrix from the first memory subsystem, compresses the uncompressed matrix to generate a compressed matrix, and provides the compressed matrix to the second memory subsystem. In response to a third type of request from a processor, the direct memory access controller requests a compressed matrix from the second memory subsystem, un-compresses the compressed matric to generate an uncompressed matrix, and provides the un-compressed matrix to the first memory subsystem.

Abstract: Embodiments of the technology can provide the flexibility of fine-grained dynamic partitioning of various compute resources among different compute subsystems on an SoC. A plurality of processing cores, cache hierarchies, memory controllers and I/O resources can be dynamically partitioned between a network compute subsystem and a server compute subsystem on the SoC.

Abstract: An apparatus comprises a processor to generate, in anticipation of receipt of a read request for data of a data set, a prefetch request to retrieve the data set from a memory device, the prefetch request to comprise at least one parameter indicating a size of the data set. The processor is further to cause transmission of the prefetch request to the memory device and in response to a read request for at least a portion of the data set, request the at least a portion of the data set from a cache storing a copy of the data set, wherein the cache is to store the copy of the data set after the copy is received from the memory device in response to the prefetch request.

Abstract: A first hypervisor uses a first version of a virtual-memory file system (VMemFS) suspends virtual machines. A second hypervisor uses a instance of the VMemFS, the version of which may be the same or different from the first version. The VMemFS is designed so that an instance of the same or a later version of the VMemFS can read and ingest information in memory written to memory by another instance of the VMemFS. Accordingly, the second hypervisor resumes the virtual machines, effecting an update or other swap of hypervisors with minimal interruption. In other examples, the swapped hypervisors support process containers or simply support virtual memory.

Abstract: A method for executing an application of a display apparatus is provided. The method includes: storing a first request list that includes items of data that an application requests from other applications; comparing the first request list with a second provision list that includes items of data provided from the other applications and acquiring data that corresponds to the items included in the first request list; and executing the application based on the acquired data.

Abstract: Mounting a filesystem for media. The method includes detecting that media has been connected to a computing device. The method further includes causing a filesystem for the media to be mounted to a virtual machine. The virtual machine is coupled to a server. The method further includes causing file data from the media organized by the filesystem to be served from the server to the computing device.

Abstract: A processor includes a central processing unit (CPU) and a direct memory access (DMA) adapter circuit. The DMA adapter circuit includes a DMA controller circuit and is configured to interface with a legacy internal hardware peripheral and with a DMA-enabled internal hardware peripheral. The DMA-enabled internal hardware peripheral includes a first special function register (SFR). The legacy internal hardware peripheral includes no DMA features. The CPU is configured to execute a legacy application that accesses a setting in memory through the legacy internal hardware peripheral. Execution of the legacy application includes access by the CPU of the setting in memory. The DMA controller circuit is configured to access the setting in memory during execution of a DMA-enabled application through the DMA-enabled internal hardware peripheral.

Abstract: A fabric-attachable storage drive self-monitors a prespecified parameter. Responsive to detecting satisfaction of a prespecified condition, the storage drive autonomously generates a reportable event regarding the self-monitored prespecified parameter, and autonomously transmits the reportable event to a prespecified location on a network fabric to which the drive is connected. The storage drive can interact with other fabric-attachable storage drives to create a logical volume according to a specified logical data storage topology on a self-organized storage device group in a peer-to-peer manner. The storage drive can be a programmable non-volatile memory Express (NVMe) storage drive exporting access thereto over an NVMe-over-fabric storage protocol, or a programmable storage drive lacking an external interface by which to connect to a host computing device storage device but that has a network interface connected to a network fabric.

Abstract: A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.

Abstract: Attributing consumed storage capacity among entities storing data in a storage array includes: identifying a data object stored in the storage array and shared by a plurality of entities, where the data object occupies an amount of storage capacity of the storage array; and attributing to each entity a fractional portion of the amount of storage capacity occupied by the data object.

Abstract: In various embodiments, a configurable hardware accelerator is provided. The configurable accelerator may include a transmit direct memory access (DMA) engine, a receive DMA engine, and one or more execution engines. In those embodiments, the configurable accelerator can be configured to access a shared data storage in a continuous mode. The transmit and receive DMA engines can be configured to transmit data from one location in the shared data storage to a different location in the memory storage. The execution engine(s) can be configured to perform a wide range of functions on the data accessed by the transmit DMA engine(s) in streaming fashion. In those embodiments, the data are accessed and processed by the configurable accelerator in a streaming manner to speed up the data processing performance.

Abstract: A fabric-attachable storage drive self-monitors a prespecified parameter. Responsive to detecting satisfaction of a prespecified condition, the storage drive autonomously generates a reportable event regarding the self-monitored prespecified parameter, and autonomously transmits the reportable event to a prespecified location on a network fabric to which the drive is connected. The storage drive can interact with other fabric-attachable storage drives to create a logical volume according to a specified logical data storage topology on a self-organized storage device group in a peer-to-peer manner. The storage drive can be a programmable non-volatile memory Express (NVMe) storage drive exporting access thereto over an NVMe-over-fabric storage protocol, or a programmable storage drive lacking an external interface by which to connect to a host computing device storage device but that has a network interface connected to a network fabric.

Abstract: Examples relate to providing data backup for a multi-tenant application. One example enables determination that a first data set for a first tenant from the application should be backed up and determination, independently from determining the first data set should be backed up, that a second data set for a second tenant from the application should be backed up. Responsive to determining the first data set should be backed up, a first portion of the first data set stored at a first data resource of a first type may be accessed via a first adaptor for the first type of data resource, and a second portion of the first data set stored at a second data resource of a second type may be accessed via a second adaptor for the second type of data resource. The accessed portions of the first data set may be stored.

Abstract: A system and related method are provided for interleaving undelayed and intentionally delayed executable instructions that are executable by a processor of a system having a memory. The method comprises utilizing the processor to execute programmed instructions for: receiving, by a message handling process (MHPa), a triggering signal triggering the MHPa to an active state. In response to the MHPa being triggered to the active state, the MHPa determines if a delayed message queue (DMQa) is empty. When the DMQa is empty, the system determines if an immediate message queue is empty. When not, a current message is set to be a top message in the IMQa. When the delay criteria of the current message do not require an intentional delay, the system executes the executable instructions of the current message, and when they do, the message is placed in the DMQa.

Abstract: An apparatus in one embodiment comprises a storage system configured to implement at least one scalable video server. The storage system comprises a software-defined storage pool, and the scalable video server comprises a plurality of file system storage nodes each including a corresponding portion of the software-defined storage pool and an associated file system server. A streaming bandwidth of the scalable video server for a given video stream is controlled by adjusting the number of file system storage nodes utilized for the given video stream in the scalable video server. The file system servers of the respective file system storage nodes are configured to interact with a file system client associated with the given video stream. The streaming bandwidth of the scalable video server for the given video stream may be dynamically adjusted by adding or deleting file system storage nodes to or from the scalable video server.

Abstract: An operating system monitors a performance metric of a direct memory access (DMA) engine on an I/O adapter to update a translation table used during DMA operations. The translation table is used during a DMA operation to map a virtual address provided by the I/O adapter to a physical address of a data page in the memory modules. If the DMA engine is being underutilized, the operating system updates the translation table such that a virtual address maps to physical address corresponding to a memory location in a more energy efficient memory module. However, if the DMA engine is over-utilized, the operating system may update the translation table such that the data used in the DMA engine is stored in memory modules that provide quicker access times—e.g., the operating system may map virtual addresses to physical addresses in DRAM rather than phase change memory.

Abstract: This system determines the operation of data transfer means by direct memory access by a task scheduler in charge of process context changes, the system including deterministic means for establishing and suspending the data transfers of memory data initiated before, but not terminated during, the contextual changes, and for resuming the data transfers during the return to the corresponding initial context, in order to give each process full and exclusive access to the means of transfer.

Abstract: Disclosed are a direct memory access (DMA) apparatus and method. The DMA apparatus may include memory, a buffer, a DMA controller suitable for setting group regions from which data of the memory is to be read, reading data of each odd-numbered group region in a first direction and writing the read data of each odd-numbered group region in the buffer in the first direction, and reading data of each even-numbered group region in the first direction and writing the read data of each even-numbered group region in the buffer in a second direction, and a read module suitable for reading the data of each odd-numbered group region written in the buffer in the second direction and reading the data of each even-numbered group region in the first direction.

Abstract: A bonding, communication and control BCC system that, via multiple digital and analog inputs and outputs provided by an on-the-go ready (OTG) microcontroller and a microcontroller combination, is capable of integrating the function of components required for a device to perform its tasks. Each BCC unit has the minimum amount of built in hardware required. First the BCC units bond, using multiple modes of identification and recognition technology. Second, the BCC units interconnect and exchange data via encrypted communication. Third, plug and play hardware can be added to the BCC unit. Each BCC unit can pair with a smart device, making possible full utilization of all of the hardware, software and existing infrastructure of the smart device, including its ability to send data to and from a remote server location.

Abstract: A method for power management of a mobile device. The method includes evaluating content of a plurality of applications received at a mobile device operated by a user and determining latency information for each of the plurality of applications. The method further includes dynamically determining a priority of the plurality of applications based on the latency information for each application, and dynamically adjusting the mobile device between at least two wireless power modes based on the priority of the plurality of applications.

Abstract: A method for storing data related to video decoding is described. A video-decoding device may divide a video image into a plurality of coding units (CUs). Each of the plurality of CUs has a horizontal coordinate and a vertical coordinate. The video-decoding device may retrieve a first tidbit associated with a first CU from a one-dimensional storage structure. The first CU is adjacent to an un-decoded second CU. The first tidbit is generated during decoding of the first CU and stored in the one-dimensional storage structure based on a first storage index calculated using the first CU's horizontal and vertical coordinates. The video-decoding device may further decode the second CU based on the first tidbit, and store a second tidbit associated with the second CU in the one-dimensional storage structure based on a second storage index calculated using the second CU's horizontal and vertical coordinates.

Abstract: Embodiments of the present invention provide a Polar code decoding method and decoder. The decoding method includes: segmenting a first Polar code having a length of N into m mutually coupled second Polar codes, where a length of each second Polar code is N/m, N and m are integer powers of 2, and N>m; independently decoding the m second Polar codes to acquire decoding results of the m second Polar codes; and obtaining a decoding result of the first Polar code according to the decoding results of the m second Polar codes. In the embodiments of the present invention, a Polar code having a length of N is segmented into multiple segments of mutually coupled Polar codes; the segmented Polar codes are independently decoded; and results of the independent decoding are jointly processed to obtain a decoding result of an original Polar code.

Abstract: Disclosed herein are techniques for migrating data from a source memory range to a destination memory while data is being written into the source memory range. An apparatus includes a control logic configured to receive a request for data migration and initiate the data migration using a direct memory access (DMA) controller, while the source memory range continues to accept write operations. The apparatus also includes a tracking logic coupled to the control logic and configured to track write operations performed to the source memory range while data is being copied from the source memory range to the destination memory. The control logic is further configured to initiate copying data associated with the tracked write operations to the destination memory.

Abstract: A multi-core processor manages contention amongst its cores for access to a shared resource using a semaphore that maintains separate access-request queues for different cores and uses a selectable scheduling algorithm to grant pending requests, one at a time. The semaphore signals the core whose request is granted by sending it an interrupt signal using a dedicated core line that is not part of the system bus. The granted request is then de-queued, and the core accesses the shared resource in response to receiving the interrupt signal. The use of dedicated core lines for transmitting interrupt signals from the semaphore to the cores alleviates the need for repeated polling of the semaphore on the system bus. The use of the scheduling algorithm prevents a potential race condition between contending cores.

Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.

Abstract: An integrated circuit coupled to an external serial bus is presented. A method for prefetching data from an external serial bus is presented. The integrated circuit comprises a serial interface, a data cache, and a prefetch control unit. The serial interface detects a data address on the serial bus and reads data elements from data storage units. The data storage units may be internal or external to the integrated circuit. The data cache is coupled to the serial interface via an internal bus. The prefetch control unit instructs the serial interface to prefetch a data element associated with the data address by reading the data element from a target data storage unit associated with the data address. The data element and the data address are written to the data cache. When a read request is detected, the data element can be quickly accessed from the data cache.

Abstract: A computer-implemented method for migrating a buffer used for direct memory access (DMA) may include receiving a request to perform a DMA data transfer between a first partitionable endpoint and a buffer of a first memory in a system having two or more processor chips. Each processor chip may have an associated memory and one or more partitionable endpoints. The buffer from the first memory may be migrated to a second memory based on whether the first memory is local or remote to the first partitionable endpoint, and based on a DMA data transfer activity level. A memory is local to a partitionable endpoint when the memory and the partitionable endpoint are associated with a same processor chip. The DMA data transfer may then be performed.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) fetch a reference samples from a memory to slots in a buffer, (ii) generate motion vectors by motion estimating inter-prediction candidates of a current picture relative to the reference samples in the buffer, (iii) snoop the fetches from the memory to determine if the reference samples fetched for a non-zero motion vector type of the inter-prediction candidates includes the reference samples for a zero motion vector type of the inter-prediction candidates and (iv) avoid duplication of the fetches for the zero motion vector type of the inter-prediction candidates where the snoop determines that the reference samples have already been fetched. The second circuit may be configured to evaluate the reference samples in the buffer based on the motion vectors to select a prediction sample unit made of the reference samples.

Abstract: The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for improved coordination between sender and receiver nodes in a one-sided memory access to a PGAS in a distributed computing environment. The system may include a transceiver module configured to receive a message over a network, the message comprising a data portion and a data size indicator and an offset handler module configured to calculate a destination address from a base address of a memory buffer and an offset counter. The transceiver module may further be configured to write the data portion to the memory buffer at the destination address; and the offset handler module may further be configured to update the offset counter based on the data size indicator.

Abstract: Examples are disclosed for establishing a secure destination address range responsive to initiation of a direct memory access (DMA) operation. The examples also include allowing decrypted content obtained as encrypted content from a source memory to be placed at a destination memory based on whether destination memory addresses for the destination memory fall within the secure destination address range.

Abstract: Peripheral devices may implement multiple reporting modes for signal interrupts to a host system. Different reporting modes may be determined for interrupts generated at a host system. Reporting modes may be programmatically configured for various operations at the peripheral device. Reporting modes may indicate a reporting technique for transmitting an indication of the interrupt and may indicate a priority assigned to reporting the interrupt. An interrupt controller for the peripheral device may report generated interrupts according to the reporting mode determined for the interrupts.

Abstract: A system interconnect is provided which includes a first channel configured to transmit a plurality of control signals based on a first clock, and a second channel configured to transmit a plurality of data signals which correspond to the control signals based on a second clock. The first channel and the second channel allows a predetermined range of out-of-orderness, and the predetermined range of the out-of-orderness indicates that an order of the control signals is different from an order of the data signals which correspond to the control signals.

Abstract: A method includes receiving a plurality of requests to perform accesses for associated DMA channels and arbitrating the requests. The arbitration includes selectively granting a given request of the plurality of requests based at least in part on an associated fixed priority of the request and an associated priority weighting of the request. The priority weighting regulates which request or requests of the plurality of requests are considered at a given time.

Abstract: A system and method for cross-controller data storage operations comprises interconnecting a responding storage controller and an owning storage controller with a direct memory access (DMA) capable fabric, the responding storage controller and the owning storage controller each comprising an interface from a data bus connected to the DMA capable fabric, configuring and implementing a shared DMA address space in accordance with the DMA capable fabric, the shared DMA address space including memory on the responding storage controller and the owning storage controller, the shared DMA address space being one of a symmetric or asymmetric address space, and exposing one or more local buffers of the responding storage controller and one or more local buffers of the owning storage controller through the shared DMA address space.

Abstract: Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.

Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

Abstract: A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator.