Abstract: A wireless memory device may include logic configured to detect that first data has been written by a microcontroller to a first address of a memory space of the wireless memory device; incorporate the first data into a first packet, in response to detecting that the first data has been written to the memory space, wherein the first packet includes the first address; and provide the first packet to a wireless chipset to wirelessly transmit the first packet to a destination device. The logic may be further configured to receive a second packet from the wireless chip set, wherein the second packet was received wirelessly from the destination device; retrieve a second memory address from the second packet; retrieve second data from the second packet; and write the second data to the retrieved second memory address in the memory space of the wireless memory device.

Abstract: Described herein are methods and systems for virtualization of a USB device to enable sharing of the USB device among a plurality of host processors in a multi-processor computing system. A USB virtualization unit for sharing of the USB device include a per-host register unit, each corresponding to a host processor includes one or more of a host register interface, host data interface, configuration registers, and host control registers, configured to receive simultaneous requests from one or more host processors from amongst the plurality of host processors for the USB device. The USB virtualization unit also includes a pre-fetch direct memory access (DMA) configured to pre-fetch DMA descriptors associated with the requests to store in a buffer. The USB virtualization unit further includes an endpoint specific switching decision logic (ESL) configured to schedule data access based on the DMA descriptors from the host processor's local memory corresponding to each request.

Abstract: Method for direct access to information stored in the nodes of a packet switching network comprises the steps of: collecting the pointers, corresponding to which the information required for processing the packets belonging to one and the same flow is stored in each node of the network;—constructing a distributed linked data structure (DLDS) in which the pointers are contained inside packets (PI, P2, P3) that traverse the DLDS-aware routers constituting the path between sender (A) and receiver (B) of the flow;—use of the DLDS data structure for direct access to the information stored in a DLDS-aware router, using a pointer of the DLDS contained in the packet in transit;—selection of the pointer of the DLDS contained in the packet in transit based on its position inside said packet, said position being equal to the serial number of the DLDS-aware router in the flow path, and checking of validity by consistency tests.

Abstract: Systems and methods of memory management storage to a host device are disclosed. A method is performed in a data storage device with a non-volatile memory and a controller operative to manage the non-volatile memory and to generate management data for managing the non-volatile memory. The method includes performing, at a given time, originating at the controller data management transfer to a host device or originating at the controller data management retrieval from the host device.

Abstract: A method implemented in a memory device, wherein the memory device comprises a first memory and a second memory, the method comprising receiving a direct memory access (DMA) write request from a first central processing unit (CPU) in a first computing system, wherein the DMA write request is for a plurality of bytes of data, in response to the DMA write request receiving the plurality of bytes of data from a memory in the first computing system without processing by the first CPU, and storing the plurality of bytes of data in the first memory, and upon completion of the storing, sending an interrupt message to a second CPU in a second computing system, wherein the interrupt message is configured to interrupt processing of the second CPU and initiate transfer of the plurality of bytes of data to a memory in the second computing system.

Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des

Abstract: The disclosed embodiments relate to an apparatus and method for acknowledging a data transfer. The first protocol may generate a request for a data transfer. The second protocol may receive the request for a data transfer from the first protocol. With the request, the second protocol may determine if the request for the data transfer contains a request for acknowledgement of completion of the data transfer. The second protocol may send a request corresponding to the request for data transfer to a third protocol. If the request for data transfer does contain a request for acknowledgement of completion of the data transfer, then the second protocol may set a variable in memory to wait for an event to correspond to the completion of the request and send an acknowledgement to the first protocol upon the occurrence of the event.

Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

Abstract: A method and system for managing direct memory access (DMA) in a computer system without a host input/output memory management unit (IOMMU). The computer system hosts virtual machines and allows memory overcommit. The computer receives, from a guest operating system that runs on a virtual machine, a request for mapping a guest address to a bus address. The computer translates the guest address to a host address and pins a memory page containing the host address to keep the memory page in host memory. The host address is then returned to the guest operating system to allow a device to use the host address as the bus address for direct memory access (DMA) to a buffer managed by the guest operating system.

Abstract: A system, method and computer program product for performing a method for presenting multimedia data are disclosed. The method includes but is not limited to detecting insertion of a portable storage device into a first end user device; automatically launching transfer of multimedia data and Meta data describing the multimedia data from the first end user device to the portable storage device; transferring the multimedia data from the first end user device to the portable storage device; detecting insertion of the portable storage device into a second end user device; automatically launching transfer of multimedia data and Meta data describing the multimedia data from the portable storage device to the second end user device; and transferring the multimedia data from the portable storage device to the second end user device.

Abstract: An apparatus includes an input/output (I/O) interface circuit that includes a memory and a controller. The memory stores a plurality of commands to regulate an input/output (I/O) interface. The commands indicate at least one I/O state of at least one I/O terminal of the I/O interface circuit and a time duration that is associated with the I/O state. The controller executes the commands to place the I/O interface in the the I/O state(s) in a predetermined sequence.

Abstract: An interface device includes a first proxy interface configured to carry out first direct memory access (DMA) transactions initiated by an input/output (I/O) device and a second proxy interface configured to carry out second DMA transactions initiated by a storage drive. A buffer memory is coupled between the first and second proxy interfaces and configured to temporarily hold data transferred in the first and second DMA transactions. Control logic is configured to invoke the second DMA transactions in response to the first DMA transactions so as to cause the data to be transferred via the buffer between the I/O device and the storage drive.

Abstract: A memory system controller includes one or more sockets for accommodating NVDIMM cards produced by different NVDIMM providers; a PCIe interface for coupling the memory system controller to a host; and a controller coupled to the PCIe interface over a PCIe-compliant connection and to the one or more sockets over respective DDR2 connections. The controller is configured to manage data transfers between the host and a specified one of the NVDIMM sockets in which an NVDIMM card is accommodated as DMA reads and writes, format data received from the PCIe interface for transmission to the specified NVDIMM socket over the corresponding one or more DDR2 interfaces, and initiate save and restore operations on the NVDIMM card accommodated within the specified NVDIMM socket in response to power failure and power restoration indications.

Abstract: A storage device is provided which includes a nonvolatile memory device and a controller configured to write meta information, indicating that a transfer of unit data is completed, in a buffer memory when the unit data is transferred to the buffer memory from the nonvolatile memory device.

Abstract: A system includes a serial interface, a peripheral device coupled to the serial interface, non-volatile memory, and a DMA controller including multiple linked channels. The various channels can be configured in different modes to facilitate the DMA controller performing various operations, such as data transfer, with respect to the non-volatile memory or the peripheral device.

Abstract: An interface device includes a first proxy interface configured to carry out first direct memory access (DMA) transactions initiated by an input/output (I/O) device and a second proxy interface configured to carry out second DMA transactions initiated by a storage drive. A buffer memory is coupled between the first and second proxy interfaces and configured to temporarily hold data transferred in the first and second DMA transactions. Control logic is configured to invoke the second DMA transactions in response to the first DMA transactions so as to cause the data to be transferred via the buffer between the I/O device and the storage drive.

Abstract: In order to control transfer to a processing unit of input data containing a plurality of lines stored across a plurality of memory regions including first and second memory regions, a position of a line of target of output data containing a plurality of lines output from the processing unit is specified. A number of lines of input data to be transferred from the first memory region and their addresses are determined, and a number of lines of input data to be transferred from the second memory region and their addresses are determined, based on the specified position of the line of target. Control is performed based on the determination result such that input data for a number of lines may be transferred from the first memory region and input data for a number of lines may be transferred from the second memory region.

Abstract: A set of techniques is described for performing input/output (I/O) between a guest domain and a host domain in a virtualized environment. A pool of memory buffers is reserved for performing virtualized I/O operations. The reserved pool of memory buffers has static mappings that grant access to both the guest domain and the host domain. When a request to perform an I/O operation is received, the system can determine whether the memory buffers allocated to the I/O operation belong to the reserved pool. If the buffers are in the reserved pool, the host domain executes the I/O operation using the buffers without the need to map/unmap the buffers and perform TLB flushes. If the buffers are not in the reserved pool, the system can either copy the data into the reserved pool or perform the mapping and unmapping of the memory buffers to the address space of the host domain.

Abstract: An approach is provided in which a virtual function, which executes on a network adapter, receives a data packet from a first virtual machine. A translation entry is identified that corresponds to sending the data packet from the first virtual machine to a second virtual machine, and a determination is made as to whether an onboard memory partition assigned to the virtual function includes the identified translation. If the onboard memory location includes the translation entry, the data packet is sent to the destination virtual machine using the translation entry retrieved from the onboard memory partition. Otherwise, if the translation entry is not located in the onboard memory partition, the data packet is sent to the destination virtual machine using a translation entry retrieved from an off board memory location.

Abstract: Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating.

Abstract: A system and method for providing a message bus component or version thereof (referred to herein as an implementation), and a messaging application program interface, for use in an enterprise data center, middleware machine system, or similar environment that includes a plurality of processor nodes together with a high-performance communication fabric (or communication mechanism) such as InfiniBand. In accordance with an embodiment, the messaging application program interface enables features such as asynchronous messaging, low latency, and high data throughput, and supports the use of in-memory data grid, application server, and other middleware components.

Abstract: Various systems, processes, and products may be used to manage the transmission and reception of messages. In particular implementations, a system, process, and product for managing message transmission and reception may include the ability to receive a plurality of messages to be transmitted over a communication network, wherein some of the messages have a higher priority and some of the messages have a lower priority, and enqueue descriptors for the messages in a direct memory access queue. The system, process, and product may also include the ability to determine whether an overrun of the queue has occurred, analyze the queue if an overrun has occurred to determine if lower priority messages are associated with any of the descriptors in the queue, and replace, if descriptors for lower priority messages are in the queue, the descriptors for the lower priority messages with descriptors for higher priority messages.

Abstract: An electronic device and data control method are provided. The electronic device includes a connector which is connected to an external storage medium storing media data therein; an identification unit which identifies a storage identifier (ID) of the external storage medium connected to the connector; and a controller which performs a media function corresponding to the media data stored in the external storage medium whose storage ID is identified by the identification unit.

Abstract: An external memory interface includes an input/output (IO) logic unit operable to convert a rate of data from a first rate corresponding to a memory controller/schedule unit to a second rate corresponding to an external memory device. The external memory interface also includes a latency adjustment unit, operating in a timing domain of the memory controller/schedule unit, operable to add between 1 to [(second rate/first rate)?1] cycles of latency of the second rate.

Abstract: An audio device and a method of operating the same are provided. The audio device includes a storage unit, a first memory and a second memory, a hardware decoder, a software decoder, a first direct memory access (DMA) block, a second DMA block, and a controller. The controller converts the audio device from an ultra low power mode in which the first PCM information is transmitted to an audio interface buffer through the first memory, the hardware decoder, and the first DMA block or a low power mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the first DMA block to a normal mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the second DMA block.

Abstract: A universal serial interface (USI) includes two transceivers configured to separately support a plurality of serial communication standards; a buffer configured to store received data and data to be transmitted; and a transceiver controller configured to connect one of the two transceivers to the buffer based on a configuration signal received from outside of the USI.

Abstract: The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptors1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. 1 Descriptors are set of instructions that is used to activate the DMA controller. By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.

Abstract: A method includes processing descriptors to control a direct memory access (DMA) channel. The method includes synchronizing at least part of the processing, which includes processing a first descriptor of the descriptors to cause the execution to selectively pause based on a trigger value.

Abstract: Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address.

Abstract: A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

Abstract: A system and method operable to manage misaligned direct memory access (DMA) data transfers is provided. This method involves determining a delta between N bytes of data to be copied from within a local side buffer (source location) to a remote buffer (destination location). After the delta is determined a tail of the same length is copied to temporary storage. Then the N bytes of data on the local side buffer minus the tail will be shifted to align the N bytes of data to be copied from within the local side buffer to the starting address of the destination location in the remote buffer. The pre-shifted N bytes of data within the local side buffer may be DMA transferred to the remote buffer. The tail transferred to temporary storage may then be copied from temporary storage to the remote buffer.

Abstract: A method for data cryptography includes accepting input data, which contains a section that is to undergo a cryptographic operation and starts at an offset with respect to a beginning of the input data, by a Direct Memory Access (DMA) module. The input data is aligned by the DMA module to cancel out the offset. The aligned input data is read out of the DMA module, and the cryptographic operation is performed on the section.

Abstract: A mobile device chip is provided. The mobile device chip includes a main processor, a multimedia processor, and a direct memory access (DMA) circuit. The multimedia processor is electrically coupled to the main processor. The DMA circuit accesses storage, and the DMA circuit is electrically coupled to the multimedia processor. When the mobile device chip operates in a normal mode, the main processor provides file accessing information of at least part of an audio file stored in the storage to the multimedia processor. When the mobile device chip operates in a power-saving mode, the multimedia processor obtains the data of the at least part of the audio file stored in the storage through the DMA circuit according to the file accessing information provided by the main processor.

Abstract: Embodiments of the invention describe systems, apparatuses and methods that enable sharing Remote Direct Memory Access (RDMA) device hardware between a host and a peripheral device including a CPU and memory complex (alternatively referred to herein as a processor add-in card). Embodiments of the invention utilize interconnect hardware such as Peripheral Component Interconnect express (PCIe) hardware for peer-to-peer data transfers between processor add-in cards and RDMA devices. A host system may include modules or logic to map memory and registers to and/or from the RDMA device, thereby enabling I/O to be performed directly to and from user-mode applications on the processor add-in card, concurrently with host system I/O operations.

Abstract: A data processing device includes a memory, a direct memory access controller including a receiving module configured to receive data coming from outside the device and for writing the data in a main buffer memory of the memory, and a processing unit programmed to read and process data written by the receiving module in a work area of the main buffer memory. The main buffer memory is divided between a used space, where the receiving module is configured not to write, and free space, where the receiving module is configured to write. The processing unit is further programmed to define the work area, and the direct memory access controller includes a buffer memory manager configured to free data written in the main buffer memory, by defining a location of this data as a free space, only when this data is outside the work area.

Abstract: Provided are a computer program product, system, and method for selecting Direct Memory Access (DMA) engines in an adaptor for processing Input/Output requests received at the adaptor. A determination is made of an assignment of a plurality of processors to the DMA engines, wherein each processor is assigned to use one of the DMA engines. I/O request related work for a received I/O request directed to the storage is processed by determining the DMA engine assigned to the processor processing the I/O request related work and accessing the determined DMA engine to perform the I/O related work.

Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.

Abstract: A system and method are disclosed for processing commands to network target devices through a SCSI router in a Fiber Channel network having a plurality of Fiber Channel hosts. The system may be configured to receive a command, and determine that the command requires a transfer of data larger than a threshold size. The system may also be configured to receive a plurality of data blocks associated with the command, store the plurality of data blocks in at least one buffer, and determine if there is an initial amount of data in the at least one buffer. The system may be further configured to forward at least one of the plurality data blocks, and request an additional data block associated with the command.

Abstract: An application processor includes a system memory unit, peripheral devices, a control unit and a central processing unit (CPU). The system memory unit includes one page table. The peripheral devices share the page table and perform a DMA (Direct Memory Access) operation on the system memory unit using the page table, where each of the peripheral devices includes a memory management unit having a translation lookaside buffer. The control unit divides a total virtual address space corresponding to the page table into sub virtual address spaces, assigns the sub virtual address spaces to the peripheral devices, respectively, allocates and releases a DMA buffer in the system memory unit, and updates the page table, where at least two of the sub virtual address spaces have different sizes from each other. The CPU controls the peripheral devices and the control unit. The application processor reduces memory consumption.

Abstract: A storage device is provided which includes a nonvolatile memory device and a controller configured to write meta information, indicating that a transfer of unit data is completed, in a buffer memory when the unit data is transferred to the buffer memory from the nonvolatile memory device.

Abstract: Systems and methods that can facilitate an expedient and efficient transfer of data between memory components (e.g., flash memory) and host components (e.g., multimedia cards, secure digital cards, etc.) are presented. A memory controller component can be employed to facilitate transferring between the memory components and host components by utilizing a multi-bus architecture. A controller first bus can be utilized for code that can be executed by a controller processor while a controller second bus can be designated for the transfer of data to the mass storage devices. By architecting the memory controller component with two buses, this innovation can provide a higher data throughput than conventional memory controllers.

Abstract: Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an instruction that when executed causes a cache line to be accessed. In response to execution of that instruction, an indicator associated with the group of instructions is updated to indicate that the cache line has been accessed. The cache line is indicated as having been accessed until execution of the group of instructions is ended.

Abstract: A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments.

Abstract: Methods and apparatus for storing and delivering compressed data are disclosed. In one embodiment, a direct memory access (DMA) unit with a lossless coder/decoder (CODEC) receives uncompressed data. The direct memory access unit then compresses the uncompressed data to produce lossless compressed data, and stores the lossless compressed data in a memory, wherein the compressing operation and the storing operation are each part of a direct memory access (DMA) write operation. In another embodiment, the direct memory access (DMA) unit receives lossless compressed data. The direct memory access unit then decompresses the compressed data to produce lossless decompressed data, and delivers the decompressed data to an output device, wherein the decompressing operation and the receiving operation are each part of a direct memory access (DMA) read operation.

Abstract: The present invention is a method for accelerating proxy Input/Output (proxy I/O). The method includes the step of receiving a command at a primary target storage system. The primary target storage system may be part of a clustered storage array. The command may be a command which was transmitted by an initiator system via a storage area network, and may include a request for data. The method further includes the step of forwarding the command to a session layer of the primary target storage system. Further, when a virtualization layer of the primary target storage system determines that a portion of the data requested in the data request is not stored by the primary target storage system, but is stored by a proxy target storage system included in the plurality of storage systems, the method further includes providing a proxyIO request to a proxy initiator of the primary target storage system.

Abstract: A method and system for copying data within a guest using a direct memory access (DMA) engine. A computer system hosts a hypervisor and a guest. The hypervisor detects an inquiry of the guest about a DMA engine. In response to the inquiry, the hypervisor indicates to the guest that a DMA engine is available. The hypervisor then receives a DMA request from the guest, the DMA request indicating a source address and a target address for copying data. Both the source address and the target address are within an address space allocated to the guest. Based on one or more data transfer policies, the hypervisor determines whether to direct the DMA engine to copy the data for the guest.

Abstract: A multicore system 2 includes a main system program 610 that operates on a first processor core 61 and stores synthesized audio data, which is mixed audio data, to a buffer for DMA transfer 63, a standby program 620 that operates on a second processor 62, and an audio output unit 64 that sequentially stores the synthesized audio data transferred from the buffer for DMA transfer 63 and plays the stored synthesized audio data. When an amount of storage of the synthesized audio data stored to the buffer for DMA transfer 63 has not reached a predetermined amount of data determined according to the amount of storage of the synthesized audio data stored to the audio output unit 64, the standby system program 620 takes over and executes the mixing and the storage of the synthesized audio data that is executed by the main system program 610.

Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

Abstract: A data transfer device includes a transmitter, a receiver, and a monitor. The transmitter transmits data by non-handshake communication, and the receiver receives the data transmitted from the transmitter. Further, the monitor is provided separately from the receiver, and monitors a size of data received by the receiver to notify the transmitter of a result of monitoring.

Abstract: A method according to one embodiment includes the operations of configuring a primary receive queue to designate a first plurality of buffers; configuring a secondary receive queue to designate a second plurality of buffers, wherein said primary receive queue is sized to accommodate a first network traffic data rate and said secondary receive queue is sized to provide additional accommodation for burst network traffic data rates; selecting a buffer from said primary receive queue, if said primary receive queue has buffers available, otherwise selecting a buffer from said secondary receive queue; transferring data from a network controller to said selected buffer; indicating that said transferring to said selected buffer is complete; reading said data from said selected buffer; and returning said selected buffer, after said reading is complete, to said primary receive queue if said primary receive queue has space available for the selected buffer, otherwise returning said selected buffer to said secondary rece