Abstract: Methods and structure for formatting and processing Scatter Gather Lists (SGLs). One exemplary embodiment is a storage controller that includes a cache memory storing data for a logical volume, and a control unit. The control unit is able to service an Input/Output (I/O) request based on a Scatter Gather List (SGL) that refers to the cache memory, the SGL comprising multiple entries that each include a flag field and an identifier (ID) field. The entries are assigned to categories that are each associated with a different set of stored processing instructions. The control unit is able to identify a category for an entry based on a combination of both flag field and ID field for the entry, and the control unit is able to process the entry using the set of instructions associated with the identified category.

Abstract: In a memory controller having a controller core and a physical signaling interface, the controller core outputs a request for read data to the physical signaling interface specifying one of at least two memory components from which the read data is to be retrieved. In response to the request for read data, the physical signaling interface outputs a memory read request to the specified memory component, receives the read data from the specified memory component, and transfers the read data to the controller core at either a first time or a second time according to whether the specified memory component is a first memory component or second memory component of the at least two memory components.

Abstract: A method maintaining a fixed QoS for a PCIe device accessed by multiple hosts includes; receiving commands from the hosts in PCIe function queues of the PCIe device, fetching the commands from the PCIe function command queues, queuing the commands according to a command arbitration policy established for the PCIe device, storing the queued commands in an internal memory of the PCIe device, retrieving the queued commands from the internal memory in a sequence determined by applying a calculated QoS to at least one of the queued commands, and allocating PCIe device resources based on payload information corresponding to each one of the retrieved commands.

Abstract: An interface unit is provided for the arrangement between a bus system, to which a processor unit and a data memory are connectable, and a data transporting unit, in particular a network processor, are described. The interface unit carries out a direct memory access to the data memory as a function of an identifier (chid) previously agreed upon between an application and the data transporting unit.

Abstract: A multi-queue cache is configured with an initial configuration, where the initial configuration includes one or more queues for storing data items. Each of the one or more queues has an initial size. Thereafter, the multi-queue cache is operated according to a multi-queue cache replacement algorithm. During operation, access patterns for the multi-queue cache are analyzed. Based on the access patterns, an updated configuration for the multi-queue cache is determined. Thereafter, the configuration of the multi-queue cache is modified during operation. The modifying includes adjusting the size of at least one of the one or more queues according to the determined updated configuration for the multi-queue cache.

Abstract: Apparatuses and methods for modifying data stored on a disk are provided. A buffer comprises a FIFO queue. The FIFO queue includes a plurality of buffer lines for queuing data units in a predetermined order. A controller is configured to write data units from the disk to respective buffer lines of the FIFO queue. The controller is further configured to perform read-modify-write (RMW) operations to modify the data units written to the queue. Each RMW operation includes (i) popping a data unit from a buffer line of the queue based on a location of a read pointer, (ii) performing a mathematical or logic operation to modify the data unit that is popped from the queue, and (iii) pushing the modified data unit into the queue. The modified data unit is written to a buffer line of the queue based on a location of a write pointer.

Abstract: A low latency digital clock fault detector has an edge detector including a delay line generating pulses on edges o an incoming clock signal of a width determined by the length of said delay line. A watchdog timer with flip-flops in a pipeline configuration has a first input held at a static logic level, a second input receiving a reference clock, and a third reset input. The watchdog is being responsive to the pulses to maintain a stable output in the presence of said pulses and generate a fault indication in the absence of the pulses.

Abstract: A system and method can support efficient packet processing in a network environment. The system can comprise a direct memory access (DMA) resources pool that comprises one or more of DMA resources. Furthermore, the system can use a plurality of packet buffers in a memory, wherein each said DMA resource can point to a chain of packet buffers in the memory. Here, the chain of packet buffers can be implemented based on either a linked list data structure and/or a linear array data structure. Additionally, each said DMA resource allows a packet processing thread to access the chain of packet buffers using a pre-assigned thread key.

Abstract: A method and apparatus for handling incoming data frames within a network interface controller. The network interface controller comprises at least one controller component operably coupled to at least one memory element. The at least one controller component is arranged to identify a next available buffer pointer from a pool of buffer pointers stored within a first area of memory within the at least one memory element, receive an indication that a start of a data frame has been received via a network interface, and allocate the identified next available buffer pointer to the data frame.

Abstract: Herein are data storage devices to transfer a reference of a data object during a storage operation. These data storage devices include a host controller configured to obtain a reference of an object stored in a shared memory system for writing to a storage media controlled by a drive controller. To the drive controller, the host controller transfers the reference of the object in the memory system. The host controller transfers a storage command to the drive controller to write the object to the storage media. The drive controller may be configured to transfer a reference of an object read into the memory system.

Abstract: A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

Abstract: A data deployment determination apparatus includes a correlation information creation processor that creates correlation information in which addresses indicating areas in a first memory are correlated with frequency information on memory accesses for the respective addresses, from trace information on a memory access to the first memory, a time reduction calculation processor that calculates, for each of the addresses, time reduction in memory accesses to data stored in the first memory based on the correlation information when data stored in the first memory is stored in a second memory which is a memory having a larger bandwidth than the first memory, and a data deployment determination processor that determines that first data stored in the address of which the time reduction is larger than the time reduction corresponding to second data stored in the address is to be stored in the second memory in preference to the second data.

Abstract: Systems and methods for hypervisor scheduling of polling tasks are disclosed. In one implementation, responsive to determining that no input/output (I/O) worker tasks associated with virtual machines are running on a processor of a host computer system running a plurality of virtual machines, callback dispatcher task may be invoked by the processor. The callback dispatcher task may identify an entry of a callback list, wherein the entry references an input/output (I/O) worker task associated with a virtual machine of the plurality of virtual machines. The callback dispatcher task may further invoke a callback code referenced by the entry of the callback list. Responsive to identifying a pending I/O request, the callback code may wake up the input/output (I/O) worker task associated with the entry of the callback list.

Abstract: A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator. In some configurations, a single multiple SDIO (MSDIO) command may cause two or more SDIO units to return data to a host.

Abstract: Power supply of ECUs connected to a communication network is optimally controlled so that power consumption is reduced. A transceiver/receiver converts a message of a differential signal received via a CAN bus into a digital signal. A select circuit determines whether the converted message is in a CAN format or a UART format. If it is in the UART format, the select circuit outputs a message to the UART circuit. A UART circuit determines whether the message matches a UART format. If matched, an ID determination circuit determines whether the input message is specifying a CAN ID of its own ECU. If it is the CAN ID of the ECU, the ID determination circuit outputs an enable signal to turn on a regulator and supply power to an MCU and an actuator.

Abstract: A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of rewriting data, a plurality of word lines connected to the plurality of memory cells, a page including the plurality of memory cells connected to the same word line, a plane including a plurality of pages, a memory cell array including a plurality of planes, and a plurality of word line drivers which apply voltages to the plurality of word lines, and a plurality of switches provided for each plane and which assigns the word line drivers to the word lines.

Abstract: A method begins by a storage unit of a dispersed storage network (DSN) executing transitioning storage of one or more groups of encoded data slices. The method continues while transitioning storage of the one or more groups of encoded data slices with the storage unit receiving a proxied data access request regarding an encoded data slice from another storage unit of the DSN. The method continues by the storage unit determining whether the other storage unit is an authentic storage unit of the DSN based on at least one of the encoded data slice, a previous version of the distributed agreement protocol, and a new version of the distributed agreement protocol. The method continues by when the other storage unit is the authentic storage unit, processing the proxied data access request to produce a data access response and sending the data access response to the other storage unit.

Abstract: Examples are disclosed for establishing a secure destination address range responsive to initiation of a direct memory access (DMA) operation. The examples also include allowing decrypted content obtained as encrypted content from a source memory to be placed at a destination memory based on whether destination memory addresses for the destination memory fall within the secure destination address range.

Abstract: An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests.

Abstract: A data cache system is provided. The system includes a central processing unit (CPU), a memory system, an instruction track table, a tracker and a data engine. The CPU is configured to execute instructions and read data. The memory system is configured to store the instructions and the data. The instruction track table is configured to store corresponding information of branch instructions stored in the memory system. The tracker is configured to point to a first data read instruction after an instruction currently being executed by the CPU. The data engine is configured to calculate a data address in advance before the CPU executes the data read instruction pointed to by the tracker. Further, the data engine is also configured to control the memory system to provide the corresponding data for the CPU based on the data address.

Abstract: A data storage device includes a nonvolatile memory device; a buffer memory for storing temporarily data to be transmitted from the nonvolatile memory device to a host device or data to be transmitted from the host device to the nonvolatile memory device; a memory control unit for performing a control operation for controlling the nonvolatile memory device; and a direct memory access (DMA) unit for performing a data transmission operation associated with the buffer memory, according to control of the memory control unit, wherein the DMA block transmits a first data from the nonvolatile memory device to the buffer memory, and wherein the DMA unit transmits a second data from the nonvolatile memory device to the buffer memory, while the first data stored in the buffer memory is transmitted from the buffer memory to the host device.

Abstract: An electronic system that can automatically set a report rate, which comprises: a first electronic apparatus; a second electronic apparatus; a transmitting interface, wherein the second electronic apparatus transmits data to the first electronic apparatus via the transmitting interface; and a processing unit, for automatically setting a report rate of the second electronic apparatus or the transmitting interface according to a type of a software program that the first electronic apparatus executes. The type of the software program can be replaced by other factors.

Abstract: A mobile vehicle communication system and a method carried out by the system to determine at a remotely-located vehicle a performance criteria of a communication network connection in the vehicle. Steps of the method include: monitoring the vehicle's communication network connection for at least one of a plurality of parameters, wherein the plurality of parameters are associated with the performance criteria of the network connection; correlating a performance status test indicative of the performance criteria of the network connection with at least one of the plurality of parameters; and determining the performance criteria of the network connection based on the correlation.

Abstract: Methods and apparatus for efficient peer-to-peer communication support in interconnect fabrics. Network interfaces associated with agents are implemented to facilitate peer-to-peer transactions between agents in a manner that ensures data accesses correspond to the most recent update for each agent. This is implemented, in part, via use of non-posted “dummy writes” that are sent from an agent when the destination between write transactions originating from the agent changes. The dummy writes ensure that data corresponding to previous writes reach their destination prior to subsequent write and read transactions, thus ordering the peer-to-peer transactions without requiring the use of a centralized transaction ordering entity.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes a first interface configured to receive a read request and a number of dependent write requests that the read request depends on from the requesting interconnect; and an issuer configured to issue the received number of dependent write requests to the serving interconnect and for issuing the received read request to the serving interconnect after issuing the number of dependent write requests and before receiving write acknowledgments for the issued dependent write requests from the serving interconnect.

Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.

Abstract: A shared counter resource, such as a register, is disclosed in the hardware, where the register representing how much free space there is in the command queue is accessible to one or more processing elements. When a processing element reads the “reservation” register, the hardware automatically decrements the available free space by a preconfigured amount (e.g., 1) and returns the value of the free space immediately prior to the read/reservation. If the read returns 0 (or a number less than the preconfigured amount), there was insufficient free space to satisfy the request. In the event there was insufficient space to satisfy the request the reservation register may be configured to reserve however much space was available or to not reserve any space at all. Any number of processing elements may read these registers and various scenarios are described where the input and output queues are accessible via various processing elements.

Abstract: A system and method for interpolating between pixels of an image for providing zoom and pan features. A piecewise cubic spline is used to find the values of each of four provisional interpolation points in each of four rows of an image and, similarly, a piecewise cubic spline is used to interpolate between the provisional interpolation points to find the value of a point in the output image. Boundary conditions used to constrain the coefficients of the piecewise cubic spline provide enhanced quality in the output image.

Abstract: Accessing a circular buffer in memory from a processor may be performed with the aid of precomputed values stored in a pointer descriptor field of a processor storage element, such as a register. The pointer descriptor may store a precomputed value for calculating a memory address in the circular buffer, which may include two values, in which the two values are based, at least in part, on the size of the circular buffer, but neither be the size of the circular buffer. The first value may be used to derive a starting memory location for a circular buffer. The second value may be used in combination with the first value to calculate an end memory location. The start and end locations or addresses, along with the precomputed stored values, are then used to calculate the next address based on the current address of a circular buffer in an efficient manner.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes a first interface configured to receive a read request and a number of dependent write requests that the read request depends on from the requesting interconnect; and an issuer configured to issue the received number of dependent write requests to the serving interconnect and for issuing the received read request to the serving interconnect after issuing the number of dependent write requests and before receiving write acknowledgments for the issued dependent write requests from the serving interconnect.

Abstract: To select a master controller from a plurality of controllers, a computing system may consider whether connections between components within field replaceable units (FRUs) are functional as well as the data dependencies between the FRUs. For example, in addition to identifying whether the connections between the FRUs and the controllers are functional, the computing system sends instructions to each of the FRUs coupled to the controllers to determine if inter- and intra-FRU connections required for booting a compute node hosting the FRUs are functional. For instance, one FRU may depend on data from another FRU in order to boot. If a communication link between the FRUs is non-functional, the compute node may fail to boot. The computer system uses these evaluations to determine which of the controllers to select as the master.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Technologies are generally described for methods, systems, and processors effective to migrate a thread. The thread may be migrated from the first core to the second core. The first and the second core may be configured in communication with a first cache. The first core may generate a request for a first data block from the first cache. In response to a cache miss in the first cache for the first data block, the first core may generate a request for the first data block from a memory. The first core may coordinate with a second cache to store the first data block in the second cache. The thread may be migrated from the second core to a third core. The second core and third core may be configured in communication with the second cache.

Abstract: A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

Abstract: An embodiment of the disclosure relates to the field of data transmission, in particular to a data transmission method and a data transmission device, for solving the problems of low data transmission efficiency and poor Direct Memory Access (DMA) performance in a method of arbitrating each DMA channel in a round-robin mode and transmitting data according to an arbitration result. The method in the embodiment of the disclosure includes that: for each DMA channel, an arbitration unit corresponding to the channel among a plurality of arbitration units is determined according to transmission performance corresponding to data in the channel; and when data in channels corresponding to at least two arbitration units need to be transmitted, the data are transmitted according to priorities of the at least two arbitration units.

Abstract: A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.

Abstract: An operating system that includes an image processing framework as well as a job management layer is provided. The image processing framework is for performing image processing operations and the job management layer is for assigning the image processing operations to multiple concurrent computing resources. The computing resources include several processing units and one or more direct memory access (DMA) channels for concurrently rendering image data and transferring image data between the processing units.

Abstract: One embodiment relates to an integrated circuit for a multiple-channel direct memory access system. The integrated circuit includes multiple direct memory access (DMA) controllers, each one corresponding to a different DMA channel. A channelizer receives descriptors from the DMA controllers. Fragmentation circuits in the channelizer fragment descriptors to generate multiple sub-descriptors therefrom, and the sub-descriptors may be sorted into priority queues. Another embodiment relates to a method of providing DMA transfers for multiple DMA channels using an integrated circuit. Another embodiment relates to a system for multiple-channel direct memory access. Other embodiments and features are also disclosed.

Abstract: Provided are a computer readable storage media, method, and system for gathering sensed data from devices to manage host command transmission and cooling of the device. Host commands are retrieved from a host memory in a host to perform Input/Output operations with respect to a device. The retrieved host commands are transmitted to the device to perform the I/O operations of the host command. A monitor command is transmitted to obtain sensed data from the device while processing the host commands. A rate of transmitting the host commands is adjusted in response to determining that the sensed data received from the device in response to the monitor command satisfies a condition.

Abstract: In an embodiment of the invention, a method comprises: A method, comprising: issuing, by a Direct Memory Access (DMA) engine, an update request to a dependency table if the DMA engine has finished executing a first descriptor; and issuing, by the DMA engine, a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table.

Abstract: Embodiments are directed to routing requests with different protocols to the same destination. In one scenario, a computer system receives a request that uses a specified protocol. The request includes a request source identifier and a request destination identifier. The computer system identifies, based on both the request source identifier and the request destination identifier, a destination to send the request to and generates a routing entry for the request that indicates which destination the first request was sent to. The computer system receives another request that uses a different protocol. This request includes a request source identifier and a request destination identifier of its own. The computer system determines that the request source identifier and request destination identifier of the subsequent request match those of the generated routing entry, and routes the subsequent request to the destination indicated in the routing entry.

Abstract: A user station for a bus system is described and a method for transmitting messages between user stations of a bus system. The user station has a CAN-Controller for reading data of a message to be sent directly from a RAM without buffer storage in a buffer store, and a memory access error detection/processing device for detecting a memory access error of the CAN controller and for processing a detected memory access error.

Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.

Abstract: Systems and methods are provided for supporting use of non-volatile memory (NVM) on a double data rate (DDR) memory channel for an information handling system so that non-volatile memory devices (e.g., such as Phase Change Memory “PCM” devices) may be employed for main memory usage. In one possible implementation, information handling system memory reads may be managed directly in hardware as memory semantics via use code, while memory writes may be separately handled, e.g., via an operating system (OS)/driver. In another possible implementation, both DRAM-based and NVM-based memory systems may be populated for an information handling system.

Abstract: An apparatus and associated methodology providing a data storage system operably transferring data between a storage space and a remote device via a network. The data storage system includes a first storage controller having top-level control of a first data storage device and a second storage controller having top-level control of a second data storage device that is different than the first data storage device, the first and second data storage devices forming portions of the storage space. Data pathway logic resides in the first storage controller that performs a direct memory access (DMA) transfer to the second data storage device at a DMA data transfer rate in response to the first storage controller receiving, from the external device via the network, an access request for the second data storage device.

Abstract: A mechanism is described for facilitating improved copying of graphics data at computing devices according to one embodiment. A method of embodiments, as described herein, includes detecting a first data having a first set of primitives at a one-dimensional (“1D”) source buffer. The first data is detected to be copied to a 1D destination buffer. The method may further include re-describing the 1D source buffer and the 1D destination buffer into a two-dimensional (“2D”) source buffer and a 2D destination buffer, respectively, where re-describing may include re-describing the first data having the first set of primitives to a second data having a second set of primitives. The method may further include copying the second data having the second set of primitives from the 2D source buffer to the 2D destination buffer.

Abstract: In the data storage system the storage area network performs XOR operations on incoming data for parity generation without buffering data through a centralized RAID engine or processor. The hardware for calculating the XOR data is distributed to incrementally calculate data parity in parallel across each data channel and may be implemented as a set of FPGAs with low bandwidths to efficiently scale as the amount of storage memory increases. A host adaptively appoints data storage controllers in the storage area network to perform XOR parity operations on data passing therethrough. The system provides data migration and parity generation in a simple and effective matter and attains a reduction in cost and power consumption.

Abstract: A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA channels includes receiving at a network traffic management device first and second network packets from respective first and second DMA channels. The received packets are segmented into respective one or more constituent CPU bus packets. The segmented constituent CPU bus packets are interleaved for transmission across a packetized CPU bus.

Abstract: A memory system according to the present embodiment includes a memory controller including a first data bus and a first address bus. A memory part includes a second data bus and a second address bus. A bridge part is capable of receiving an address from the memory controller via the first data bus, and outputs the address via the first address bus to the memory part.

Abstract: A method begins by a dispersed storage (DS) processing module ascertaining processing speeds of distributed storage and task (DST) execution units where the DST execution units receive a set of encoded data slices that includes a sub-set of data-based data slices. The method continues with the DS processing module allocating task performance on the sub-set of data-based data slices to a sub-set of DST execution units, where a first DST execution unit is allocated to perform a first partial task on a first data-based data slice of the sub-set of data-based data slices. When a second DST execution unit has a processing speed that is a threshold speed greater than a processing speed of the first DST execution unit, the method continues with the DS processing module identifying at least one encoded block of the first data-based data slice for transferring processing responsibilities to the second DST execution unit.