Abstract: Mechanisms for migration of a virtual endpoint from one virtual plane to another are provided. With these mechanisms, when a management application requests migration of a virtual endpoint (VE) from one virtual plane (VP) to another, a fabric manager provides an input/output virtualization intermediary (IOVI) with an interrupt to perform a stateless migration. The IOVI quiesces outstanding requests to the virtual functions (VFs) of the VE, causes a function level reset of the VFs, deconfigures addresses in intermediary switches corresponding to the VP, and informs the fabric manager that a destination migration is requested. The fabric manager sends an interrupt to the destination IOVI which performs a function level reset of the destination VFs and reprograms the intermediary switches with the addresses of the destination VP. The destination VFs may then be placed in an active state.

Abstract: An asymmetric multiprocessor capable of increasing a degree of freedom of distributed processing, minimizing a processing load on each processor (CPU), and achieving a large reduction in power consumption by reducing an operating frequency or lowering the power supply voltage. An asymmetric multiprocessor includes a hardware resource mediator that mediates request signals requesting permission to use arbitrary hardware accelerators from CPU cores. A signal processing content selector selects signal processing content of a dynamically reconfigurable signal processor that is connected as a slave A clock skew mediator arbitrarily shifts a clock phase relationship among groups, while clock delay generators delay a clock signal based on a clock skew selection enable signal.

Abstract: A reader-writer lock is provided that scales to accommodate multiple readers without contention. The lock comprises a hierarchical C-SNZI (Conditioned Scalable Non-Zero Indicator) structure that scales with the number readers seeking simultaneous acquisition of the lock. All readers that have joined the C-SNZI structure share concurrent acquisition, and additional readers may continue to join until the structure is disabled. The lock may be disabled by a writer, at which time subsequent readers will wait (e.g., in a wait queue) until the lock is again available. The C-SNZI structure may be implemented in a lockword or in reader entries within a wait queue. If implemented in reader entries of a wait queue, the lockword may be omitted, and new readers arriving at the queue may be able join an existing reader entry even if the reader entry is not at the tail of the queue.

Abstract: A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means.

Abstract: According to an aspect of an embodiment, an apparatus has a pair of first system boards, each of the first system boards including a processor and being adapted for sending duplicate requests, in parallel, respectively, a second system board including a processor and being adapted for sending requests, a first transfer device for transferring requests, having a first arbiter for selecting and outputting one of the duplicate requests sent from each of the first system boards, and a second arbiter for selecting and outputting one of the requests sent from the second system board and a second transfer device for transferring requests, having a third arbiter for selecting one of the duplicate requests sent from each of the first system boards and outputting the selected request in synchronization with the selected request outputted by the first arbiter, the second transfer device having a forth arbiter.

Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: A resource and partition manager of the preferred embodiments includes a lock mechanism that operates on a plurality of locks that control access to individual I/O slots. The resource and partition manager uses the lock mechanism to obtain a lock on an I/O slot when transferring control of the I/O slot to a logical partition that is powering on and when removing the I/O slot from a logical partition that is powering off. The resource and partition manager uses the lock mechanism to remove control of an I/O slot from, or return control to, an operating logical partition in order to facilitate hardware service operations on that I/O slot or on the physical enclosure in which it is contained.

Abstract: A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: A method and an apparatus that synchronize an application state in a client with a data source in a backend system in an asynchronous manner are described. A response is sent to the client based on a priority determined according to a history of received update requests. When a notification message from a data source in a backend system is received, an update request is selected from a plurality of update requests currently pending to be served according to the priority associated with each update request. A response is sent to the client over a network corresponding to the selected update request. The response includes state updates according to the changes in the data source and the current application state in the corresponding client.

Abstract: A processing device includes a processor which executes first and second pieces of control software in a memory to perform processing, and a device 1 having a plurality of SLOTs 1 to 8 to electrically connect the processor to a plurality of device. The device 1 switches a SLOT which connects devices 2 and 3 between a SLOT 1 or 2 and a spare SLOT 8 allocated in advance through a switch. The processor executes the first and second pieces of control software to manage SLOT information including pieces of path information obtained through the SLOTs 1, 2, and 8 between the devices 1 and 2 such that the SLOT information can be registered and updated. When a failure occurs in the SLOT 1 or 2, the processor updates the path information obtained through the SLOT 1 into the path information obtained through the spare SLOT, and the SLOT which connects the devices 2 and 3 is switched from the SLOT 1 or 2 to the spare SLOT 8.

Abstract: Bus transfer efficiency is improved in bus communication that uses a shared memory, based on a communication origin master 101 selectively using an arbitration completion notification signal and a memory access completion notification signal. Based on the arbitration completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12. Based on the memory access completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12.

Abstract: A plurality of nodes are coupled via a serial data bus A transition from a first state to a second state is repeatedly transmitted onto the bus from a node arbitrarily selected from the plurality of nodes and is defined as the bit master. One or more of the nodes transmits onto the bus dominant and recessive states at a first predetermined time after each transition. The transmitted states represent respective dominant and recessive bits of an attempted message. The plurality of nodes detect dominant and recessive states of the bus at a second predetermined time after each transition. Any of the one or more nodes that transmits a recessive bit at the first predetermined time and detects a dominant bit at the second predetermined time ceases transmission of bits onto the bus.

Abstract: A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.

Abstract: A method for providing access arbitration for an integrated circuit in a wireless device is provided. The method includes receiving a command from a processing element coupled to the integrated circuit. A preempt signal associated with the command is generated. The preempt signal is operable to identify a priority for the command as one of high and low. The preempt signal is provided to an access arbiter for use in providing access arbitration for the command.

Abstract: A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.

Abstract: A computer system associated with a plurality of interrupt sources that produce interrupt signals may include interrupt signal processing blocks corresponding to the interrupt sources, respectively. Each of the interrupt processing blocks can include: a counter for generating an interrupt count value associated with the number of interrupt signals received from the corresponding interrupt source; a first register for storing the interrupt count value; a logic circuit for to generate an interrupt request signal according to the interrupt count value; and a second register for storing a service routine address associated with the interrupt source.

Abstract: A pipelined device and method for executing transactions in a pipelined device, the method includes: setting limiter thresholds that define a maximal amount of pending transaction requests to be provided from one pipeline stage to another pipeline stage; executing an application while monitoring the performance of a device that comprises pipeline limiters; wherein the executing includes: selectively transferring transaction requests from one stage of the pipeline to another in response to the limiter thresholds, arbitrating between transaction requests at a certain pipeline stage, and executing selected transaction requests provided by the arbitrating.

Abstract: Method, apparatus and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.

Abstract: Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.

Abstract: Provided are a method, system, and program for managing path groups to an Input/Output (I/O) device. Indication is made of a connection path on which a processing system initially communicated an establish request to establish a connection with an I/O device, wherein attention that the processing system may own a lock for the I/O device is transmitted down the indicated connection path. A request is received from the processing system to add a path to a path group with respect to the I/O device, wherein the added path is capable of comprising the connection path the processing system used to establish the connection with the I/O device. The received path is added to the path group.

Abstract: A method and architecture are provided for SOC (System on a Chip) devices for RAID processing, which is commonly referred as RAID-on-a-Chip (ROC). The architecture utilizes a shared memory structure as interconnect mechanism among hardware components, CPUs and software entities. The shared memory structure provides a common scratchpad buffer space for holding data that is processed by the various entities, provides interconnection for process/engine communications, and provides a queue for message passing using a common communication method that is agnostic to whether the engines are implemented in hardware or software. A plurality of hardware engines are supported as masters of the shared memory. The architectures provide superior throughput performance, flexibility in software/hardware co-design, scalability of both functionality and performance, and support a very simple abstracted parallel programming model for parallel processing.

Abstract: Method and apparatus for communication between hardware blocks configured in a programmable logic device (PLD) and a computation device external to the PLD is described. A bus controller is provided for receiving words from the computation device. Each of the words includes an address component and a data component. A first-in-first-out buffer (FIFO) is configured for communication with the bus controller to store the words. A processing engine is provided having a memory space associated with the hardware blocks and being configured to receive a word at a top of the FIFO. An address decoder is provided for decoding the address component of the word at the top of the FIFO to obtain an address of a memory location in the memory space. A strobe generator is provided for coupling a strobe signal to the processing engine. The strobe signal is configured to store the word in the memory location.

Abstract: Provided is an access right managing method for a resource of a storage system, in which a management computer stores access right definition information of the resource, and resource correspondence information including information on a management program which manages another resource related to the resource managed by the management program. In case of which receiving an updating request of an access right of the resource, the management computer updates an access right based on the updating request of the access right, selects a management program of the resource whose access right is requested to be updated based on the resource correspondence information, transmits an updating request of an access right for a relative resource to a management computer which executes the selected management program, and in case of which the access right updating request of the related resource is received, updates the access right of the relative resource.

Abstract: Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.

Abstract: System for application priority based on device operating mode. A method is provided for allocating a top visible resource on a device. The method includes receiving a request requesting allocation of the top visible resource to a requesting application, and determining that the top visible resource is allocated to an owning application. The method also includes associating owner information with requester information to form an arbitration request. The method also includes arbitrating the arbitration request to produce an arbitration decision that indicates that the top visible resource is to be allocated to the requesting application if the owner information indicates that the owning application is privileged and an identifier that identifies the requesting application is contained in a relinquish list associated with the owner information.

Abstract: A multiprocessing system executes a plurality of processes concurrently. A process execution circuit (10) issues requests to access a shared resource (16) from the processes. A shared access circuit (14) sequences conflicting ones of the requests. A simulating access circuit (12) generates signals to stall at least one of the processes at simulated stall time points selected as a predetermined function of requests from only the at least one of the processes and/or the timing of the requests from only the at least one of the processes, irrespective of whether said stalling is made necessary by sequencing of conflicting ones of the requests. Thus, part from predetermined maximum response times, predetermined average timing can be guaranteed, independent of the combination of processes that is executed.

Abstract: A system provides dual use of a general purpose input/output (I/O) line. In an embodiment, the system comprises a controlling circuit having a dual purpose I/O line that is selectively operable in a serial transmit mode or an I/O mode. A first circuit that receives a serial data stream when the controlling circuit operates in the serial transmit mode is coupled to the I/O line. A second circuit that generates and transmits a signal when the controlling circuit operates in the I/O mode is also coupled to the I/O line. Finally, a third circuit is disposed between the second circuit and the I/O line. In an embodiment, when the controlling circuit operates in the serial transmit mode, the third circuit maintains the second circuit in an idle state, and when the controlling circuit operates in the I/O mode, the third circuit permits the second circuit to transmit the signal to the controlling circuit.

Abstract: To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: In a device that can execute multiple media applications, but only one at a time, a media server coordinates among applications, but neither the media server nor the individual applications maintain rules regarding all of the different applications. Each connection used by an application is assigned a priority and communicates that priority to the media server when the connection is established. When an application requests to begin playback, the request is granted if no other application is playing, or if another application is playing on a connection having a priority at most equal to that of the connection used by the requesting application, but is denied if the connection already in use has a higher priority. Resumption of an application that was interrupted by another application on a connection with higher priority is determined by the interrupted application after the interruption ends, based on information communicated by the media server.

Abstract: Masters request access to a shared resource, such as a shared bus. Usage of the shared bus by each of the masters is monitored, a request to use the shared bus by one of the masters is received, and usage of the shared bus by the master is compared with a corresponding bandwidth threshold. The request is arbitrated if the usage of the shared bus by the master is below the bandwidth threshold, and the request to use the shared bus is granted to the master based on the arbitration.

Abstract: A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

Abstract: When four access request origins A, B, C, and D are present, a priority table (No. 1) having a priority order of A, B, C, and D, a priority table (No. 2) having a priority order of B, D, A, and C, a priority table (No. 3) having a priority order of C, A, D, and B, and a priority table (No. 4) having a priority order of D, C, B, and A are prepared. An order of employing these tables is determined in advance in this order. A priority table next in the order to the priority table employed in last arbitration or, when a priority table at the bottom in the order is employed in last arbitration, a priority table at the top in the order is employed. Based on the priority levels defined in the employed priority table, an access request to be accepted is selected.

Abstract: An arbitration circuit for granting access to a shared resource among requestors comprises N request shapers, where N is an integer greater than one. An input unit receives a request from a requestor. An age unit assigns an age to the request and increases the age of the request when the requestor is not granted access to the shared resource. A priority unit assigns a priority level to each of the requests and selectively increases the priority level of the request based on the age of the respective one of the requests and a delta period of the request. An arbiter core receives the requests from the N request shapers and selectively grants access to the shared resource to each of the requestors corresponding to the requests based on the priority level and age of the requests. The delta period of one of the N request shapers is different than the delta period of another of the N request shapers.

Abstract: A data processing system includes processing units for processing data, at least one memory for storing data from the processing units, an interconnect for connecting the processing units and the memory. The processing units request write access to the memory via the interconnect to write data into the memory. At least one arbiter performs interconnect arbitration for the access to the memory from the processing units, wherein interconnect arbitration is performed based on the minimum logic level changes of the interconnect as introduced by the write accesses of the processing units to the memory. If more than one write request is available from different processing units the interconnect arbitration (interconnect access), is granted to that processing unit, whose data to be sent to the memory via the interconnect results in minimum logic level changes to the interconnect. Power dissipation due to switching of logic levels is reduced.

Abstract: A data processing apparatus and method are provided for arbitrating access to a shared resource. The data processing apparatus includes a plurality of requester elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests asserted by one or more of the requester elements for access to the shared resource, to perform a priority determination operation to select one of the asserted requests as a winning request. Each of the asserted requests has a priority level associated therewith, and the apparatus further comprises relative priority ordering circuitry for attributing relative priorities to the plurality of requester elements. The arbitration circuitry is responsive to the asserted requests to perform the priority determination operation in order to select as the winning request the request asserted by the requester element with the highest relative priority whose asserted request has a priority level not exceeded by any other asserted request.

Abstract: Technologies are described herein for governing access to a computing resource. A proxy receives a request to access a computing resource. In response to the request, the proxy determines whether the request can be granted without consulting a governor for the computing resource. If the request cannot be granted without consulting the governor, the proxy transmits the request to a broker. The broker, in turn, transmits the request to a governor for the computing resource. The governor determines whether the requested access to the computing resource should be granted. The governor generates a response to the request and transmits the response to the broker. The broker, in turn, transmits the response to the proxy. The broker may also request notifications from the governor.

Abstract: A resource management system uses a virtual resource pool distributed across a set of storage devices to manage resources in a distributed storage system. The storage devices dedicate a resource in an allocation pool available to the virtual resource pool. The virtual resource pool is a virtual storage server in which an application receives at least a predetermined amount of storage capacity, a predetermined level of performance, or a predetermined reliability, represented by tokens. A virtual resource pool manager gives the tokens to an application. The application transmits the tokens along with the commands to the storage device. The token represents a right to consume up to some limit of resources on a specific storage device in a computing session. The storage device locally tracks resource consumption through the token.

Abstract: Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Abstract: Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t?[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.

Abstract: The remaining time period until the deadline of transfer by a device connected to a bus is measured, the remaining data size to be transferred by the device is detected, and the priority level of the device is set based on the remaining time period and the remaining data size.

Abstract: A method and system for equipment arbitration in a process control system are presented. The method and system include receiving a request for a first resource associated with a first area from a first resource user associated with a second area where the first and second areas are distinct. The method and system automatically determine whether the first resource is available for use by the first resource user.

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract: An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the device to the central logic unit and the second unidirectional, point-to-point communication link transfers data from the central logic unit to the device.

Abstract: When receiving a write message associated with data, an input/output controller issues a write-request message to a home processor node which holds the data in a memory. When receiving the write-request message, a memory controller in the processor node executes a consistency process on the basis of information, regarding the state of the data, stored in a directory, and sends a write-permission message to the input/output controller which has issued the write-request message. In response to the received write-permission message, the input/output controller in an input/output node issues an update message, serving as a write message, to the home processor node. In response to the received update message, the memory controller in the process node updates the data in the main memory. In the above process, when receiving a plurality of write messages from input/output devices, the input/output controller issues write-request messages irrespective of the progress of a preceding write message.

Abstract: A data processing apparatus and method are providing for arbitrating access to a shared resource. The data processing apparatus has a plurality of logic elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests by one or more of the logic elements for access to the shared resource to perform a priority determination operation to select one of the requests as a winning request. The arbitration circuitry applies an arbitration policy to associate priorities with each logic element, the arbitration policy comprising multiple priority groups, each priority group having a different priority and containing at least one of the logic elements. Within each priority group, the arbitration circuitry applies a priority ordering operation to attribute relative priorities to the logic elements within that priority group.

Abstract: A method and system that allows a host system application to securely communicate with a legacy device is provided. A redirector software module receives data that is destined for a host system serial COM port. Data is secured and re-directed to a legacy device via a network port instead of the serial COM port. Conversely, data destined for the host system is provided to a device server via a server COM port by the legacy serial device. The data can be encrypted and sent to the host system via the network. The redirector software module decrypts the encrypted data and presents it to the consumer application as if the data had arrived via the local COM port.

Abstract: In an arbitration circuit in which a shared circuit such as a memory is used exclusively by one of a plurality of functional blocks at a time, an access reservation request is issued from one of the functional blocks, and the access request associated with the access reservation request is reserved. Thereafter, when an access request is issued from another functional block, it is determined which one of the access reservation request and the access request from these functional blocks takes precedence. For example, if the access request from the latter functional block has a low priority level, the access reservation request is selected and the circuit waits for an access request from the functional block which has issued this access reservation request. In this manner, it is possible to avoid cancellation of a once-accepted access request and waiting for a high-priority access request.

Abstract: A data processing system is provided comprising at least one processing unit for processing data; a memory means for storing data; and a cache memory means for caching data stored in the memory means. Said cache memory means is associated to at least one processing unit. An interconnect means is provided for connecting the memory means and the cache memory means. The cache memory means is adapted for performing a cache replacement based on reduced logic level changes of the interconnect means as introduced by a data transfer between the memory means and the cache memory means.