Abstract: Creating virtual extender plugins using MGTs (Multi-Gigabit Transceivers). A virtual extender plugin allows a user seamlessly to bridge between various FPGAs (Filed Programmable Logic Arrays) when designing and implementing electronic devices. These bridges, provided by these virtual extender plugins, allow for efficient use of various untapped resources within a device. For example, a given FPGA may employ virtual extender plugin(s) to access and use various untapped (or relatively lightly tapped) functionality of other FPGAs. These virtual extender plugins may be implemented according to a relatively wide variety of applications allowing the tapping of unused resources such as memory, microprocessor peripherals, LUTs (Look Up Tables), IOs (Input/Output devices and/or ports), memory, and embedded microprocessor blocks.

Abstract: A small electronic card with peripheral contacts includes a body, a plurality of front end contacts and a plurality of extended contacts placed along the two side edges. The plurality of extended contacts are used for increasing the data transmission bandwidth, and thus the data transmission speed, and the arrangement of the extended contacts does not affect the design of the reader, while preventing short circuit caused by pins touching incorrect contacts.

Abstract: A system is provided for switching the I/O channel for disk drives between multiple computers. The system incorporates the switch into removable drive modules, or a docking base for a removable drive module. The incorporation of switching into the system, such that it is integral with the drives, can reduce overall system failures, by reducing the number of elements which flow through a central switching element. Thus, even where a switch fails other drive modules of the system may continue to operate in the system and provide information to different computers of the system.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: The invention relates to a system for coupling a mobile data input unit to a field bus, whereby a coupling unit is connected to the field bus via a spur line and a line driver and the signals at the output of the line driver are supplied to a coupling link or received from the latter via first level converters. The mobile data input unit receives the signals from the coupling link or supplies them to the latter via second level converters.

Abstract: An electrical host system includes a host and an expandable optical disk recording and playing device. The expandable optical disk recording and playing device includes an expanding interface module, an expanding interface, a storage interface module, an output interface module and a CODEC module. The expanding interface module connects to the expanding interface and the host. The storage interface module connects to a storage device. The CODEC module encodes, decodes or transcodes an audio/video source to generate audio/video data, wherein the audio/video source is inputted from the host through the expanding interface and the expanding interface module. The audio/video data are outputted through the output interface module, or through the storage interface module to the storage device.

Abstract: Each attention button is tied to a presence signal, which is also used to detect the presence of a PCI adapter card within a slot. By comparing HPPC register states, pending due to a system control interrupt (“SCI”), with stored HPPC register states prior to the SCI, the HPPC is able to distinguish between an attention button press and a PCI card insertion or removal and therefore may respond appropriately to the SCI. According to the method, SCIs generated in a computer system by attention buttons are diagnosed and serviced by storing the contents of the HPPC registers. The contents of the registers identify the state of the presence and manually-operated retention latch (“MRL”) signals prior to the occurrence of a SCI and upon receiving a SCI corresponding to a state change for either signal, identify the hot plug controller and the slot where the interrupt occurred.

Abstract: In a connection form of PC-printer-digital camera, for example, to enable a printing function from a PC to a printer, a direct printing function from a digital camera to a printer, and a function of directly transferring image data on a memory card of the digital camera to storage means on the PC, without changing the connection of each device, a printer comprises a virtual USB function which receives data from a PC directly connected via a communication line, a USB host which requests a digital camera also directly connected via the communication line for a data transfer and obtains data, a USB function capable of inputting and outputting the data received by the virtual USB function and the data obtained by the USB host, respectively, and a virtual USB function which transfers the data obtained from the digital camera to the PC.

Abstract: The present invention is a method, apparatus and program storage device for providing data path optimization for redundant data paths. The present invention provides data path optimization that increases the data access throughput and availability to a device by using multiple paths when a modification event occurs.

Abstract: A system and method for providing the functionality of independent dedicated servers in a space savings and heat dissipation limited design, including a PC having a plurality of independent dedicated server cards which do not communicate over the PC system bus and only receive power therefrom. Communication with the server cards is done by independent pin connections on the exterior of the PC housing.

Abstract: An integrated controller for the detection and operation of both PC Cards, smart cards and passive smart card adapter cards. In one aspect, the invention detects the presence of standard expansion cards or passive smart card adapters by utilizing the reserved detection and voltage selection signal area defined by the PC Card specification. In another aspect, the invention provides an integrated controller that includes logic to operate either a standard expansion card or a passive smart card adapter by reassigning certain PC Card signal lines to operate a standard expansion card or a passive smart card adapter, thereby eliminating the need to provide pins in addition to those defined by the PC Card specification.

Abstract: A Compact Peripheral Component Interconnect (CPCI) system is provided that can map PCI Industrial Computer Manufactures Group (PICMG) states describing the state of a hot-swap CPCI card into Telecommunication Management Network (TMN) plug-in unit states. Specifically, the hardware/Operating System (OS) states for the CPCI card are specified in PICMG states in accordance with the PICMG hot-swap specification. The present system identifies or defines the meaning (e.g., the definition, identification, function, and/or status) of the states on the CPCI card. The system then maps these states into intermediate states. The intermediate states are then mapped into TMN plug-in unit states (e.g., OperationalState and/or AvailiableStatus). The TMN plug-in unit states corresponding to the CPCI card will then comprise the proper identification information for the CPCI card.

Abstract: A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A first sub-bus is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same. A second sub-bus is also connected to the main bus and branches into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number. Further, the second sub-bus branches into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.

Abstract: A system and method electrically isolates configuration and status information about power provided over Ethernet cabling.

Abstract: A method for preserving digital evidence of a computer misconduct, the method including the steps of: prior to the misconduct, installing an expansion card capable of retrieving and storing a memory image and register information from a digital electrical computer in which the expansion card is installed; connecting a switch to regulate the expansion card from a location other than the computer; at the time of the misconduct, using the switch to trigger the retrieving and storing of the memory image and the register information into the expansion card; and subsequent to the misconduct, extracting the expansion card to preserve digital evidence of the computer misconduct. This method can be carried out further by subjecting the memory image and register information from the expansion card with another computer to forensic analysis.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A processor surrogate (320/520) is adapted for use in a processing node (S1) of a multiprocessor data processing system (300/500) having a plurality of processing nodes (P0, S1) coupled together and to a plurality of input/output devices (330, 340, 350/530, 540, 550, 560) using corresponding communication links. The processor surrogate (320/520) includes a first port (372, 374/620, 622) comprising a first set of integrated circuit terminals adapted to be coupled to a first external communication link (370/590) for coupling (P0) of the plurality of processing nodes (310, 320/510, 520), a second port (382, 384/630, 632) comprising a second set of integrated circuit terminals adapted to be coupled to a second external communication link (380/592) for coupling to one (350/550) of the plurality of input/output devices (330, 340, 350/530, 540, 550, 560), and an interconnection circuit (390, 392/608, 612, 614) coupled between the first port (372, 374/620, 622) and the second port (382, 384/630, 632).

Abstract: A mini PCI module includes a mini PCI card and a mini PCI slot for the mini PCI card to be inserted into. The mini PCI card includes 124 signal pins and an antenna pin set. The mini PCI slot includes 124 signal connection ends corresponding to the 124 signal pins, and an antenna connection end set corresponding to the antenna pin set for electrically connecting to an antenna set.

Abstract: Methods and structures for managing connection requests within a SAS controller operating as a target device. A SAS target device maintains a table of information regarding known SAS initiator devices in the SAS domain. An index value is supplied in transport layer requests and used by each of a plurality of link layer processing elements in the SAS controller to access information in the table. The index value is fewer bits than the complete eight byte SAS address and the logic to manipulate and compare the index value is therefore simpler than that required to directly manipulate a full SAS address. Further, the information table is shared by each of the link layer processing elements to further reduce complexity from replication of circuits and logic in the SAS controller.

Abstract: A universal serial bus (USB) system having a card-type USB interface connector includes a host platform, a storage layer, and an electrical interface. The host platform includes a USB host controller for controlling data transfer, and a first card-type connector at which data is transferred. The storage device includes a non-volatile memory device for storing data, a memory controller for controlling the non-volatile memory device, and a second card-type connector at which data is transferred with the first card-type connector. A plurality of electrical lines interconnecting the first and second connectors are disposed in the electrical interface. A USB control module converts transferred data into USB packets, and converts USB packets into data for transfer. The card-type USB interface connector of the USB system is used as a USB interface connector by means of a card-type plug. Thus, the card-type USB interface connector is readily installed in card-type connector interfaces.

Abstract: A data transfer control system receives a command packet ORB transferred through a bus BUS1 (IEEE 1394), issues a command indicated by ORB to a device connected to a bus BUS2 (ATA (IDE)/ATAPI), and orders start of a DMA transfer. The command issued based on ORB is aborted after the completion of the DMA transfer. The data transfer control system compares contents of a command packet ORB1 transferred before a bus reset with contents of a command packet ORB2 transferred after the bus reset. If the contents are different, a command issued based on ORB1 is aborted after completion of a DMA transfer. Dummy data is transferred between the data transfer control system and the device connected to the bus BUS2 until a DMA transfer is completed. Dummy data transfer is controlled by performing a dummy update on a pointer.

Abstract: This invention adapts a stationary flat display for use as a portable computing and media device. The adaptation takes advantage of the predetermined mounting arrangements of the stationary flat display by inserting external modules between the predetermined mounting arrangements. When stationary, the flat display can continue its intended use as the primary display connected to a desktop computer system. The combination of the flat display with attached external modules is quickly released from stationary use to enable portable use for other applications.

Abstract: A USB device for performing communications with a second device through a USB interface while supplying electric power to the second device through a power-source supplying line in the USB interface. The USB device includes a communication unit for communicating with the second device, a power source capable of outputting electric power of a voltage being different from a standard power voltage prescribed in the standards of the USB interface. The power source supplies the electric power to the second device through the power-source supplying line. The second device includes a low load unit and a high load unit The power source supplies the electric power having a power voltage higher than the standard power voltage to the high load unit through the power-source supplying line.

Abstract: Modules coupled to multiple connectors can check to see if full connectivity is provided through the connectors. If it is not, for instance because the connectors are mis-seated, the modules can prevent themselves from fully powering up. In a storage environment, a first module is coupled to connectors. The connectors are coupled to corresponding disk drives. Each connector provides a connectivity indication. The module prevents itself from fully powering up if it fails to receive a connectivity indication from a subset of connectors coupled to boot disks.

Abstract: In a storage controlling apparatus controlling an access from a host to a disk apparatus, for example, when a data transfer confirmation flag set in a data transfer descriptor is “ON”, a data transfer confirmation descriptor is automatically generated on the basis of transfer information in the data transfer descriptor, data is transferred to a management module according to the data transfer descriptor, and a confirmation code is read out from a bridge module according to the data transfer confirmation descriptor after data transfer to the management module is completed. Whereby, the load on the CPU and the number of PCI accesses are decreased so that the input/output performance is improved.

Abstract: A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.

Abstract: A polling method, apparatus, and system to detect the attachment and detachment of Universal Serial Bus devices in a wireless system. A hub provides a wired connection to the host and wireless attachment points for its devices, The host periodically queries the hub for changes in the hub's status register by sending a polling message through each of its wireless ports, and awaits a response. A peripheral device that wishes to attach to the system responds by sending its unique peripheral address. If a device currently occupies the port, the hub sends out the device's unique address in the polling message. If the device is still present, it responds by sending its unique peripheral address. If a response is not received after multiple retries, the device is considered detached. The hub thus determines the status of the ports and updates the status register, which is queried by the host.

Abstract: The present invention provides a method and apparatus to be used to extend the range of standard USB devices, and in particular, USB devices operating in accordance with Revision 2.0 of the USB Specification. An extended range hub is provided which comprises a Local Expander (LEX) and a Remote Expander (REX) which can be separated by up to, for example 100 meters. The LEX and REX operate in accordance with an enhanced high-speed USB Extended Range Protocol (USB-ERP) which permits USB devices to be more conveniently located and used, and is in compliance with Revision 2.0 of the USB Specification.

Abstract: A system for extending in length a connection from a universal serial bus (USB) peripheral device to a computer beyond the length enabled by the device hardware.

Abstract: A method and system for wirelessly coupling a computer with a peripheral device. The peripheral device is initially docked to a docking port in the computer. The computer then listens for identifiers from all peripheral devices within range of the computer, including the identifier for the peripheral device that is presently docked with the computer. The computer then instructs the docked peripheral device to stop sending its identifier. By a process of deduction, the computer is able to identify the docked peripheral device. The step of stopping the docked peripheral device from sending the peripheral device's identifier is preferably controlled by monitoring whether the computer is charging a battery in the docked peripheral device. Thus, the docked peripheral device transmits its identifier only when it is charging its battery.

Abstract: A method for using a personal computer memory card international association (PCMCIA) controller to communicate with an Integrated Drive Electronics (IDE) drive which includes performing a transfer between the static random access memory (SRAM) controller and the IDE drive using PCMCIA interface signals to communicate with the IDE drive and a general purpose input/output signal to communicate with an interrupt request of the IDE drive.

Abstract: A semiconductor integrated circuit to be connected to a PCI bus, having a configuration register. The size of an address space mapped to the semiconductor integrated circuit depends on the size of readable and writable region (Fv) of a base address register (30) that the configuration register has. The size of the readable and writable region of the base address register can be changed by a mask circuit (31). The size of a local address space can be set to be variable according to the number of mask bits specified by a mask signal. For example, also in the case where a plurality of PCI devices are used, a memory space mapped to each device can be selectively reduced in size and as such, it is also possible to cope with the case where finite resources are mapped to many PCI devices to construct a system.

Abstract: A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines.

Abstract: In one embodiment, a method is provided. The method of this embodiment may include receiving an indication that a first device has been granted access to a bus. In response, at least in part, to the indication, a signal may be provided that may result in the coupling of a signal line of a second device to the bus. After the provision of the signal, the first device may configure the second device. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.

Abstract: A server for carrying out synchronization control, includes (a) at least one event receiver for receiving an event, (b) a memory storing therein distribution schedule information including a plurality of schedule data therein, each of the schedule data including (b1) a timing at which a channel driver controls a media server, (b2) a content of how the channel driver controls the media server, and (b3) a timing type indicating which one of a time and the event the timing is defined by, and (c) a controller which detects whether a timing is established for each of the schedule data included in the distribution schedule information, and transmits a signal to the channel driver, the signal being indicative of a control associated with the established timing.

Abstract: An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.

Abstract: In one embodiment, a system for automatically establishing a wireless connection between adapters includes a master adapter coupleable to a peripheral device. The master adapter can automatically enter an inquiry mode in response to the occurrence of a first event. In the inquiry mode, the master adapter automatically establishes one or more wireless connections between the master adapter and one or more slave adapters that are coupled to one or more computer systems. The master adapter can also automatically enter an operational mode in response to the occurrence of a second event. In the operational mode, the master adapter enables communication between the peripheral device and the one or more computer systems via the one or more wireless connections using a wireless protocol.

Abstract: An interface link layer device is connected in-between a first sub network and a long delay link to which at least one second sub network is connected. The interface link layer device comprises at least two storage areas, whereby new configuration data received via the long delay link is written to one of the storages to simulate the devices of the second network within the first network. In case a self ID phase is initiated as long as the configuration information is not complete yet, the respective other storage area is accessed. In case a self ID phase is initiated as soon as or after the new configuration data is complete, the storage area to which the new configuration data has been written is used for setting up the self ID packet.

Abstract: A method and system for accessing devices through use of an abstraction layer interface that “hides” the access methods from components accessing the devices, such as device drivers and OPROMs. The abstraction layer interface includes a set of resource access methods and a database containing bus, device, function and resource information for various devices in a system. During an initialization process, bus and device configuration information is determined and stored in the database. When an application or operating system requests access to a device, the application or OS uses the device's device driver or OPROM to pass identification information, resource information and one or more resource access commands to the abstraction layer interface, which then verifies the identification information against the database, and converts the resource access request into appropriate resource access methods that are used to access the device.

Abstract: An USB composite device using hub link layer and UTMI interface is disclosed, which connects to a host through an USB cable. The device includes an USB physical layer, a hub link layer and plural functional link layers. The USB physical layer can receive and transmit USB signals. The hub link layer connects to the USB physical layer through an UTMI interface, has plural downlink ports to provide linking, and responds an USB transaction performed by the host. The plural functional link layers connect to the downlink ports of the hub link layer through plural UTMI interfaces.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A method, system, and data processing system for dynamic detection of problem components in a hot-plug processing system and automatic removal of the problem component via hot-removal methods without disrupting processing of the overall system. A data processing system that provides a non-disruptive, hot-plug functionality is designed with a additional logic for initiating and/or completing a sequence of factory level tests on hot-pluggable components to determine if the component if functioning properly. When a component is not functioning properly, the OS re-allocates the workload of the component to other component so the system, and when the OS completes the re-allocation, the service element initiates the hot removal of the component so that the component is logically and electrically separated from the system.

Abstract: A memory card comprising a first modular component that comprises a first host interface and a first host interface module and a device interface module configured to operate a device interface that is coupled to a storage device. The first host interface module is configured to call a function in the device interface module. The first modular component is replaceable with a second modular component that comprises a second host interface and a second host interface module, and the second host interface module is configured to call the function in the device interface module.

Abstract: A storage device that is communicably connected to a host computer includes a plurality of disk units for storing data from the host computer. Each of the disk units includes a plurality of hard disks and is connected to one of a plurality of ports. A plurality of disk unit control units control the plurality of disk units, and each of the disk unit control units includes a memory for temporarily holding data from the host computer. A plurality of control signal transmission cables transmit control signals from the disk unit control units to the disk units. At least one of the control signal transmission cables is connected to at least two of the disk unit control units and transmits different control signals to at least two of the disk units. This enables device miniaturization and reduced costs for the storage device without a drop in reliability, even when a variety of devices are mounted in a highly dense configuration.

Abstract: An information handling system comprises a first bus system comprising a plurality of connection pins wherein at least one pin is unused, at least one control line for controlling or communication with devices of the system, a controllable coupling/de-coupling unit for coupling/de-coupling the control line with the at least one previously unused pin, and a control unit for controlling the coupling/de-coupling unit coupled with the control line.

Abstract: The present invention provides systems, methods, and bus controllers (12) for establishing communication with various network systems located on a network system (10). Importantly, the systems, methods, and bus controllers (12) of the present invention are capable recognizing that a new network device (16, 18, 20) has been added to an existing network and assigning it an address such that the added network device is identifiable on the network. Further, the systems, methods, and bus controllers (12) of the present invention may update the operating schedule that outlines communication in the network system between the bus controller (12) and the network devices (16, 18, 20) to include commands for communicating with the added network device. The systems, methods, and bus controllers (12) of the present invention may also detect when a network device (16, 18, 20) has been disconnected from a network system (10) and remove the commands associated with the networked device from the command schedule.

Abstract: Techniques are provided for distributing signals in a stackable unit, including a first input connector of two or more input connectors; a second input connector of two or more input connectors, wherein the first input connector is spaced apart from the second input connector, and the first input connector has a particular spatial relationship to the second input connector; a first output connector of two or more output connectors; a second output connector of two or more output connectors, wherein the first output connector is spaced apart from the second output connector, and the first output connector has the same particular spatial relationship to the second output connector; means for communicatively coupling the first input connector and the second output connector; and means for terminating the first output connector.

Abstract: Very small non-volatile memory cards are modified to include a connector to which a connector on a separate data input-output card electrically and mechanically mates when pushed together. The input-output card transfers data directly between an external device and the non-volatile memory, without having to go through the host to which the memory card is connected. The input-output card communicates with the external device through a wired or a wireless communication channel.

Abstract: A method for connecting an expansion module to a programmable electric switching device includes initiating a recognition mode within the switching device during which an interrogation is carried out as to whether or not the connected expansion module is initializable. If the expansion module is not initializable, no data is exchanged between the switching device and the expansion module. If the expansion module is initializable, the switching device switches into an expansion communication mode in which data exchange takes place under the control of the operating system of the expansion module.