Abstract: A VXS multi-service platform system (100) includes a VXS computer chassis (103), a monolithic backplane (102) in the VXS computer chassis having a VMEbus network (108) on the monolithic backplane and a switched fabric (110) operating coincident with the VMEbus network on the monolithic backplane. A switched fabric link (260) extends the switched fabric external to the VXS computer chassis and the monolithic backplane.

Abstract: The present invention discloses a PCI extended function interface and PCI device using such an interface. The PCI extended function interface is suitable for use in a PCI device comprising a master device and at least one slave device. The PCI extended function interface comprises at least one connecting port and a first circuit. The slave device is coupled to a corresponding connecting port and the PCI extended function interface transmits a control signal through the connecting port to control the operation of a corresponding slave device. The first circuit is used to determine the configuration space.

Abstract: A system and method is disclosed that efficiently provides standard termination blocks in an approved cell library that are flexible and customizable. A serial communications system includes a transmitter for sending a serial data signal at an output of the transmitter; a transmitter terminator, coupled to the output and responsive to a first configuration signal, to variably terminate a first selected property of the output; a receiver for processing the serial data signal at an input of the receiver, the input of the receiver coupled to the output of the transmitter; and a receiver terminator, coupled to the input of the receiver and responsive to a second configuration signal to variably terminate a second selected properly of the input.

Abstract: A system and method for introducing user-defined (e.g., proprietary) signals into a standard backplane. A front side backplane portion is provided with a set of connector holes that are electrically separated from corresponding connector holes provided on the backplane's rear side portion. Thus, whereas the separated front side connector portion is operable with standard bus signals, the rear side connector portion can support an independent signal pathway to carry one or more user-defined signals.

Abstract: A method and system processing non-data frames in a host bus adapter with a main processor and a first processor coupled to a host system and fibre channel is provided. The method includes, examining non-data frames; storing non-data frame information; notifying the first processor of non-data frames; and processing non-data frames without generating an interrupt for the main processor. The host bust adapter includes a fibre channel module (“FPM”) with a state machine, wherein the fibre channel module receives and examines the non-data frames and stores non-data frame information in a FIFO. The FPM notifies the first processor that the non-data frames have been received.

Abstract: An expander coupled between at least a first and second SCSI device for transmitting data and training patterns is provided. The expander includes, a first detection module for detecting a training pattern received from the first device; a second detection module that detects when a first section of the training pattern has been transmitted to the second device; and means for changing the expander's mode from a training mode to a repeat mode after the first section.

Abstract: A computer system comprises a host processor, and a service processor for providing system management functions within the computer system. One or more external communication devices are provided, for example ethernet ports. The external communication devices include at least one management communication device that communicates with the service processor. The management communication device is controlled by a signal from the service processor and is operative to send and receive data only when it receives the signal from the service processor.

Abstract: A storage device (200) has a memory and a circuit (100) which has a data input (Din), a control input (CTRL) and a data output (Dout), and provides an address input from the data input (Din) to the memory in accordance with a control signal from the control input (CTRL), so that the storage device (200) stores the data at the address in the memory or outputs data at the address in the memory to the data output (Dout). The apparatus provides the control signal to the control input (CTRL) from the interface (PORTS, P0, P1, P2), address and the data to the data input (Din) from the interface (PORTS, P0, P1, P2), to store the data at the address in the memory or to output data at the address in the memory to the data output (Dout). The apparatus may have a microcontroller (MPU) in which the interface (PORTS, P0, P1, P2) is provided.

Abstract: In one embodiment, a method is provided in which an integrated circuit that includes an integrated input/output (I/O) controller is coupled to a storage system. The integrated circuit is coupled to a host processor system bus via a dedicated communication path. The storage system is capable of being coupled to and de-coupled from at least one removable storage device, and of receiving from the integrated circuit, when the storage system is coupled to the integrated circuit, data and/or an I/O request. The method of the embodiment also includes coupling or de-coupling the at least one removable storage device to or from, respectively, the storage system. The storage system remains capable of receiving from the integrated circuit the data and/or I/O request while the at least one removable storage device is being coupled to or de-coupled from the storage system.

Abstract: A data amplifier configured to allow for fewer data lines and/or increased processing speeds. Specifically, multiple helper flip-flops are used to prefetch data in a data amplifier. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines. Alternatively, the number of data lines can be maintained and faster bus processing speeds may be realized.

Abstract: Aspects for increasing control information from a single general purpose input/output (GPIO) mechanism are described. The aspects include utilizing a single GPIO mechanism with a socket on a computer system. Determinations of whether a first card, a second card, or no card is installed in the socket occur according to detected changes in signal states on a single signal line between the GPIO mechanism and the socket. Detection of a first state on the single signal line indicates presence of a first card in the socket, while detection of a second state on the single signal line indicates presence of a second card in the socket. Detection of a state change on the single signal line indicates no card presence in the socket, where the changes occur in response to signals sent by a POST (power-on self test) routine to the GPIO mechanism.

Abstract: A system and a method for the transfer of data between a digital camera and a host using a novel combination of hardware and software related elements. An aspect of the hardware-related elements provides a camera base unit which remains connected with the host, and which the camera is connected with to facilitate the transfer of data to the host. The camera base unit significantly simplifies the connection between the camera and the host by alleviating the need to directly connect the camera with a host. Furthermore, the camera base unit, by providing a pass-through connection and placement guides that mate with the camera, assures that an intuitive placement of the camera on the camera base unit also enables an electronic connection between the camera and the host. Therefore, the simple placement of the camera in contact with the camera base unit ensures a proper interface between the camera and the host, which is connected with the camera base unit.

Abstract: A portable USB device built with rechargeable functional apparatus is disclosed. The portable USB device has a USB connector for being inserted into a socket of a host device. A USB device module is powered by the +5V pin on the USB connector and activated to perform data exchange via the D+ and D? pins on the USB connector when the USB connector is coupled to the host device, so as to provide a first specific function to the host device. A charge circuit charges the rechargeable battery via the +5V pin when the USB connector is coupled to the host device. A functional apparatus is powered by the rechargeable battery so as to provide second specific function different from the first one when the USB connector is not coupled to the host device.

Abstract: A USB-based wireless transmitting/receiving system includes a transmitting portion connected to at least one USB-based peripheral device for receiving a signal from the peripheral device and a receiving portion connected to a computer host and coupled to the transmitting portion in a wireless fashion for receiving and applying the signal from the transmitting portion to the computer host whereby a wireless communication is established between the computer host and the USB-based peripheral device. Both the transmitting portion and the receiving portion include a central processing unit for processing signals received, a receiving unit for receiving signals, a transmitting unit for transmitting signals and a power supply system for powering the transmitting portion or the receiving portion. The power supply system includes a regulation circuit adapted to connect to an electric main.

Abstract: An electronic interface device interfaces between a first and second electronic device. The first device has a mechanical module connector. The electronic interface device includes a receiver/transmitter for receiving signals from and transmitting signals to the second electronic device, a circuit for decoding/coding and mapping its input/output signals, and a connector connected to the mechanical module connector of the first electronic device.

Abstract: Single end signal communication is provided in a first direction from a single end signal transmitter to a single end signal receiver through at least one dumping resistor and may be provided in another direction from another single end signal transmitter to another single end signal receiver through the at least one dumping resistor. During the single end signal communication, differential signal transmitters and differential signal receivers are disabled so that the communication path of the differential signal has a high impedance. Differential signal communication is also provided in the first direction from one of the differential signal transmitters to one of the differential signal receivers through a first termination resistor that also serves as the dumping resistor and may be provided in the another direction from another of the differential signal transmitters to another of the differential signal receivers through another termination resistor that also serves as another dumping resistor.

Abstract: A system and method for selecting a hardware master from a plurality of computing devices and controlling the communication of a master control signal(s) to one or more of the plurality of computing devices includes monitoring first and second connectors coupled with a midplane to detect the presence of first and second computing devices, respectively. Master control signals may be transmitted to the second computing device if the first computing device is not coupled with the first connector. Transmission of the master control signals to the second computing devices may be prevented if the first computing device is coupled with the first connector. In accordance with a particular embodiment of the present invention, master control signals may be transmitted to the first computing device if the first computing device is coupled with the first connector.

Abstract: A method and associated apparatus is provided for improving the performance of a high speed memory bus by substantially eliminating bus reflections caused by electrical stubs. The stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a looping bus for continuing the looping bus through each device. The invention also provides an interface circuit that enables data communications between devices of different technologies. The interface circuit connects to the looping data bus and includes a circuit for providing voltage level, encoding type, and data rate conversions for data received from the looping data bus and intended for use on a second data bus connected to the interface circuit.

Abstract: A method for connecting an interface to a serial bus is provided comprising the steps of sensing at least one identification line for the interface, identifying an interface type from the at least one identification line, and switching the interface to or from a serial bus depending on the interface type identified. The at least one identification line specifies at least one serial type of interface and at least one non-serial type of interface. Preferably, the method further comprises the step of switching the interface off the serial bus based on a criteria.

Abstract: There is disclosed a system and method for providing an improved common control bus for use in the on-line insertion of line replaceable units (such as circuit board cards) into a backplane of a processor shelf, a modem shelf, or a similar type of equipment. The present invention increases the number of device locations that a common control bus can access. The present invention comprises a complex programmable logic device on a circuit board card that is coupled to a common control bus. The complex programmable logic device is capable of selectively coupling to the common control bus each one of a plurality of device locations on the circuit board card. The complex programmable logic device controls data access to and from each device that is coupled to the common control bus.

Abstract: A system for extending in length a connection from a universal serial bus (USB) peripheral device to a computer beyond the length enabled by the device hardware.

Abstract: An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular, by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.

Abstract: In a device information acquisition method, it is discriminated whether a network is constituted by a plurality of buses or a single bus. A bus ID assigned to each of remote buses is acquired. Device information is acquired from each of devices connected to the network. When at least one of the remote buses is disconnected from the network, the device information of the device connected to the disconnected remote bus is discarded. If it is discriminated that the network is constituted by a single bus, the information of all devices connected to the local bus is acquired. If it is discriminated that the network is constituted by a plurality of buses, the information of all devices connected to each of the buses having the acquired bus ID is acquired. A device controller and bridges using the device information acquisition method are also disclosed.

Abstract: One aspect of the invention relates to creation of a container object being part of software that is stored in platform readable medium and executed by a processor within a platform. The container comprises (i) a hardware identification object to identify to an operating system of the platform that a type of device represented by the container object is a node and (ii) a plurality of component objects to identify constituent components of the node. Another aspect of the invention is the distribution of BIOS to handle initiation of components of a substrate in response to hot-plug addition of that substrate.

Abstract: A configurable and scaleable multi-bus platform for developing, testing and/or debugging prototype systems to be implemented in an integrated circuit includes a backplane providing multiple busses. Multiple system bus cards can be coupled to the backplane, and each of the system bus cards includes a system bus which is electrically coupled to at least one bus on the backplane. The system bus cards also include a bus infrastructure device providing support logic for operating the system bus. Daughter cards, containing master or slave devices for particular design configurations, are coupleable to the system bus cards in order to simulate a system bus which will be implemented in the integrated circuit. The backplane and system bus cards, as well as other components, can be easily reused in other projects for designing, testing and debugging other integrated circuits.

Abstract: A method of (and system for) of displaying information, includes an extended bus bridge, a graphics adaptor coupled to the extended bridge, and a monitor coupled to the graphics adaptor to display the information, such that the graphics adaptor is localized to the monitor.

Abstract: A data storage device array includes a number of data storage devices. Each of the disc drives is operable to spin-up its spindle motor in response to the successful communication of predetermined out-of-band (OOB) signals. By selectively causing the communication of the predetermined OOB signals to the data storage devices, the selective spin-up of the data storage devices may be achieved.

Abstract: A peripheral computer enclosure includes a casing, a plurality of slots, a plurality of canisters being disposed in the slots, a plurality of storage devices, a plurality of canisters, a back plane, a power supply, a blower, a controller card and a personality board. The casing has an open front and a back. The slots are disposed inside the casing. The back plane is disposed in the casing. The power supply is disposed in the casing. The blower is disposed in the casing. Each storage device is disposed in one of the canisters. The back plane interconnects the storage devices. The personality board is connected to the back plane. The controller card is connected to the back plane.

Abstract: A disk module of solid state is comprised of a IDE interface, a flash memory controller, a power source, and a flash memory array. The IDE interface is a connector to engage with the main board of a computer. The flash memory controller is used to control data access and specify an address of data storage. The power source is connected to the flash memory controller for supplying a working voltage. A flash memory array is composed of a plurality of flash memories and connecting with the flash memory controller for saving data.

Abstract: A method and apparatus for low pin count firmware hub recovery on a circuit board having a firmware hub includes coupling a firmware hub recovery module having a firmware program onto the circuit board, establishing communication between a central processing unit (CPU) and the firmware hub recovery module, and reprogramming the firmware hub by the firmware program.

Abstract: In a first embodiment, an applications programming interface (API) implements and manages isochronous and asychronous data transfer operations between an application and a bus structure. During an asynchronous transfer the API includes the ability to transfer any amount of data between one or more local data buffers within the application and a range of addresses over the bus structure using one or more asynchronous transactions. An automatic transaction generator may be used to automatically generate the transactions necessary to complete the data transfer. The API also includes the ability to transfer data between the application and another node on the bus structure isochronously over a dedicated channel. During an isochronous data transfer, a buffer management scheme is used to manage a linked list of data buffer descriptors.

Abstract: A method and system for selectively interconnecting two SCSI host buses where each SCSI host bus includes a host device and multiple addressable SCSI target devices, each SCSI target device having a multibit SCSI ID associated therewith. A SCSI cross-link repeater is interposed between the two SCSI host buses and selectively enabled. Each time the SCSI cross-link repeater is enabled, the repeater enable signal is utilized to automatically alter the most significant bit of the multibit SCSI ID associated with each SCSI target device on the second SCSI host bus, such that those SCSI target devices do not duplicate the SCSI IDs of the SCSI target devices on the first SCSI host bus. Disabling the SCSI cross-link repeater automatically resets the most significant bit of the multibit SCSI IDs, restoring the original SCSI IDs for those devices.

Abstract: A system for extending in length a connection from a universal serial bus (USB) peripheral device to a computer beyond the length enabled by the device hardware.

Abstract: A polling method, apparatus, and system to detect the attachment and detachment of Universal Serial Bus devices in a wireless system. A hub provides a wired connection to the host and wireless attachment points for its devices. The host periodically queries the hub for changes in the hub's status register by sending a polling message through each of its wireless ports, and awaits a response. A peripheral device that wishes to attach to the system responds by sending its unique peripheral address. If a device currently occupies the port, the hub sends out the device's unique address in the polling message. If the device is still present, it responds by sending its unique peripheral address. If a response is not received after multiple retries, the device is considered detached. The hub thus determines the status of the ports and updates the status register, which is queried by the host.

Abstract: Disclosed is a serial bus interface device having a physical layer circuit capable of also simulating a plurality of devices without exerting an influence on a topology when the device is connected to a serial bus such as an IEEE 1394 serial bus. When a bus analyzer of the invention is inserted between a personal computer having the ID of 1 and a digital camera having the ID of 0 in order to analyze data on the IEEE 1394 serial bus to which the personal computer and the digital camera are connected, the bus analyzer interfaces with buses without being given an ID by the physical layer circuit, and analyzes the states of the buses without changing the state of the system to be analyzed and without changing the IDs of the personal computer and the digital camera.

Abstract: A system and method for hot swapping daughtercards in high availability computer systems. In one embodiment, a high availability computer system includes a peripheral bus. Daughtercards may be added to the computer system by inserting them into connectors associated with the peripheral bus. The daughtercards are configured to allow their insertion or removal from the computer system without interruption to system operations. When inserted into a computer system, a daughtercard may be powered up by power control circuitry on the daughtercard. When the daughtercard is powered up, it may then assert a configuration change signal. The computer system may then respond to the assertion of the configuration change signal by establishing software communications with the daughtercard. The configuration change signal may be driven to a storage unit located within a bus interface unit of the computer system. The state of the configuration change signal may be stored within a storage location of the storage unit.

Abstract: A system and method are provided that include determining optimum memory organization in an electronic device, wherein further determined are optimum resource interconnection patterns. One aspect of the system and method includes determining resource, e.g., memories and data paths, interconnection patterns of complex bus structures with switches using system-level information about the data-transfer conflicts. The quantity of memories within an electronic device, the size of the memories and the interconnection between the memories, including the interconnection of the memories with one or more data paths, defines a memory organization of an electronic device. Another aspect of the system and method relates to selecting an optimized memory organization, including selecting an optimized interconnection pattern between the memories and between the memories and the data paths.

Abstract: A riser card with a corresponding interface on a motherboard can reduce the overall cost of an electronic system as well as simplify upgrading the features provided by the riser. Implementation costs can be reduced, for example, for audio components that may otherwise require shielding in order to prevent electromagnetic interference if the audio component were located on the motherboard. Other components can also be simplified if located on a riser rather than the motherboard. Upgrading of features supported by the riser card is simplified because the riser card can be replaced. The riser card described herein provides Plug-and-Play functionality so that an operating system controlling the electronic system in which the riser card is included can load the appropriate driver software thereby simplifying operation of the electronic system.

Abstract: A communication adapter includes a cable communication signal processing circuit which enables a PDA to have access to a communication network via a cable and a radio communication signal processing circuit which enables a PDA to have access to a communication network via radio waves. The cable communication signal processing circuit and the radio communication signal processing circuit are provided in a single case or on a single board. The cable communication signal processing circuit and the radio communication signal processing circuit operate simultaneously. By attaching the communication adapter to a PDA, the PDA can have access to the communication network via the cable and to make an access to the communication network via the radio waves. Further, the PDA is capable of communicating with the network via the cable and via the radio waves simultaneously.

Abstract: A multi-function interface which allows connectivity between a communication device and a host is provided. The multi-function interface includes a plurality of logical devices which provide connectivity between the communication device and the host. The communication device transmits data and updates the host simultaneously using the plurality of logical devices which are associated with the peripheral device. The plurality of logical devices includes a communication port and status port. The communication port allows for the transmission of data between the host and the communication device. The status port updates the host with real-time status information as the communication device is transmitting data to the host.

Abstract: A system and method are disclosed providing for broadened time constraints under USB 2.0 protocol, enabling extended cable spans, in addition to other benefits. The present invention in one embodiment utilizes ‘split transactions’ to take advantage of the relaxed latency requirements of this scheme, in addition to utilizing the 80/20 transaction ratio for USB 2.0 microframes. Another embodiment of the present invention improves timing constraints by providing a delay between start splits and complete splits equal to some number, ‘N’, of microframes. A further embodiment takes advantage of the fact that under USB 2.0, no transaction can span from one frame to the next, freeing one extra microframe per frame by virtue of phase shifting a slave device into appropriate synchnronization. Lastly, an embodiment of the present invention improves timing constraints by providing a delay between start splits and complete splits equal to a full frame (eight microframes).

Abstract: When data is transferred from a controller of a liquid crystal display device to each driver through a predetermined number of signal lines, the Transferring Data are divided into a plurality of groups by forming the signal lines into groups beforehand. For each group, the combination of inversion/non-inversion of the data to be transmitted is examined, a well-balanced combination is selected so as to reduce EMI.

Abstract: A method and system for producing a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface has a plurality of first directors, a plurality of second directors, and a global memory. The method includes: providing a backplane having slots adapted to have plugged therein a plurality of printed circuit board. The printed circuit boards include: a plurality of first director boards having the first directors; a plurality of second printed circuit boards having the second directors; a plurality of memory printed circuit boards providing the global memory; a plurality of dummy first director boards having first jumpers; a plurality of dummy second director boards having second jumpers; a plurality of dummy memory boards having third jumpers.

Abstract: A system carrier for freely programmable blocks that are connected to one another by buses, of a carrier body, at least three identically configured connectors disposed on the carrier body and being configured to receive in each case one module with a freely programmable block, the module being couplable to the connector and its position changable, and three groups of buses arranged to fixedly connect the connectors to one another.

Abstract: The invention is directed to techniques for discovering a powerability condition of a computer network such as the existence of a remotely powerable device attached to a connecting medium of the computer network. Such detection can then control whether a remote power source (e.g., a data communications device such as a switch) provides remote power (e.g., phantom power) to the computer network. One arrangement of the invention is directed to an apparatus for discovering a powerability condition of a computer network. The apparatus includes a signal generator, a detector and a controller which is coupled to the signal generator and the detector. The controller configures the signal generator to provide a test signal to a connecting medium of the computer network, and configures the detector to measure a response signal from the connecting medium of the computer network.

Abstract: A serial bus expansion circuit, system, and method are provided. In one embodiment, the serial bus expansion circuit comprises a bus distribution circuit selectively coupling a serial bus to one of a number of serial bus outputs. The serial bus expansion circuit also includes a distribution controller having a control output coupled to a control input of the bus distribution circuit, and, a number of power-up pull resistors coupling each of the serial bus outputs to a power-up pull source.

Abstract: Expander device and method for resetting bus segments in I/O subsystem to clear bus hang in an I/O subsystem having a plurality of bus segments. Each bus segment in the I/O subsystem includes a set of devices and a bus that is coupled to the set of devices. In addition, the I/O subsystem includes at least one expander, each expander being arranged to couple a pair of buses for propagating communication signals. A reset signal is asserted on a first bus segment. In response to the reset signal, each expander coupled to the first bus segment and each device in the first bus segment reset themselves. Additionally, each expander coupled to the first bus segment isolates the reset signal such that the reset signal is not propagated to the other bus segments. For each expander coupled to the first bus segment, all communication signals are isolated such that each expander prevents propagation of the communication signals between the first bus and other bus.

Abstract: A method and system for determining the location of plural devices operationally coupled to a computer system using a 1-Wire bus is provided. The method includes, determining if more than one bus-coupler is detected by the computer system; disconnecting bus-couplers in an arbitrary manner until a pre-determined number of bus-coupler(s) is visible to the computing system; determining the location of the detected pre-determined number of bus-couplers; storing the location of the detected pre-determined number of bus-couplers; and repeating the foregoing steps until all the bus-coupler locations are determined and stored. The pre-determined number of bus-couplers may be one and the plural devices include switches and analog/digital converters.

Abstract: System (50), e.g. a System on a chip (SoC), comprising a system bus (56), a high-speed functional block (51) operably linked to the system bus (56), and a high-speed clock line (54) for applying a high-speed clock to the high-speed functional block (51). The system (50) further comprises a peripheral bus (59), a low-speed functional block (52) operably linked to this peripheral bus (59), a circuitry (53) for generating a wait signal (PWAIT), a low-speed clock line (57) for applying a low-speed clock (PCLK) to the low-speed functional block (52), a select line (58) for feeding a select signal (PSEL) from the peripheral bus (59) to the low-speed functional block (52), an enable line (55) for applying a clock enable signal (PCLKEN) to the circuitry (53), and a wait line (61) for feeding the wait signal (PWAIT) to the high-speed functional block (51). The circuitry (53) generates the wait signal (PWAIT) from the select line signal (PSEL) and the clock enable signal (PCLKEN).

Abstract: A card, particularly a digital line card is provided for use with a chassis having a slot for receiving the digital line card. The chassis has an Ethernet bus for receiving packets from the line card and has a power supply and power strip for supplying power to the line card. The line card includes a public switched telephone network (PSTN) digital line input/output interface for sending digital signals over the PSTN and for receiving digital signals from PSTN. A line card control processor is connected to the digital line input/output interface. An Ethernet input/output is provided for sending packets over a local network corresponding to signals received from the telephone line and for receiving packets from the local network and forwarding received signals to the digital line input/output interface.