Abstract: An exemplary Peripheral Component Interconnect Express (PCIE) interface card is electrically coupled to a CPU. The PCIE interface card includes a circuit board, a first PCIE interface module arranged on the circuit board, at least one second PCIE interface module arranged on the circuit board, and a PCIE switch arranged on the circuit board. The PCIE switch is electrically coupled to the first PCIE interface module and the at least one second PCIE interface module. The PCIE switch transmits data from the CPU to the first PCIE interface module, and exchanges data between the CPU and the at least one second PCIE interface module.

Abstract: A memory card of one published standard, such as the Multi-Media Card (MMC) or Secure Digital Card (SD), is modified to include the function of a Subscriber Identity Module (SIM) according to another published standard. The controller of the memory card communicates between electrical contacts on the outside of the card and both the memory and the SIM. In one specific form, the memory card has the physical configuration of the current Plug-in SIM card with a few external contacts added to accommodate the memory controller and data memory. In another specific form, the memory card has the physical configuration of the current SD card, including external contacts.

Abstract: An expansion card is provided with a PCB; a PCI slot disposed on the PCB, two connectors disposed on an edge of the PCB, each connector including a plurality of contacts; and a PCIe slot disposed on the PCB. Both the PCI slot and the PCIe slot are electrically connected to the contacts. The expansion card can be connected to a compact computer motherboard.

Abstract: A computer motherboard is provided with a plurality of expansion slots; an expansion card including a PCB, a PCI slot disposed on the PCB, two connectors disposed on an edge of the PCB, each connector including a plurality of contacts, and a PCIe slot disposed on the PCB wherein both the PCI slot and the PCIe slot are electrically connected to the contacts; a PCI card fitted into the PCI slot; and a PCIe card fitted into the PCIe slot. The computer mother can be made compact.

Abstract: A communication speed control application sets the initial communication mode of the USB controller to a full speed mode through a USB driver. If a data transfer start request is received from a USB device using application and if the requested communication speed is a high speed communication mode, the communication speed mode of the USB controller is changed to a high speed mode through the USB driver. The USB application estimates the transfer rate required for the data transfer to be executed and, if the estimated transfer rate is higher than the full speed mode or the transfer rate resulting from subtraction of a predetermined margin from the full speed, the requested communication speed is set to the high speed or is set to full speed otherwise.

Abstract: A main board and a method for dynamically configuring PCIE ports thereof. The main board comprises a PCIE slot, a detecting circuit, an ROM, a chipset and a modifying circuit. The chipset comprises a Management Engine controller and several PCIE ports. The chipset has a Management Engine function or a similar function. The detecting circuit detects the PCIE slot to generate a current state parameter. The ROM stores a default configuration data. The modifying circuit coupled between the chipset and the ROM determines whether the default configuration data needs to be modified according to the current state parameter. When the default configuration data needs to be modified, the modifying circuit modifies the default configuration data according to the current state parameter, so that the Management Engine controller initially configures the PCIE ports according to the modified default configuration data. Thus, the dynamical configuration of the chipset PCIE ports is realized.

Abstract: An electronic device includes a network interface port, a processing unit, a network card, a serial interface, and a microchip. The network interface port connects to a debugging host or connects to an external network. The processing unit is connected to the network interface port. The network card is connected to the processing unit. The microchip is connected to the processing unit through the serial interface. The processing unit determines whether the network interface port is connected to the debugging host or connected to the external network, and selectively connects the network card or the serial interface to the network interface port according to the determination.

Abstract: The present invention provides a server system comprising a first group of mainboard modules and a second group of mainboard modules, each of the first and second groups of mainboard modules including a plurality of mainboard modules. Each mainboard module includes a mainboard and a daughter board electrically connected to the mainboard; a first adaptor and a second adaptor; a hard disk array including a hard disk backplane and a plurality of hard disks, wherein the hard disk backplane is electrically connected to the first adaptor and the second adaptor; a first power control board and a second power control board respectively connected to at least one power supply, wherein the first power control board and the second power control board are electrically connected to the hard disk array; and a management board electrically connected to the first adaptor and the second adaptor.

Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.

Abstract: A new form factor for circuit boards can be employed for directly connecting an expansion board to a motherboard without the need for PCIe hardware such as sockets, retainers, screw and nut assemblies, and connectors. The module on board form factor for an expansion board comprises a first side of the expansion board and a second side of the expansion board located physically opposite to the first side of the expansion board. The first side of the expansion board comprises one or more components configured to provide functionality associated with the expansion board. The second side of the expansion board comprises a plurality of connection leads, such as solder connections, that directly couple the expansion board to the motherboard.

Abstract: In one embodiment, a system having a non-volatile programmable memory and a controller is provided. The system has data pins that are configured to be accessed in one of a first mode and a second mode such that, in the first mode, the system receives information using one of the data pins and, in the second mode, the system receives information using four of the data pins. The system also has a command pin that is configured to receive a first command, a second command, and a third command, the first command requesting a current operation mode of the data pins, the second command requesting operation voltage information of the system, and the third command setting the system into one of the first and second modes. Additionally, the system has a power signal pin configured to receive power for the system.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: A power management apparatus is configured to manage a switch having line-cards with ports. The management apparatus includes a tracking module configured to track activity for each port in a line-card in the switch, and a control module configured to determine whether the line-card is to be disabled. The management apparatus also includes output module configured to initiate a deactivation process for the line-card if all the ports are inactive.

Abstract: The present disclosure provides a method of assigning media access control (MAC) addresses to image paths for a printing system. The method comprises: initializing a MAC address to each image path board in the printing system wherein the printing system includes at least two print engines each having an image path board; modifying a card cage enclosure to include a bit selector for each image path board; and, creating a unique IP address for each MAC address including generating a unique octet for each MAC address. A slot ID is used for the generating of the unique octet for each MAC address having a standard base value.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: The audio player 30, to which a cartridge 10 storing digital audio data of a book for the visually impaired can be attached, is capable of reproducing the audio data read from the cartridge 10, an accommodating section 40, into which the cartridge 10 can be inserted in a state where the thickness direction of the cartridge is arranged in the vertical direction, is formed in a front wall 30a, and a part of a flat surface of the inserted cartridge 10 is exposed from the accommodating section 40.

Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.

Abstract: An information handling system (IHS) remote input/output (I/O) connection system includes an enclosure having a power button, a communication bus connection point, and an audio connection point. A cable dongle extends from the enclosure. The cable dongle has a first end and a second end. The cable dongle also includes a connection from the power button on the enclosure on the first end to a communication connection point plug on the second end, which mates with a connection point plug on a remote I/O device card that enables a parallel (ACPI) S5-capable power button from the IHS to exist on the enclosure. The cable dongle further includes a communication cable coupled to the communication bus connection point on the first end and having a communication connection point plug on the second end. In addition, the cable dongle includes an audio cable coupled to the audio connection point on the first end and having an audio connection point plug on the second end.

Abstract: A method for controlling peripheral component interconnect express (PCI-E) slots of a computer reads processor configuration information of a PCI-E slot unit from a CMOS chip when the computer boots up, and controls a GPIO interface to output a first control signal to a PCI-E multiplexer according to the processor configuration information, to control a PCI-E slot unit of the computer to connect to one of processors of the computer through the PCI-E multiplexer according to the first control signal. Then the method checks whether the processor connected to the PCI-E slot unit is running normally. In addition, the method controls the GPIO interface to output a second control signal to the PCI-E multiplexer if the processor connected to the PCI-E slot unit is not running normally, to control the PCI-E slot unit to connect to another processor through the PCI-E multiplexer according to the second control signal.

Abstract: A data processing assembly includes one or more hosts connected to one or more I/O Expansion Drawers. Assignment state information is stored on the Expansion Drawer to convey the assignment state of Expansion Drawer(s) resources to the hosts. The host retrieves the assignment state and, from it, determines, for each Expansion Buss cable connected to the host, the number of Expansion Cards in the Expansion Drawer to configure. A change in the number of Expansion Cards in the expansion apparatus may necessitate a change in the assignment state, which can be electronically accommodated (as opposed to a manual reconfiguration). Similarly, a failure of an Expansion Buss cable is addressed by electronically reassigning resources to another host or to the same host over a different Expansion Buss cable without the need for further manual intervention. The assembly is capable of verifying correct cable connection between a host and the Expansion Drawer.

Abstract: A system and method for configuring expansion bus links to generate a double-bandwidth link slot are disclosed. An information handling system includes a central processing unit (CPU) and memory operable to store program instructions executable by the CPU. A chip set operably couples the CPU and the memory to a first slot and a second slot. The chipset includes a root port that generates a first link coupled to the first slot and a second link coupled to the second slot. An adapter card is inserted into either of the first or second slots such that the adapter card routes either the first or second link to the slot not populated by the adapter card.

Abstract: A motherboard assembly includes a serial advanced technology attachment dual-in-line memory module (SATA DIMM) with a circuit board, a memory slot, and an interface. An edge connector is set on a bottom edge of the circuit board. A SATA connector is arranged on the circuit board, and connected to a control chip and the interface, enabling a motherboard communication with the SATA DIMM module.

Abstract: A switch apparatus which can switch between two different booting chips includes a first connector, a platform controller hub (PCH) chip, a first basic input output system (BIOS) chip, a switch circuit, and a diagnostic card. The diagnostic card includes a second connector operable to be plugged into the first connector, and a second BIOS chip. When the switch circuit receives a high level control signal from the second BIOS chip, the switch circuit outputs a high level switch signal to first and second trapping pins of the PCH chip, to select the second BIOS chip to bootstrap the motherboard. When the switch circuit does not receive a high level control signal, the switch circuit outputs a low level signal to the first and second trapping pins of the PCH chip, to select the first BIOS chip to bootstrap the motherboard.

Abstract: A PCI riser card includes a printed circuit board and an array of PCI connectors located on the printed circuit board. A plug portion extends from an edge of the printed circuit board and may be inserted into a PCI connector of a system board. The array of PCI connectors includes a first PCI connector and a second PCI connector. The first PCI connector is parallel to the second PCI connector is arranged in inverse relative to the second PCI connector.

Abstract: A stackable form-factor Peripheral Component Interconnect (PCI) device can be configured as a host controller or a master/target for use on a PCI assembly. PCI device may comprise a multiple-input switch coupled to a PCI bus, a multiplexor coupled to the switch, and a reconfigurable device coupled to one of the switch and multiplexor. The PCI device is configured to support functionality from power-up, and either control function or add-in card function.

Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.

Abstract: Methods and systems are described for transmitting and displaying video data after a hot plug event during a start-up dead period. In particular, hot plug events occurring when a toggleable hot plug detection mechanism is use.

Abstract: A serial advanced technology attachment dual-in-line memory module (SATA DIMM) assembly includes a SATA DIMM module with a first circuit board, an expansion slot, and an expansion card with a second circuit board. A first edge connector is arranged on a bottom edge of the first circuit board and includes first power pins connected to a control chip and first storage chips, and first ground pins. A second edge connector connected to the expansion slot is arranged on a top edge of the first circuit board and includes second power pins connected to the first power pins, second ground pins, and four first signal pins connected to the control chip. A third edge connector engaged in the expansion slot is arranged on a bottom edge of the second circuit board and includes third power pins and four second signal pins connected to the second storage chips, and third ground pins.

Abstract: In accordance with embodiments of the present disclosure, methods and systems for displaying information regarding an unengaged plug-in unit are provided. A plug-in unit may include a processor and an information verification module communicatively coupled to the processor. The information verification module may include a non-volatile memory, a controller communicatively coupled to the non-volatile memory, and display communicatively coupled to the controller. The a non-volatile memory may store information. The controller may be configured to, when the plug-in unit is unengaged: (i) read the information from the non-volatile memory, and (ii) communicate control signals based at least in part on the read information. The display may be configured to, when the plug-in unit is unengaged, display graphic images or alphanumeric characters based at least in part on the control signals.

Abstract: An RFID card includes a smartcard controller that receives power from a host device. The RFID card also includes a small inductive device capable of inductive coupling with an RFID reader. The small inductive device is small enough to fit in the form factor of a memory card or SIM card. Enhancement circuits enhance the usable read and write distance of the RFID card.

Abstract: The invention is a portable electronic device comprising a non volatile memory and a memory controller. The portable electronic device comprises a connector having eight pads able to communicate using a protocol of Secure Digital® type. The connector comprises at least one additional pad intended to be linked to an antenna. The additional pad is able to communicate using a protocol of SWP type.

Abstract: A portable mass storage device is used to store large files such as digital pictures, movies and music. The mass storage device has firmware with security mechanisms that limit access to read write operations to ensure reliable operation of the device to prevent unwanted copying or storing of secure content such a copyrighted material. Although the security mechanisms generally limit access, the firmware is operable to work with a virtual machine and allows the virtual machine to access the secure content and work in conjunction with the firmware to read and write data to the mass storage memory, if the virtual machine is present. The virtual machine is either loaded but not activated at the time of manufacture, or is downloaded and activated post manufacture. Any royalty for the virtual machine is paid for only if and when the virtual machine is both present and activated in the device.

Abstract: A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors.

Abstract: Multi-chassis fabric-backplane enterprise servers include a plurality of chassis managed collectively to form one or more provisioned servers. A central client coordinates gathering of provisioning and management information from the chassis, and arranges for distribution of control information to the chassis. One of the chassis may perform as a host or proxy with respect to information and control communication between the client and the chassis. Server provisioning and management information and commands move throughout the chassis via an Open Shortest Path First (OSPF) protocol. Alternatively, the client may establish individual communication with a subset of the chassis, and directly communicate with chassis in the subset. Server provisioning and management information includes events generated when module status changes, such as when a module is inserted and becomes available, and when a module fails and is no longer available.

Abstract: A connector assembly includes first to fifth connectors, two PCIe slots, and an adapter board. When the first connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at the pins of the third connector are transmitted to the second group of pins of the first PCIe slot through the fourth connector, the fifth connector, and the first connector in series. When the second connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at pins of the third connector are transmitted to the fourth group of pins of the second PCIe slot through the fourth connector, the fifth connector, and the second connector in series.

Abstract: The present invention relates to a storage card having selectable contact elements, a terminal capable of receiving said storage card, and method of its operation. The storage card with selectable contact elements, comprises an interface having a plurality of contact elements, a storage card controller, being connected to at least a subset of said contact elements, a storage memory device, being connected to said storage card controller, a switching unit, that is connected to said storage card controller and to at least one of said contact elements of said interface, wherein said storage card controller is connected to said switching unit to controllably select said at least one contact element.

Abstract: A dual bus interface PCB includes a main chipset component, a first type bus interface connector, and a second type bus interface connector. The PCB can be configured at fabrication time to enable a variety of configurations for operation. Optionally, the PCB can also be provided at least one memory chip and a NIC (Network Interface Card) chip. By virtue of having a dual interface, the PCB can be used with either the first type or the second type bus. Furthermore, the dual interface PCB eliminates the need by chipset manufacturers to carry multiple PCB variations of the same product in order to support various bus interfaces. In one embodiment, the PCB is a dual PCI-X/PCI-E interface PCB.

Abstract: The present invention relates to multimedia devices for different age groups with different ability to understand and control such multimedia devices. The invention relates more specifically to a computer device for multimedia functions, where the functions are provided in a control unit/peripheral device for the computer device. The control unit comprises all the essential functional parts and operational codes for its function and can operate alone through the display device or in combination with other peripheral devices.

Abstract: A service is configured by provisioning the service for a facility on a network access device (NAD). The service endpoint is created in an operationally disabled state responsive to provisioning the service. A first network interface unit (NIU) is detected connecting to the facility. The first NIU has an identification code associated therewith. The service transitions to an operationally enabled state responsive to detecting the first NIU connecting to the facility. The identification code is associated with the facility. The first NIU is detected disconnecting from the facility. The service transitions to an operationally disabled state responsive to detecting the first NIU disconnecting from the facility. A second NIU is detected connecting to the facility. The second NIU has an identification code associated therewith. The identification code of the second NIU is compared with the identification code of the first NIU.

Abstract: A cascade-able serial bus device for coupling between a host device and another serial bus device is disclosed. The host device includes a serial bus interface. The serial bus device includes a first connection interface, a second connection interface and a bypassing module. The first connection interface is coupled to the serial bus interface of the host device. The second connection interface is coupled to the second serial bus device. The bypassing module is coupled to a chip select (CS) signal line of the serial bus interface and the second connection interface for selectively bypassing or non-bypassing the CS signal to the second serial bus device.

Abstract: A dual bus interface PCB includes a main chipset component, a first type bus interface connector, and a second type bus interface connector. The PCB can be configured at fabrication time to enable a variety of configurations for operation. Optionally, the PCB can also be provided at least one memory chip and a NIC (Network Interface Card) chip. By virtue of having a dual interface, the PCB can be used with either the first type or the second type bus. Furthermore, the dual interface PCB eliminates the need by chipset manufacturers to carry multiple PCB variations of the same product in order to support various bus interfaces. In one embodiment, the PCB is a dual PCI-X/PCI-E interface PCB.

Abstract: An apparatus for upgrading a standard PC system to a fail-safe computation system, comprising a plug device for plugging into the computation system, a memory module, a microcontroller, and a first device for generating a first time signal, wherein the microcontroller and the first device interact such that the computation system is provided with the first time signal through the plug device device.

Abstract: A motherboard assembly includes a motherboard and an expansion card. The motherboard includes an expansion slot, a hard disk drive (HDD) controller, a power connector, and a central processing unit (CPU). The expansion slot includes a protrusion, idle pins connected to the HDD controller, power pins connected to the power connector, signal pins connected to the CPU. The expansion card includes a circuit board. A storage unit, a display unit, and a power circuit connected to the storage unit and the display unit are all arranged on the circuit board. A notch is defined in a bottom side of the circuit board, to receive the protrusion. An edge connector is arranged on a bottom side of the circuit board and includes control signal pins connected to the storage unit, power pins connected to the power circuit, and bus signal pins connected to the display unit.

Abstract: The information processing system includes a plurality of information processing apparatuses connected via a network. Each apparatus includes one or more modules interconnected via a system bus. At least one of the modules is a network module having a network communication function. The information processing apparatus that inputs an external timing signal functions as a timing master, and the other information processing apparatuses function as a timing slave. The module in the timing master generates time synchronization information in the form of a packet and in the form of a command according to the timing signal and transmits the command to another module and transmits the packet to the timing slave via the network. The network module in the timing slave receives the packet from the timing master, converts the packet to the command to transmit to another module connected to the system bus and included in the timing slave.

Abstract: A modularly constructed field device of process automation technology having a basic card with an executable, basic program, wherein the basic card is expandable by at least one expansion card containing at least one, executable, expansion program. For executing the basic program, the basic card comprises at least one computing unit and a first memory unit matched to memory requirement of the executable, basic program, characterized in that the expansion card comprises at least a second memory unit designed for memory requirement of the expansion program, an automatic detecting of the connected expansion card is provided by the basic card, and, for expanding the basic program by the expansion program, a partial and/or intermittent accessing of the second memory unit by the computing unit is provided.

Abstract: A master-slave communication circuit includes a master device, a number of slave devices, and a bus providing communication channels between the master device and the slave devices. Each slave device includes an identification (ID) address setting unit, a plug-in detecting pin, and a plug-out detecting pin. The identification (ID) address setting unit is connected to the bus to receive an ID address setting signal transferred from the master device, and set an ID address to the corresponding slave device. The master sets the ID addresses of the slave devices according to voltage levels of the plug-in detecting pin and the plug-out detecting pin, to make the ID addresses of the slave devices connected to the bus are different.

Abstract: The present invention relates to a storage device having communication function and expandable memory capacity, which comprises: a top housing having a first open slot at one side; a bottom housing engaged with the top housing for forming an accommodating space; a printed circuit board; a terminal seat; a memory array; a memory controller; a processer; and a wireless communication module. When the storage device is inserted in a portable electronic device, data in the memory array can be transmitted to a remote mainframe through the wireless communication module. Moreover, the storage device has a slot allowing a removable memory card to be inserted for expanding the memory capacity of the storage device.

Abstract: Interface adapter systems and methods are provided. An adapter means can be provided for coupling a first interface to a second interface, the second interface configured to accommodate the coupling of a peripheral device. A detector means can be provided for detecting the peripheral device. A means can be provided for communicating a first signal to a first bus when the peripheral device is not detected. A converting means can be provided to convert a first signal to a second signal having a protocol different than the first and a communications means for communicating the second signal to a second bus can be provided when the detecting means has detected the peripheral device.

Abstract: Precise operation of an accelerator operating member (7) is more difficult to perform in a reversing operation of a vehicle (1) as compared with an advancing operation. Therefore, behavior of the vehicle (1) is not smooth and thus tends to be unnatural. In the reversing operation of the vehicle (1), driving force output from an internal combustion engine (2) is limited in accordance with vehicle acceleration (D). At this time, it is possible to regulate the driving force of the vehicle (1) in conformity to the actual operation of the accelerator operating member (7) by the driver. In addition, limitation of the driving force is not executed in the advancing operation of the vehicle (1). At this time, the vehicle (1) can be driven in a state in which the driving force is comparatively small. Therefore, it is possible to prevent the behavior of the vehicle (1) from being unnatural.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.