Abstract: A computer-implemented method performed by a server including obtaining a stream of live data comprising a plurality of segments; storing the plurality of segments to form a recorded stream; transmitting the plurality of segments as a near-live feed to one or more nodes in a network; transmitting the recorded stream to another node in the network; and transitioning from transmission to the another node of the recorded stream to the near-live feed, the transmission comprising: delaying transmission of the near-live feed to the another node until a new segment of the stream of live data is obtained.

Abstract: A bus monitor circuit includes an access info information/write data FIFO and a read data FIFO to produce a bus monitor output signal on a bus transmitting data between a master and a slave. In a write access ascribed to an attribute of the access information stored at a header of the access information/write data FIFO, the bus monitor circuit directly outputs a bus monitor output signal indicating the access information accompanied with the corresponding write data which is transmitted in the same cycle. In a read access ascribed to an attribute of the access information, the bus monitor circuit waits for the read data FIFO storing the corresponding read data, and then outputs a bus monitor output signal indicating the access information paired with the read data in the same cycle. This guarantees the occurrence order of bus access according to a bus interface protocol enabling pipeline transmission.

Abstract: A serial communication device includes: a data transfer unit configured to repeat storing a predetermined unit of data, received by a receiving unit, in a receiving buffer and transfer data to a storage unit when data of a predetermined size is accumulated in the receiving buffer; a counting unit configured to count one of the number of times the predetermined unit of data is stored and an amount of data accumulated; a monitoring unit configured to monitor a count value counted by the counting unit; and a data identifying unit configured to determine that a current interval is a non-communication interval during which a sending source does not send data if the count value remains unchanged for a predetermined time and identify first data, received after the determination of the non-communication interval, as beginning data of a sequence of data including a plurality of pieces of data.

Abstract: Embodiments relate to collecting extended error data from units within a programmable device. A pointer is accessed that points to a region of memory that contains a list of entries that references the extended error data. The list of entries is walked by adjusting a read pointer to obtain the extended error data. The referenced extended error data is moved to an event log.

Abstract: There is provided a method for updating an internal memory on a semiconductor device from an external memory. The external memory is arranged in a plurality of data portions. The method comprises the steps of writing a first data portion from the external memory to the internal memory, processing the first data portion and, while the first data portion is being processed, once a selected data item is processed, starting to write a second data portion from the external memory to the internal memory. The method may be applied to the processing of software by an embedded processor on a semiconductor device. There is also provided a semiconductor device and a hardware module for the semiconductor device.

Abstract: In one aspect, techniques are provided for adding a packet to a queue. A packet may be received. A determination may be made if the packet is encumbered or unencumbered. The packet may be added to a posted queue, to an encumbered queue, or a unencumbered queue based on the determination. In another aspect, techniques are provided for de-queuing a packet in a posted queue. A posted packet may be de-queued and encumbered queues associated with the packet may be added to unencumbered queues.

Abstract: A non-volatile memory system includes a memory controller that receives commands from a host and identifies commands that can be executed in parallel. The order in which commands are received is recorded so that responses may be provided to the host in the same order in which the commands were received.

Abstract: A video decoding method and apparatus, the video decoding apparatus including: a decoder unit to control a video decoding operation; and a multi-core processor to perform the video decoding operation on an input bitstream by using the decoding unit, wherein the multi-core processor includes: a first core to parse the input bitstream into a plurality of slices and to allocate the slices; and a second core to receive one of the slices, to generate a plurality of macroblocks by decoding the received slice, to alternately store the macroblocks in first and second buffers included in an auxiliary memory thereof, to alternately transfer the macroblocks from the first and second buffers to a main memory, and to reconstruct an image for the macroblocks, wherein the macroblocks are transferred from one of the first and second buffers while the macroblocks are stored in the other one of the first and second buffers.

Abstract: A device such as a turbo decoding device is proposed in which an intermediate buffering device including an address buffering device and an element buffering device is communicatively coupled to a plurality of processing devices and a memory device. During a cycle of a parallel decoding process, the intermediate buffering device receives, from two different processing devices, first and second address information respectively corresponding to first and second elements of a code sequence stored in the memory device. During the cycle, the intermediate buffering device transmits a request for the first element to the memory device based on the first address information and stores the second address information in the address buffering device. Subsequently, during the cycle, the intermediate buffering device receives first element information corresponding to the first element from the memory device and stores the received first element information in the element buffering device.

Abstract: A radio access network (RAN) may receive indications from a wireless communication device (WCD). The RAN may support wireless communication via a plurality of non-overlapping frequency bands, and the plurality of non-overlapping frequency bands may include a low-frequency band and a high-frequency band. The low-frequency band and the high-frequency band may be separated by at least 5 megahertz. The indications may indicate signal strengths at which the WCD received signals from one or more frequencies in the low-frequency band and one or more frequencies the high-frequency band. The RAN may also receive a communication request from the WCD. Based at least in part on receiving the communication request, the RAN may select a frequency from the one or more frequencies in the low-frequency band and the one or more frequencies in the high-frequency band, and may instruct the WCD to communicate using the selected frequency.

Abstract: A method of operating a semiconductor memory device includes receiving a timeout index signal corresponding to a master of the first master group based on a residual capacity of a data buffer of the first master, setting a first timeout value in response to the timeout index signal, and changing an execution order of commands stored in a queue of the semiconductor memory device based on a result of counting the first timeout value and counting a second timeout value corresponding to a master of the second master group.

Abstract: This disclosure is directed to a fast and scalable concurrent queuing system. A device may comprise, for example, at least a memory module and a processing module. The memory module may be to store a queue comprising at least a head and a tail. The processing module may be to execute at least one thread desiring to enqueue at least one new node to the queue, enqueue the at least one new node to the queue, a first state being observed based on information in the tail identifying a predecessor node when the at least one new node is enqueued, observe a second state based on the predecessor node, determine if the predecessor node has changed based on comparing the first state to the second state, and set ordering in the queue based on the determination.

Abstract: A method is provided for a network-attached storage (NAS) server to directly write data to a disk or block device within a storage subsystem. A NAS server Ethernet interface receives a file, and writes the file data into kernel space as PDU segments. A TCP/IP stack maps the file data in kernel space RAM as sequentially ordered segments. The NAS/CIFS server application sends a call specifying file storage data. A zero-copy DMA application receives the call, maps a file offset to a Logical Block Address (LBA) in the block device, and requests that the block device DMA application transfer the file data. Without rewriting the file data in the system RAM, the block driver DMA application transfers the file data, in units of file system blocks, directly from kernel space RAM to the block device, with each file system block written in a single write operation.

Abstract: Systems and methods for protection from buffer overflow vulnerability due to placement new constructs in C++ are provided. A system for protecting from buffer overflow vulnerability due to placement new constructs, comprises a compiler which is capable of receiving a program including a placement new instruction, and runtime which is capable of receiving binary code from the compiler and determining whether the program includes the placement new instruction and whether the placement new instruction would lead to buffer overflow, wherein the runtime is linked to a library including methods for preventing the buffer overflow, and selects a method for preventing the buffer overflow if the runtime determines that the placement new instruction would lead to the buffer overflow.

Abstract: A computing system including a communication network architecture with a transport layer mechanism. The computing system is capable of supporting a multitude of different application protocols involving information and/or data exchange between an operating system instance and various firmware services. The computing system may include an operating system instance with a Generic Transport Driver supporting the application protocols in the operating system instance, a firmware service connected to a Generic Transport Facility via a Generic Firmware Service Interface and a virtual machine with a Generic Transport Passthrough. The Generic Transport Driver of the operating system instance exchanges communication protocol data with the Generic Transport Facility of the firmware component via the generic Transport Passthrough.

Abstract: Processing data packets from a receive queue is provided. It is determined whether packets are saved in a pre-fetched queue. In response to determining that packets are not saved in the pre-fetched queue, a number of packets within the receive queue is determined. In response to determining the number of packets within the receive queue, it is determined whether the number of packets within the receive queue is greater than a number of packets called for by an application. In response to determining that the number of packets within the receive queue is greater than the number of packets called for by the application, an excess number of packets that is above the number of packets called for by the application is saved in the pre-fetched queue. An indication is sent to the application of the excess number of packets. The predetermined number of packets is transferred to the application.

Abstract: An unequal bit-reliability information storage method for communication and storage systems at least includes one storage unit having a first memory and a second memory; the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory. Based on the significance of each bit of the information with the use of the first or second memories of different reliability for storage, the complexity of the storage unit, the production cost and the power consumption can be reduced while maintaining the performance.

Abstract: Disclosed herein are a deskew apparatus and method for Peripheral Component Interconnect (PCI) Express for compensating for a skew. The deskew apparatus includes a lane data input unit, a lane data alignment unit, and a lane data detection unit. The lane data input unit receives 18-bit data from each of lanes of the PCI Express. The lane data alignment unit aligns the 18-bit data using a COM symbol. The lane data detection unit detects a change in a state of alignment of the 18-bit data attributable to deletion or addition of an SKP symbol when the 18-bit data is aligned, and to perform synchronization between the lanes.

Abstract: By connecting, to a bus bridge according to a configuration of a bus system, a monitor circuit including an activation control circuit generating a counter activation signal from an input monitor activation signal, a counter circuit, activated by the counter activation signal, counting the transfer number using a signal of bridge transfer completion indicating an issuance of one transfer from a bus bridge, and outputting a count completion signal when the transfers of the same number as that stuck in the bus bridge indicated by the signal of the transfer number stuck in the bridge is issued when being activated, and a completion control circuit outputting a monitor completion signal upon receiving the count completion signal from the counter circuit, consistency of data may be guaranteed in any bus system without changing the configuration of the bus bridge based on the number of masters accessing the bus bridge.

Abstract: Input data is encoded using a look-up table and then transmitted over a transmission medium as a series of pulses. The look-up table includes data elements. The length of each pulse is calibrated to correspond to one of the data elements in the look-up table. Upon receipt at another end of the transmission medium, the data is decoded using a look-up table. This decoding includes measuring the length of each received pulse to match the measured length to a corresponding one of data elements in the look-up table.

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract: Provided are a storage device, controller, and method for using host transfer rates to select a recording medium transfer rate for transferring data to a recording medium. A host transfer rate of data with respect to a buffer is measured. Provided are a plurality of recording medium transfer rates at which data is transferred between the buffer and the recording medium. A determination is made of an amount of decrease in the host transfer rate. The recording medium transfer rate is selected based on the amount of decrease in the host transfer rate. A transfer rate at which the storage device transfers data is set to the selected recording medium transfer rate.

Abstract: Provided is a PLC data log module and method for storing data in the same, wherein, in a case one or more storages among a plurality of outside storages is attached, a log data is stored in the attached outside storage, the log data is stored in the storage and check is made as to whether the log data is normally stored in the attached outside storage.

Abstract: Systems and methods are described including dynamically configuring a shared buffer to support processing of at least two video read streams associated with different video codec formats. The methods may include determining a buffer write address within the shared buffer in response to a memory request associated with one read stream, and determining a different buffer write address within the shared buffer in response to a memory request associated with the other read stream.

Abstract: Methods and apparatus for eliminating the need for a complete synchronization due to failure of a data protection appliance in a continuous data protection system having a replication splitter. In one embodiment, a continuous data protection system includes a source side having a source side storage array with a splitter and a data protection appliance, where processing includes initiating a source side splitter session, initializing a first I/O tracking mechanism for the splitter session, and activating the splitter to a source side processing active state to continuously push I/O data from the source side to the target side.

Abstract: An asymmetrical processing multi-core system used in a network device is provided. A sub processing core within the asymmetrical processing multi-core system facilitates a main processing core of the asymmetrical processing multi-core system in processing tasks, thereby improving an overall performance of the entire network device and causing the network device to operate more facilely. Different from a conventional processing method, the asymmetrical processing multi-core system does not require moving or copying a large amount of processed packet data, and thus a large amount of memory bandwidth is saved and the power consumption is reduced.

Abstract: A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.

Abstract: In a method for improving the transmission efficiency in a communication system with a layered protocol stack, data packets are processed on an upper protocol layer. Data packets are forwarded to a lower protocol layer for transmission and the transmission is performed with variable channel access delays. The upper protocol layer is notified by the lower protocol layer when a transmission is started to allow a synchronization of timers in the upper protocol layer. If a layer performs a scheduling of data packets for the transmission, a rescheduling is performed alternatively or in addition during a channel access delay. Devices and software programs embodying the invention are also described.

Abstract: A method of controlling the data communication in a communications network having a central data server provided data through multiple data queues. The data arriving at the central data server may be stored in each of the multiple data queues. The data in the multiple data queues may then be supplied to the central data server based on a predetermined schedule.

Abstract: A method and device for operating a data link having multiple data lanes is provided. The method includes supplying first data (such as video data that follows the DisplayPort protocol) on one or more data lanes of a data interface between a video source device and a video sink device. In addition to being video stream data (such as the above mentioned DisplayPort video data) the first data can also be audio stream data (such as DisplayPort audio data), source-sink interface configuration data (such as DisplayPort AUX data) and sink related interrupt data (such as DisplayPort Hot Plug Detect “HPD” data). The method also includes receiving second data on one or more unidirectional data lanes of the data interface. The second data being data other than video stream data, source-sink interface configuration data and sink related interrupt data.

Abstract: A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.

Abstract: A buffer controller includes a first write pointer generation module for generating a first write pointer that points to a first sequence of write locations in a buffer memory, that directs an input module to store a sequence of samples of a real-time signal in a buffer memory. A read pointer generation module generates a plurality of read pointers for a corresponding plurality of output modules, wherein each of the plurality of read pointers points to a sequence of read locations in the buffer memory, in a buffer order, that contain the sequence of samples.

Abstract: A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.

Abstract: A first I/O transaction request is sent to a storage controller for processing by firmware running on the storage controller. A second I/O transaction request is sent to storage hardware without further processing by the firmware running on the storage controller. Since the firmware did not process the second I/O transaction request, information associated with the second I/O transaction is stored in in a circular buffer accessible to the firmware running on the storage controller. The firmware running on the storage controller reads, from the circular buffer, the information associated with the second I/O transaction that was stored in the circular buffer.

Abstract: An improved system and method for deinterleaving a data unit containing chunks of two or more different data types. In an embodiment of the invention, both a device MPU and DMA hardware are used to deinterleave a data unit containing chunks of both compressed data and uncompressed data. The device MPU is used to transfer compressed data from an interleaved data buffer to a compressed data buffer, while the DMA hardware is used to transfer uncompressed data from the interleaved data buffer to a compressed data buffer. By using both the MPU and the DMA hardware, the overall efficiency of the data transfer process is improved.

Abstract: A dynamically controllable buffering system includes a data buffer that is communicatively coupled between first and second data interfaces and operable to perform as an elasticity first-in-first-out buffer in a first mode and to perform as a store-and-forward buffer in a second mode. The system also includes a controller that is operable to detect data rates of the first and second data interfaces, to operate the data buffer in the first mode when the first data interface has a data transfer rate that is faster than a data transfer rate of the second data interface, and to operate the data buffer in the second mode when the second data interface has a data transfer rate that is faster than the data transfer rate of the first data interface.

Abstract: A method for indicating an overload condition of a data storage system, comprises the steps of: defining one or more load indexes, wherein each of the load indexes has an overload threshold; and if one of the load indexes has met its respective overload threshold, providing an indicator of the overload condition of the storage system, else, monitoring the load indexes.

Abstract: A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data value. A multiplexer tree is coupled between the storage locations and a read port. A priority circuit is configured to generate and provide selection signals to each multiplexer of the multiplexer tree, based on a priority scheme. Based on the states of the selection signals, one of the storage locations is coupled to the read port via the multiplexers of the multiplexer tree.

Abstract: Systems and techniques are disclosed that include in one aspect a computer implemented method storing a received stream of data elements in a buffer, applying a boundary condition to the data elements stored in the buffer after receiving each individual data element of the stream of data elements, and producing one or more data elements from the buffer based on the boundary condition as an output stream of data elements sorted according to a predetermined order.

Abstract: An information processing apparatus including a plurality of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier.

Abstract: A buffer circuit includes: a register array including registers in a plurality of stages; and a control circuit configured to rearrange a plurality of pieces of received data in the register in a determined transfer order and to control the register array to sequentially output the plurality of pieces of received data as one piece of transfer data when all the received data is stored, wherein the control circuit controls the register array to store stored data in each register in a preceding stage when the register array outputs the received data, and the control circuit determines a write register in accordance with the transfer order when the register array newly stores the received data and controls the register array to store data stored in the write register in a following stage of the write register and to store the new received data in the write register.

Abstract: An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal.

Abstract: A queue control circuit controls the placement and retrieval of a plurality of tasks in a plurality of types of virtual queues. State registers are associated with respective tasks. Each of the state registers stores a task priority order, a queue ID of a virtual queue, and the order of placement in the virtual queue. Upon receipt of a normal placement command ENQ_TL, the queue control circuit establishes, in the state register for the placed task, QID of the virtual queue as the destination of placement and an order value indicating the end of the queue. When a reverse placement command ENQ_TP is received, QID of the destination virtual queue and an order value indicating the start of the queue are established. When a retrieval command DEQ is received, QID is cleared in the destination virtual queue.

Abstract: Described herein is a system (102) having a virtualization and switching system configured to virtualize I/O devices (108) and perform switching of the I/O devices (108) and I/O requests. The virtualization and switching system (102) includes a peripheral virtualization controller (PVC) (204), at least one device control module (206) connected to the PVC (204), and at least one command parser (210). The PVC (204) is configured to manage I/O virtualization and I/O command access of different I/O devices (108). The device control module (206) is configured to store configuration and I/O device registers, implemented by the PVC (204) to enable virtualization of I/O devices (108). The device control module (206) also implements the I/O command and switching logic to perform graceful handling of the I/O commands and virtualized I/O devices between multiple host processors (104).

Abstract: Systems and methods are provided to enable a near-end receiver to control the far-end transmitter's data transmission such that the near-end receiver's TC data buffers do not overflow. In an embodiment, a high waterline and low waterline implemented into a near-end receiver are used to determine when the near-end receiver's TC data buffers are near maximum capacity. In an embodiment, the near-end receiver transmits a Packet Transfer Mode (PTM) All Idle Out Of Sync (AIOOS) codeword to the far-end transmitter when the high waterline is reached, and the near-end receiver stops transmitting the AIOOS codeword when the low waterline is reached.

Abstract: A router has multiple channel inputs and multiple channel outputs and a switch core for selectively connecting at least two of the channel outputs to respective channel inputs. Each channel output is connected to an output signal path containing a FIFO register and the router is configured so that first and second channel outputs are connected to a pair of channel inputs respectively. The router configuration is changed so that the first and second channel outputs are connected to first and second channel inputs respectively. The FIFO registers in the output signal paths of the first and second channel outputs are forced to equal fullness.

Abstract: A method for read pointer maintenance of a buffering apparatus, which is arranged to buffer data of a multi-tile encoded picture having a plurality of tiles included therein, includes the following steps: judging if decoding of a first tile of the multi-tile encoded picture encounters a tile boundary of the first tile; and when it is judged that the tile boundary of the first tile is encountered, storing a currently used read pointer into a pointer buffer, and loading a selected read pointer from the pointer buffer to act as the currently used read pointer.

Abstract: Records or filemarks read from data segments are aggregated into at least one single data segment. The records and the filemarks are reorganized and restructured in the single data segment such that buffer utilization is improved.

Abstract: One or more out-of-band input signals (GPIO) are handled and efficiently embedded into a USB capture stream. In order to conserve resources, the state of the input signals can be sent only when a change occurs. The signals are accurately time-stamped, and then presented within the context of the captured USB data. In order to provide maximum visibility, if the digital inputs occur during a normally filtered multi-packet sequence, the filter is canceled and the surrounding packets will also be sent to an analysis computer. Furthermore, because digital inputs may happen during a USB packet, the digital inputs are queued in a FIFO buffer until there is an opportunity to send the digital inputs. Even though the state of the inputs may be sent at a later time, the state of the inputs may be time-stamped when the state of the inputs is perceived by the analyzer.

Abstract: A relay and a data processing method are provided. The relay includes: a detection unit for classifying and detecting event oriented monitoring data and non-event oriented monitoring data from monitoring data; a storage unit for storing the detected monitoring data; a communication unit for receiving a request signal of the monitoring data from a monitoring device and transmitting corresponding monitoring data in response to a transmission request signal of the monitoring data; and a control unit for extracting event oriented monitoring data from the monitoring data and performing a control to transmit the monitoring data requested from the monitoring device.