Abstract: A method for communicating data between peripheral devices and an embedded processor that includes receiving, at a data buffer unit of the embedded processor, the data from a peripheral device. The method also includes copying data from the data buffer unit into the bridge buffer of the embedded processor as a bridge buffer message. Additionally, the method includes creating, after storing the data as a bridge buffer message, a peripheral device message comprising the bridge buffer message, and sending the peripheral device message to a thread message queue of a subscriber.

Abstract: Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a T_STORE operation, comparing a first address associated with the T_STORE operation with a plurality of addresses associated with previous T_STORE operations, wherein the previous T_STORE operations are part of the same transaction as the T_STORE operation and the entries corresponding to the previous T_STORE operations are stored in the merge window; in response to a match between the first address and a second address, associated with a second T_STORE operation, of the plurality of addresses, merging a first entry corresponding to the first T_STORE operation with a second entry corresponding to the second T_STORE operation; and consolidating results associated with the first T_STORE operation with results associated with the second T_STORE operation.

Abstract: An expandable wireless storage device is provided that includes an interface slot, internal memory, a wireless interface and an aggregated file system view providing component. An external memory, which stores a first subset of multi-media files, can be physically coupled with the expandable wireless storage device using the interface slot. A second subset of multi-media files can be stored on the internal memory. A multi-media file of the multi-media files can be streamed to a playing device using the wireless interface. The internal memory is used as a buffer when the multi-media file resides on the external memory. An aggregated file system view providing component provides an aggregated file system view of the multi-media files.

Abstract: An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtual machine instructions configured to access the volatile memory with a first virtual machine. The instructions including second virtual machine instructions configured to access the volatile memory with a second virtual machine. The instructions including virtual machine monitor instructions configured to page data out from a shared memory to a reserved memory section in the volatile memory responsive to the first virtual machine or the second virtual machine paging the data out from the shared memory or paging the data in to the shared memory. The shared memory is shared across the first virtual machine and the second virtual machine. The volatile memory includes the shared memory.

Abstract: A processor includes a first transmitting unit that transmits, when receiving from a second processor a transmission request indicating transmission of target data which is read from a main storage unit and stored in the first processor, a transfer instruction to the first processor, the transfer instruction indicating transfer of the target data and state information to the second processor, the state information indicating a state of the target data used when the second processor reads and stores the target data. The processor includes a second transmitting unit that transmits acquisition information indicating acquisition of the target data to the second processor before receiving a response to the transfer instruction transmitted by the first transmitting unit from the first processor.

Abstract: A data processing unit includes a main controller configured to receive data requirement information from a host and to generate processing information based on the data requirement information; a pre-processing unit configured to pre-process n types of data output from the main controller according to the processing information and to generate n types of pre-processed data where n is an integer equal to or greater than 2; and a pre-processed data storing unit configured to store the n types of pre-processed data and to output the n types of pre-processed data in an output order determined based on the processing information, wherein the processing information includes information about at least one of type, format, order, size and transmission mode of the n types of pre-processed data.

Abstract: A method and system for performance monitoring of a multimedia content distribution network (MCDN) includes a probe device configured to capture input and output data with respect to a network terminal device at an MCDN client premises. The input data, representing network data sent to the MCDN client for display, may be buffered along with the output data, representing audio and video data generated using the input data. When an anomaly event, such as a display error, occurs, the probe device may record the buffered input and output data, including data acquired prior to the anomaly event. The input and output data may be analyzed to determine a source or origin of the anomaly event. The probe device may also certify that the MCDN and/or the network terminal device was operating normally.

Abstract: A data transfer apparatus includes a plurality of input ports, a plurality of output ports and a switch unit between the plurality of input ports and the plurality of output ports. Each input port includes an input buffer configured to store input data including destination information indicating destinations of respective pieces of the input data, a first buffer monitoring unit configured to monitor a first usage rate of the input buffer, and a first frequency control unit configured to control a first operating frequency of the input buffer on the basis of the first usage rate. Each output port includes an output buffer configured to store output data, a second buffer monitoring unit configured to monitor a second usage rate of the output buffer, and a second frequency control unit configured to control a second operating frequency of the output buffer on the basis of the second usage rate.

Abstract: A data processing apparatus may include: a data conversion unit configured to designate one-transfer data as one transfer unit and designate a predetermined number of transfer units as one conversion unit when a plurality of input data sequentially input is converted into transfer data of which the number of bits is the same as that of a data bus having a predetermined number of bits, and the transfer data is sequentially transferred, and arrange the input data in the transfer data within the conversion unit. The data conversion unit may include: a data generation unit, a first data arrangement change unit, and a first data selection unit configured to sequentially select the changed data in which the position of the input data is changed by the first data arrangement change unit and output the selected changed data as the transfer data in the data conversion unit.

Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.

Abstract: A first device of a Multimedia Over Coax Alliance (MoCA) network may communicate with a second device of the MoCA network to control power-save operation of the second MoCA device. The first device may control the power-save operation of the second MoCA device based on an amount of data stored in a buffer, wherein the data stored in the buffer is destined for the second device. The buffer may be in a third device which sends the data to the second device, and/or the buffer may be in the first device. The first device may be operable to buffer data destined for the second device while the second device is in a power-saving state.

Abstract: A device includes a link interface circuit, a first plurality of allocated buffers, and a second plurality of non-allocated buffers. The link interface circuit is operable to communicate over a communications link using a plurality of virtual channels. A different subset of the plurality of allocated buffers is allocated to each of the virtual channels. The non-allocated buffers are not allocated to a particular virtual channel. The link interface circuit is operable to receive a first transaction over the communications link and assign the first transaction to one of the allocated buffers or one of the non-allocated buffers.

Abstract: A Solid State Drive (SSD) controller is disclosed. When a data read command is transmitted by a host, the SSD controller may select a representative pointer from at least one first pointer by checking a point in time when data writing is completed in a buffer by at least one memory, read the data from the buffer by referring to a second pointer, and transmit the read data to the host, based on the representative pointer.

Abstract: Buffer memory reservation techniques for use with NAND flash memory include dynamically reserving regions of the buffer memory, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.

Abstract: Data transmission from a data storage device (DSD) to a host. Data is received from a volatile memory of the DSD in an ingress buffer of the DSD and the data from the ingress buffer is formatted into formatted data. A size of data buffered in the ingress buffer is compared to a frame ingress size for data to be buffered in the ingress buffer for a frame to be transmitted to the host. It is determined based on the comparison whether to buffer all of the formatted data for the frame in an egress buffer of the DSD before transmission to the host, or to transmit at least a portion of the formatted data for the frame to the host before all of the formatted data for the frame is received in the egress buffer.

Abstract: Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer.

Abstract: The components of communication network device ingress systems and methods cooperate to manage information ingress and prevent denial of service attempts. A classifier classifies incoming information. A classification filter filters the information on a classification basis to prevent denial of service. The classification filter includes a classification filter counter for tracking the flow of information associated with the classification filter. A zero value in the classification filter counter indicates that a buffer capacity limit associated with the classification is reached. The counter permits information to flow to a packet buffer if the classification filter counter value is not zero and discards information if the classification filter counter value is zero. In one exemplary implementation the classification filter counter decrements a classification filter counter value when the information is placed in the buffer.

Abstract: A functional unit is provided which allows for fast, parallel data read, write, and manipulation operations. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, a plurality of memory tables, a combinational logic circuit, and a decoder. Each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. The combinational logic circuit receives lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code.

Abstract: A direct memory access circuit includes a buffer handler configured to store received data within a buffer in a buffer memory coupled to the direct memory access circuit and to generate a descriptor for the buffer. The direct memory access circuit further includes a descriptor handler coupled to the buffer handler. The descriptor handler is configured to determine a descriptor address for the descriptor and to store the descriptor at the determined address within a descriptor memory coupled to the direct memory access circuit.

Abstract: A storage network includes at least one storage processor. At least one switch is coupled to the at least one storage processor. At least one nontransparent bridge is coupled to the at least one switch. The at least one nontransparent bridge includes at least one addressable endpoint. At least one storage device is coupled to the nontransparent bridge. At least one baseboard management controller is coupled to the at least one addressable endpoint.

Abstract: A time-sharing buffer access system manages a buffer among plural master devices. Plural buffer handling units are operable to associatively couple the master devices, respectively, and a first end of each buffer handling unit is used to independently transfer data to or from the associated master device. A second end of each buffer handling unit is coupled to a buffer switch. A time slot controller defines a time slot, during which one of the buffer handling units is selected by the buffer switch such that data are only transferred between the selected buffer handling unit and the buffer.

Abstract: A control method includes allocating a plurality of virtual disks to a virtual storage allocated to a physical storage, associating data with one of the plurality of virtual disks which has been instructed to store the data and storing the data in the physical storage, and selecting, by a processor, one of the plurality of virtual disks as a data movement target virtual disk from which data is to be moved in accordance with a network bandwidth of the physical storage corresponding to the virtual storage when free space in the virtual storage exceeds a threshold value.

Abstract: A system and method for transmitting data bursts over a constant data rate link that transmits a continuous stream of data is disclosed. A transmitter node accesses a region in a memory to form a continuous stream of data, wherein the region is a circular buffer and is accessed in a circular manner. The continuous stream of data is transmitted from the circular buffer, wherein the circular buffer initially contains dummy data. A data burst is stored in the circular buffer at a selected location and a control message is transmitted with an indication of the selected location of the data burst in the circular buffer. The data burst is transmitted as part of the continuous stream of data from the circular buffer.

Abstract: A method and apparatus of performing a data transmission from an electronic device or a peripheral device of an electronic device to a peripheral device of a remote electronic device is disclosed. One example method of performing the data transmission may include transmitting data designated for the remote peripheral device to a local virtual device object. The data that is received by the local virtual device object is transmitted via at least one communication interface or peripheral device of the electronic device to at least one remote communication interface or peripheral device of the remote electronic device. The data arriving at the least one remote communication interface or peripheral device of the remote electronic device is received by a remote virtual device object and transmitted to the designated remote peripheral device.

Abstract: An audio device and a method of operating the same are provided. The audio device includes a storage unit, a first memory and a second memory, a hardware decoder, a software decoder, a first direct memory access (DMA) block, a second DMA block, and a controller. The controller converts the audio device from an ultra low power mode in which the first PCM information is transmitted to an audio interface buffer through the first memory, the hardware decoder, and the first DMA block or a low power mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the first DMA block to a normal mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the second DMA block.

Abstract: Data is written from a first domain to a FIFO memory buffer in a second domain. The first domain uses a first clock signal, the second domain uses a second clock signal and the memory buffer uses the first clock signal that is delivered alongside the data. The data is read from the memory buffer using the second clock signal. A read pointer is adjusted and synchronised with the delivered first clock signal. A token is generated using the delivered first clock signal, based on the read pointer. The token represents a capacity of the memory buffer having been made available. The token is passed to the first domain and synchronised with the first clock signal. The writing of data to the memory buffer is controlled based on a comparison between the synchronised token and a previously received token.

Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.

Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

Abstract: In a data network, a node determines whether to handle data-dependent events using the node's hardware interrupt buffer or instead using an available fallback action. The node classifies each detected event as being one of a plurality of different categories of events and determines, based on the classified category, whether to handle the detected event using the hardware interrupt buffer of the node. Each different event category can be assigned its own scale factor, where the available (i.e., currently unused) capacity of the hardware interrupt buffer is allocated based on those programmed scale factors. If the node determines to handle the detected event using the hardware interrupt buffer, then the node stores a hardware interrupt corresponding to the detected event in the hardware interrupt buffer. Otherwise, the node handles the detected event using a fallback action.

Abstract: Described is a data switching device comprising a plurality of input ports, a plurality of output ports, a plurality of first conductive connectors, a plurality of second conductive connectors, a plurality of crosspoint regions, and a memory device at each crosspoint region. The first conductive connectors are in communication with the input ports. The second conductive connectors are in communication with the output ports. Each crosspoint region includes a first conductive connector and a second conductive connector. The memory device is coupled between the first conductive connector and the second conductive connector for exchanging data between the input ports and the output ports.

Abstract: A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage nodes has a determined maximum latency.

Abstract: A method for controlling a memory operation includes determining a number of commands for each memory address based on information of requests stored in an interface buffer and a scheduler buffer, determining a control state of the memory operation according to a command type with a largest number of commands, and determining types of a request transmitted to the scheduler buffer from the interface buffer and a request output from the scheduler buffer according to a control state of the memory operation. Other embodiments including an apparatus for controlling a memory are also disclosed.

Abstract: A universal serial interface (USI) includes two transceivers configured to separately support a plurality of serial communication standards; a buffer configured to store received data and data to be transmitted; and a transceiver controller configured to connect one of the two transceivers to the buffer based on a configuration signal received from outside of the USI.

Abstract: A system includes a plurality of processors, a message fabric, and a plurality of hardware units. Each of the plurality of processors comprises a plurality of communication FIFOs and has an instruction set including at least one instruction to send a message via at least one of the plurality of communication FIFOs. The message fabric couples the processors via at least some of the plurality of communication FIFOs . Each of the processors is associated with a respective one or more of the hardware units and coupled to each of the associated hardware units via respective hardware unit input and output communication FIFOs. Each of the processors is enabled to send messages to others of the processors via respective processor output communication FIFOs. The respective hardware units associated with each of the processors are enabled to send messages to the associated processor via the respective hardware unit input communication FIFOs.

Abstract: A controller for a storage device is connected to a host system and the storage device. A buffer memory includes first and second storage areas. A timer counts a preset given time in response to an instruction to start counting and sends a deadline notification when A given time is elapsed. A command responding portion, when receiving a read command from the host system, instructs the timer to start counting and thereafter outputs a read instruction to read data from the storage system. A data processing portion, in response to the read instruction by the command responding portion, reads specified data from the storage device and holds the read data in the second storage area of the buffer memory. A read control portion sends the host system the data held in the second storage area of the buffer memory when the deadline notification is received from the timer.

Abstract: Partitioning of a variable length scatter gather list including a processor for performing a method that includes requesting data from an I/O device comprising an I/O buffer. The requesting includes initiating a subchannel. The method further includes determining whether the subchannel supports data divisions by requesting SSQD data from the I/O device and inspecting at least one bit in the SSQD data. A determination is made whether the requested data includes a metadata block in response to determining that the subchannel support data divisions. Also, the subchannel is notified that the requested data includes the metadata block in response to determining that the requested data includes the metadata block. A location of storage is identified in an SBAL in response to notifying the subchannel.

Abstract: A multiprocessing system executes a plurality of processes concurrently. A process execution circuit (10) issues requests to access a shared resource (16) from the processes. A shared access circuit (14) sequences conflicting ones of the requests. A simulating access circuit (12) generates signals to stall at least one of the processes at simulated stall time points selected as a predetermined function of requests from only the at least one of the processes and/or the timing of the requests from only the at least one of the processes, irrespective of whether said stalling is made necessary by sequencing of conflicting ones of the requests. Thus, part from predetermined maximum response times, predetermined average timing can be guaranteed, independent of the combination of processes that is executed.

Abstract: Systems and methods presented herein provide for tunneling PCIe data through a SAS domain. a data system includes a SAS expander, a PCIe target device coupled to the expander, and a SAS controller communicatively coupled to a host system and the expander. The controller is operable to open a connection with the expander via the SAS protocol, and to transport packet data between the target device and the host system through the connection via the PCIe protocol. For example, the controller and the expander may be operable to buffer packets of data in the connection. The controller may issue a number of the data packets to be transferred in the connection. Then, the issued number of data packets are transported between the target device and the host system through the connection via the PCIe protocol.

Abstract: A mobile device, and a method and computer program product for displaying a streaming video image at the mobile device during a packet based video call via a channel established over a wireless communication network, the method includes receiving a speed indication of the mobile device and sending said indication to a communication client application; and responsive to receiving said indication, the communication client application is configured to limit the amount of information in the streaming video image that is supplied for display on a display of the mobile device during the video call when the speed of the mobile device is greater than, or equal to, a first predetermined speed threshold.

Abstract: A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received symbols to locations pointed to by a write pointer and output to downstream logic, symbols stored at locations pointed to by a read pointer. The receiver may also include a symbol drop unit that disables the write pointer in response to receiving a start alignment symbol, and enables the write pointer in response to receiving an end alignment symbol. The receiver also includes an alignment unit that disables the read pointer in response to detecting that the end symbol has been received at least one lane but not all lanes. In addition, the alignment unit may enable the read pointer in response to a determination that the end symbol has been received on all lanes.

Abstract: A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.

Abstract: A system and method operable to manage a message queue is provided. This management may involve out-of-order asynchronous heterogeneous remote direct memory access (RDMA) to the message queue. This system includes a pair of processing devices, a primary processing device and an additional processing device, a memory in storage location and a data bus coupled to the processing devices. The processing devices cooperate to process queue data within a shared message queue wherein when an individual processing device successfully accesses queue data the queue data is locked for the exclusive use of the processing device. When the processing device acquires the queue data, the queue data is locked and the queue data acquired by the acquiring processing device includes the queue data for both the primary processing device and additional processing device such that the processing device has all queue data necessary to process the data and return processed queue data.

Abstract: According to one embodiment, a buffer management device includes a buffer memory, a current-credit retaining module, a reserved-credit retaining module, a transfer controller, and a subtractor. The buffer memory manages a storage area in a credit unit representing a predetermined data size and temporarily stores data transferred from an external device. The current-credit retaining module retains the number of credits currently available for the buffer memory as a current credit value. The transfer controller registers the number of credits necessary to temporarily store the data in the reserved-credit retaining module as a reserved credit value prior to the transfer of the data from the external device to the buffer memory. The subtractor subtracts the reserved credit value registered in the reserved-credit retaining module from the current credit value retained by the current-credit retaining module and outputs a subtraction result as an available credit value.

Abstract: According to one embodiment, a media system communicates with an aggregate device that includes multiple media output devices. When providing media data for presentation, the system adjusts for device clock drift by resampling the media data provided to a media output device based at least in part on a device clock rate difference between a device clock of one of the media output devices and a device clock of another of the media output devices.

Abstract: One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during an initialization operation of the computing system. The initialization operation initializes components of the computing system.

Abstract: A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.

Abstract: An adaptive multi-thread buffer supports multiple writer process and reader processes simultaneously without blocking. Writer processes are assigned a reserved write slot using a writer index that is incremented for each write request. When a reserved write slot is not null, the buffer is resized to make room for new data. Reader processes are assigned a reserved read slot using a reader index that is incremented for each read request. When data is read out to the reader process, the read slot content is set to null. When a writer process attempts to write null data to a write slot, the buffer replaces the null write data with an empty value object so that content of the buffer is null only for empty slots. When an empty value object is read from a slot, the buffer replaces the content with null data to send to the reader process.

Abstract: A first-in first-out (FIFO) memory device includes a main FIFO unit, an auxiliary FIFO unit and a control unit. The main FIFO unit includes first through N-th one-port memories, each of which including M entries, where N and M are integers greater than or equal to two. The auxiliary FIFO unit includes one dual-port memory having M entries. The control unit performs a write operation by receiving a write command and data and storing the data in one of the main FIFO unit and the auxiliary FIFO unit based on an operating mode, and performs a read operation by receiving a read command and reading the data from one of the main FIFO unit and the auxiliary FIFO unit based on the operating mode.

Abstract: A storage device is provided which includes a nonvolatile memory device and a controller configured to write meta information, indicating that a transfer of unit data is completed, in a buffer memory when the unit data is transferred to the buffer memory from the nonvolatile memory device.

Abstract: Apparatuses, systems, and methods are disclosed for a virtual channel for data transfers between devices. A method includes presenting an address space for a memory buffer. The address space may be larger than a physical capacity of the memory buffer. A method includes controlling, from a peripheral device, a rate at which a data source transfers data to a memory buffer using a presented address space based on a rate at which a data target transfers data from the memory buffer using the presented address space so that an amount of data stored in the memory buffer remains at or below a physical capacity of the memory buffer.