Abstract: Embodiments of the invention improve the cache hit ratio of read data. A hard disk drive (HDD) according to an embodiment of the present invention determines whether the read buffer should be used in its entirety or the partial continuous space should be used to read read-data from the magnetic disk. When the HDD determines use of the partial continuous space, the HDD specifies the sub-buffer which is a continuous space wherein the leading-end position and the trailing-end position are coupled to each other, and executes data writing to the sub-buffer in parallel with data reading from the sub-buffer and transmission thereof to the host. The sub-buffer capacity coincides with the data length of the back data.

Abstract: In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A reading section reads the accumulated data successively from the FIFO buffer memory at an variable output rate so that the data amount residing in the FIFO buffer memory varies temporally. A detector detects a current data amount residing in the FIFO buffer memory, and a current direction of variation of the data amount residing in the FIFO buffer memory. A loop filter generates control information according to both of the detected current data amount and the detected current direction of variation of the data amount. A controller regulates the output rate according to the control information so as to promptly converge the current data amount residing in the FIFO buffer memory to a target data amount.

Abstract: Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According to some of these embodiments, a multi-queue FIFO memory device includes a write flag counter register file that is configured to support flow-through of write counter updates to at least one read port of the write flag counter register file. This flow-through occurs when an active write queue and an active read queue within the FIFO memory device are the same. A read flag counter register file is also provided, which supports flow-through of read counter updates to at least one read port of the read flag counter register file when the active write queue and the active read queue are the same.

Abstract: A storage medium drive is controllable by a storage medium array controller. the storage medium array controller receives a data storage medium drive information and the storage medium array controller sets a data transmission parameter with respect to the storage medium drive based on the data storage medium drive information.

Abstract: A system for buffering data received from a network comprises a network socket, a plurality of buffers, a buffer pointer pool, receive logic, and packet delivery logic. The buffer pointer pool has a plurality of entries respectively pointing to the buffers. The receive logic is configured to pull an entry from the pool and to perform a bulk read of the network socket. The entry points to one of the buffers, and the receive logic is further configured to store data from the bulk read to the one buffer based on the entry. The packet delivery logic is configured to read, based on the entry, the one buffer and to locate a missing packet sequence in response to a determination, by the packet delivery logic, that the one buffer is storing an incomplete packet sequence. The packet delivery logic is further configured to form a complete packet sequence based on the incomplete packet sequence and the missing packet sequence.

Abstract: A buffer architecture enables linked lists to be used to administer virtual output queue buffering. The buffer has three random access memories (RAMs). A data RAM holds data. A free RAM holds a linked list of entries defining free space in the data RAM. Destination RAM holds a linked list of entries defining data in the data RAM to be forwarded to a destination.

Abstract: To provide an inexpensive display panel driver unit with a built-in memory, which is capable of achieving the same operation as that obtained in using a dual port memory by employing a single port RAM without reduction in an operation speed. A reservation buffer 14 for storing an address and data in a memory writing is provided. When a display reading and a memory writing occurs simultaneously and row addresses of the memory writing and the display reading agree with each other, the memory writing is executed and also read data from addresses except a write address together with write data into the write address are used as data of the display reading. Also, when the row addresses of the memory writing and the display reading are different from each other, the write address and data are stored in the reservation buffer and also the display reading is executed. The similar mediation is applied in executing the reserved writing.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of configuration objects according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.

Abstract: An apparatus such as a Device Wire Adapter (DWA) with improved buffer management and packaging of Wireless Universal Serial Bus (WUSB) isochronous packets for transmission to a host. The apparatus includes an isochronous IN endpoint that receives data segments from a device function. Memory is associated with the endpoint and includes an endpoint buffer configured in a loop and a plurality of registers. The apparatus includes an endpoint controller that stores the received data segments sequentially in the loop buffer, assigns a set of the registers to each of the stored data segments, and stores additional packet information in the registers for each of the data segments rather than in the endpoint buffer. The additional packet information includes presentation time for the stored data segment derived from a sample time of a last segment in the buffer and a time interval between two consecutive data segments in the buffer.

Abstract: A memory buffer comprises a first asynchronous latch chain interface connectable to at least one of a memory controller and a memory buffer, a second data interface connected to a memory device, and a circuit comprising a buffer and a processor, the circuit being coupled to the first and the second interfaces, so that data can be passed between the first interface and the buffer and between the second interface and the buffer and so that the processor is capable of processing at least one of the data from the first interface to the second interface and the data from the second interface according to a data processing functionality, wherein the data processing functionality of the processor is changeable by a programming signal received via an interface of a memory buffer.

Abstract: An apparatus and method is provided to facilitate Input/Output (I/O) transfer in resource limited storage environment. Scatter gather list, segment and memory data buffer allocation are dynamically managed. I/O transfer performance is increased through the use of a data cut-through buffer mechanism.

Abstract: A file allocation system for a hard disk drive includes a memory with driver logic and a processor configured with the driver logic to receive a request to allocate hard disk space of a defined size for a buffer file. In some embodiments, the processor is configured with the driver logic to allocate clusters for the buffer file from a plurality of clusters on the hard disk, wherein the clusters for the buffer file store media content instances. In some embodiments, the processor is configured with the driver logic to designate a portion of the clusters of the buffer file for at least one non-buffer file such that the non-buffer file is permitted to share the portion of the clusters of the buffer file with the buffer file.

Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: A transfer controller (or a host controller) issues IN tokens to a plurality of USB devices connected to USB and including first and second USB devices. When data including destination information which specifies the second USB device as a destination has been received in response to an IN token issued to the first USB device, the transfer controller issues an OUT token to the second USB device and transmits the received data from the first USB device to the second USB device. The transfer controller issues an IN token to at least one of the USB devices which has declared itself to be a local area network (LAN) node.

Abstract: Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

Abstract: A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the second clock rate is higher than the first clock rate. The circuit comprises a first buffer 13 coupled to the first component 11; a second buffer 14 coupled to the second component 12; and a copy/access controller 15, 16, 17 connected to the first buffer 13, the second buffer 14, and the second component 12. The copy/access controller 15, 16, 17 is operable to copy data from the first buffer 13 to the second buffer 14 when the first buffer 13 is substantially full. It is also operable to prompt the second component 12 to access the second buffer 14 when the data is copied from the first buffer 13. The buffers can be random access memories or shift registers, and can be integrated onto the same semiconductor die as either the first or second component.

Abstract: An apparatus and method for scheduling requests to a source device is provided. The apparatus comprises a high-priority request queue for storing a plurality of high-priority requests to the source device; a low-priority request queue for storing a low-priority request to the source device, wherein a priority of one of the high-priority requests is higher than the priority of the low-priority request; a history counter for storing an information related to at least one requesting interval between two adjacent high-priority requests; and a scheduling module for scheduling the high-priority requests and the low-priority request according to the information.

Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.

Abstract: A switch comprising front-end and back-end application specific integrated circuits (ASICs) is disclosed. Frame storage and retrieval in the switch is achieved by dividing a frame into equal sized portions that are sequentially stored in switch memory during an assigned time slot. Control logic coupled to the front-end and back-end ASICs assigns the time slot either dynamically or statically.

Abstract: Loss of data to be transmitted from a peripheral device to a host before a software hierarchy of the host side completely starts is prevented. In a time period before a host completely reached a normal operation mode from a sleep mode, data outputted from a receiver is stored in second buffer memory of a communication control device. When the host reaches the normal operation mode, an application hierarchy in the host transmits a transmission approval command to a control unit, and then the data is transferred from the second buffer memory to first buffer memory. Since communication between the host and the communication control device of the receiver is resumed and then the data stored in the first buffer memory is sent to the host through a USB line, loss of the data can be prevented.

Abstract: A system and method for rendering images, and performing operations such as windowing and leveling, when the parameters of a client appliance are known and rendering images when the parameters of a client appliance are unknown. The invention also considers the rendering from the client appliance perspective and the server appliance perspective.

Abstract: A method for transferring data in a storage system is provided. The method includes setting a catch-up threshold for accepting data requests from a port where the queue value corresponds to a number of requests collected from an input queue for every CPU interrupt, and the input queue receives requests from the port and stores the requests to be collected by a CPU. The method also includes adjusting the catch-up threshold to reduce an imbalance between the number of requests made to the input queue and a number of requests made to an output queue in a particular period of time where the output queue receives requests from the CPU and stores the requests to be gathered by the port.

Abstract: A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a register with a processor, continuously accessing data from the register with the processor if the data in the register is valid, enabling an identifier register with the processor if the data in the register is invalid, transmitting an interrupt signal to the processor, disabling the identifier register with the processor, and accessing the data from the register with the processor.

Abstract: The present invention relates to a method using windows of data, a window (w) comprising data to be written and to be read and having a size. It is characterized in that it comprises:* A step of writing a current window of data into a unique buffer (BUF) in a first address direction, said first address direction being at an opposite direction from an address direction of the writing of a preceding window of data, said writing of said current window beginning at an address where no data of the preceding window of data have been written, said buffer (BUF) having a length greater than the maximum size of the windows of data, and* A step of reading the data of said preceding window of data from said unique buffer (BUF), from a reading address equal to a last written address of the same preceding window of data, said reading being made simultaneously to said writing of the current window of data and in the same first address direction.

Abstract: An electronic communications device including a user input device for inputting characters; and buffering and communications systems for storing in a buffer characters input by the user input device, and transmitting the content of the buffer over a communications link when there is a pause in input by the user input device for a predetermined time duration. The content of the buffer may also be transmitted over the communications link when the amount of stored characters in the buffer reaches a predetermined size, or when a designated submit key is detected.

Abstract: A command accumulation tool, a testing tool for a queue, and a method, are provided, which, for example, may cause commands to accumulate in queue(s). In one embodiment, a testing tool comprises an I/O interface for connecting with a target having the queue(s); and an I/O interface for connecting with initiator(s). Trigger logic intercepts a predetermined response at the target I/O interface from a target to an initiator with respect to a command of the initiator, and asserts a trigger signal. Outbound logic responds to the trigger signal, providing a reject and retry response at the target I/O interface for the target with respect to the response from the target, whereby a timeout timer for the command of the initiator is stopped for the queue(s). The outbound logic additionally conducts flow control with respect to the target at the target I/O interface.

Abstract: A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

Abstract: An electronic control unit has two microcomputers. Each microcomputer has a data buffer storing data first to be transmitted in every 8 ms, a second data buffer storing data to be transmitted in every 16 ms, and a third data buffer storing data to be transmitted in every 16 ms and being different from the first and second data buffers. The microcomputer transfers at the transmission timing of every 8 ms data in the first data buffer to the transmitting buffer, while it transfers alternately the data in the second data buffer and the data in the third data buffer to the transmitting buffer. The microcomputer also transfers an ID that indicates content of the present transmitting data to the transmitting buffer.

Abstract: Subject matter to regulate real-time data capture rates to match processor-bounded data consumption operations is described. In one aspect, a computing device receives data from a data source at a real time rate. The data is associated with an object of a particular data size. A data transfer buffer of less capacity than the particular data size is filled with the data at the real-time rate. In parallel with filling the data transfer buffer, the data source is transitioned at one or more particular times, to send repeat data. This allows an application to continuously process all data associated with the object independent of a data transfer buffer overflow condition caused by removal of the data from the data transfer buffer at a processor-bounded rate less than the real-time rate.

Abstract: A method and system for a PCI Express device is provided. The elastic buffer includes, a buffer control module that determines a difference between a write and read pointer value and compares the difference to a threshold value for inserting or deleting a standard symbol, wherein the threshold value is adjusted dynamically based on a slow or fast clock speed. The standard symbol is a PCI Express SKIP symbol. The method includes, determining if a clock speed is slow, wherein a monitoring register value indicates if a clock speed is slow; selecting a threshold value based on the monitoring register value; and inserting or deleting a standard symbol based on a comparison of a difference between a write and read pointer and the threshold value. The PCI Express device may be a host bus adapter operating in a storage area network or any other network.

Abstract: A SCSI-to-IP cache storage system interconnects a host computing device or a storage unit to a switched packet network. The cache storage system includes a SCSI interface (40) that facilitates system communications with a host computing device or the storage unit, and an Ethernet interface (42) that allows the system to receive data from and send data to the Internet. The cache storage system further comprises a processing unit (44) that includes a processor (46), a memory (48) and a log disk (52) configured as a sequential access device. The log disk (52) caches data along with the memory (48) resident in the processing unit (44), wherein the log disk (52) and the memory (48) are configured as a two-level hierarchical cache.

Abstract: In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of flow control and extended burst transfers are described.

Abstract: A data transfer device is disclosed for writing data to and reading data from a disk drive system through a plurality of ports of the data transfer device. The data transfer device includes a first buffer for serially receiving, from a host system, control portions of data read requests and data write transfers; a second buffer for serially receiving, from the host system, data portions of data write transfers received by the first buffer; and N temporary storage devices, wherein N is a positive integer, coupled to the first buffer and the second buffer, the N temporary storage devices for parallelly receiving and temporarily storing consecutive control portions of the data read transfers and data write transfers from the first buffer. Up to N of the data read transfers and data write transfers are transferred to the disk drive system through the plurality of ports simultaneously.

Abstract: In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the occupancy level of data in the receiving buffer and the vacancy level of data in the transmitting buffer are determined. Access to the system bus is granted based on the determination result. Buffers in the transmitting and receiving paths are treated as a single virtual transmitting buffer and a single virtual receiving buffer, respectively. Bus priority is determined by the data occupancy level in each virtual buffer and any change in the occupancy level. Therefore, it is possible to prevent or reduce underflow of the transmitting buffer and overflow of the receiving buffer, thereby impartially arbitrating which of the buffers can access the memory.

Abstract: An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Abstract: Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue and dequeue nodes that it may choose. The prior art merely provided access to the values stored in the node. In order to avoid anomalies, the queue is never allowed to become empty by requiring the presence of at least a dummy node in the queue. The ABA problem is solved by requiring that the next pointer of the tail node in each queue point to a “magic number” unique to the particular queue, such as the pointer to the queue head or the address of the queue head, for example. This obviates any need to maintain a separate count for each node.

Abstract: A method and apparatus for enabling repeated switching of a cross-connect and a timing source in a network element through the use of a phase adjuster. In one embodiment, a traffic card includes an aligner to adjust the occupancy of the data in two ingress FIFOs to synchronize their occupancy. In addition, the traffic card includes a clock control logic, including a phase adjuster, to adjust the phase of clock signals driving the two ingress FIFOs to avoid an underflow or overflow.

Abstract: A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

Abstract: A method of transmitting data through an I2C router from a source port to a destination port, the method comprising: receiving data in a first I2C source port buffer of the I2C router; capturing the I2C destination port before the first I2C source port buffer has overflowed; and transmitting the data from the first I2C source port buffer to the I2C destination port while restricting transmission from the second I2C source port buffer to the I2C destination port.

Abstract: A method and an apparatus for power management in a computer system have been disclosed. One embodiment of the method includes monitoring transactions over an interconnect coupling a chipset device and a peripheral device in the system, the transactions being transmitted between the peripheral device and the chipset device according to a flow control protocol to allow the chipset device to keep track of the transactions, and causing a processor in the system to exit from a power state if a plurality of coherent transactions pending in a buffer of the chipset device exceeds a first threshold. Other embodiments are described and claimed.

Abstract: A media player and a method for operating a media player are disclosed. A media program is able to substantially immediately begin playing after a media play selection has been made. Through intelligent operation, the media program is able to start playing even before the media program has been substantially or completely loaded from disk storage into semiconductor memory (i.e., cache memory). Additionally, the media program can be loaded into semiconductor memory through use of a background process without disturbing the playing of the media program. Further, if desired, the disk storage is able to be aggressively “powered off” when not being accessed, thereby enhancing battery life when being battery-powered.

Abstract: A polling-based communication apparatus and system. The apparatus of the invention, connected to a host computer through a peripheral bus, comprises an arbiter and multiple addressable entities. Each addressable entity corresponds to one of queues maintained in the host computer. The arbiter can determine which queue is to be served next in accordance with a quality of serve policy. The host computer polls each addressable entity by issuing a query packet. Depending on the queue chosen to be served next, the arbiter grants the corresponding addressable entity access to the peripheral bus, causing this granted addressable entity to respond to the host computer's polling with an acknowledgement packet. Thus the host computer initiates transactions to transfer data packets from the chosen queue through the peripheral bus to the corresponding addressable entity.

Abstract: A method and apparatus are described for flow control for digital signal processing to support data stream operations. According to an embodiment of the invention, a method comprises setting a buffer number to an initial value; receiving a first data packet for processing during a first part of a first time frame, the data packet having a first data size; increasing the buffer number by an amount of data that can be passed to a coder; comparing the buffer number to a minimum amount of data for the coder; and setting a second data size to be received based on the comparison between the buffer number and the minimum amount of data for the coder.

Abstract: Direct memory access data transfers may be initiated between buffers on one processor system to corresponding buffers in another processor system. The buffers in each system may be provided as a linked list such that transfers successively occur between the buffers. Each buffer may include a descriptor that indicates whether or not the buffer is full or empty. As a result, the buffer may be accessed by controllers in either processor system.

Abstract: A method and apparatus for ensuring fair and efficient use of a shared memory buffer. A preferred embodiment comprises a shared memory buffer in a multi-processor computer system. Memory requests from a local processor are delivered to a local memory controller by a cache control unit and memory requests from other processors are delivered to the memory controller by an interprocessor router. The memory controller allocates the memory requests in a shared buffer using a credit-based allocation scheme. The cache control unit and the interprocessor router are each assigned a number of credits. Each must pay a credit to the memory controller when a request is allocated to the shared buffer. If the number of filled spaces in the shared buffer is below a threshold, the buffer immediately returns the credits to the source from which the credit and memory request arrived.

Abstract: A data transmission system where an image providing device and a printer are directly connected by a 1394 serial bus, a command is sent from the image providing device to the printer, then a response to the command is returned from the printer to the image providing device. Image data is sent from the image providing device to the printer based on information included in the response. The printer converts the image data outputted from the image providing device into print data. Thus, printing can be performed without a host computer by directly connecting the image providing device and the printer by the 1394 serial bus or the like.

Abstract: A recording/reproducing apparatus for recording a received signal as digital data in a file format and for reproducing the digital data stored in the file format includes a memory controller which controls the recording made in a manner such that the digital data continuously received and stored in a buffer memory is stored in a storage unit at a writing speed which is higher than a speed at which the digital data is stored in the buffer memory. In a reproducing mode, the digital data is read from the storage unit into the buffer memory at a reading speed which is higher than a speed at which the digital data is outputted from the buffer memory to the outside.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer.

Abstract: A system and method for efficient transfer and buffering of captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to access the data event buffer to process the captured data events without the DMA transfer operation being stopped. In response to the region being filled, the DMA transfer engine may perform the DMA transfer operation to a different region of the data event buffer without the DMA transfer operation being stopped.