Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.

Abstract: An improved DMAC translation mechanism is presented. DMA commands are “unrolled” based upon the transfer size of the DMA command and the amount of data that a computer system transfers at one time. For the first DMA request, a DMA queue requests a memory management unit to perform an address translation. The DMA queue receives a real page number from the MMU and, on subsequent rollout requests, the DMA queue provides the real page number to a bus interface unit without accessing the MMU until the transfer crosses into the next page. Rollout logic decrements the DMA command's transfer size after each DMA request, determines whether a new page has been reached, determines if the DMA command is completed, and sends write back information to the DMA queue for subsequent DMA requests.

Abstract: Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write pointer (370) is reached in response to an indication that a data buffer controlled by the gray code counter is empty. Additionally, a read pointer (380) associated with the data buffer (310) may be gradually incremented or decremented until a reset value of the read pointer (380) is reached in response to an indication that the data buffer controlled by the gray code counter is full. The data buffer may be a first-in-first-out (FIFO) buffer such as FIFO buffer 310, which may be asynchronously clocked. The data buffer may be adapted to buffer any one or a combination of video, voice and data.

Abstract: An audio system communicates with an aggregate device that includes multiple audio devices. When providing audio data for playback, the system compensates for presentation latency differences between the various audio devices. In addition, the system adjusts for device clock drift by selecting a master device and resampling the audio data provided to the other devices based on the difference between the device clock of the master device and the device clocks of the other devices.

Abstract: A storage management device can receive a write operation that includes a data payload, store a first instance of the data payload at a first storage buffer in the storage management device, and evaluate a first cost equation to identify a second storage buffer in the storage management device, different from the first storage buffer, at which to optimally store a second instance of the data payload.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: Techniques for distributing data packets over a network link bundle include storing an output data packet in a data flow queue based on a flow identification associated with the output data packet. The flow identification indicates a set of one or more data packets, including the output data packet, which are to be sent in the same sequence as received. State data is also received. The state data indicates a physical status of a first port of multiple active egress ports that are connected to a corresponding bundle of communication links with one particular network device. A particular data flow queue is determined based at least in part on the state data. A next data packet is directed from the particular data flow queue to a second port of the active egress ports. These techniques allow a more efficient use of a network link bundle.

Abstract: Between data accesses to a storage medium, requested by an initiator, a logical unit may need to perform autonomous operations. The logical unit receives information from the initiator to allow the logical unit to estimate whether the stream buffer of the initiator is reaching a critical level. Based on this estimate, the logical unit can determine whether to perform or continue autonomous operations such as error recovery; physical maintenance of a drive mechanism or storage medium; or relative positioning between the drive mechanism and storage medium. The estimate also allows a flexible, rather than a fixed, time-out.

Abstract: Embodiments of the invention provide improved timing compensation for a bidirectional serial link in order to relax accuracy requirements of clock sources used for the link. Fill levels of receiver buffers at either ends of the link are used to determine a particular type of start of PDU (SOP) character sequence to use when forming a PDU for transmission over the link. When a given type of SOP character sequence is present in a PDU received at one end of the link, a next PDU to be transmitted from the same end of the link is delayed by a predetermined amount of time to allow the receiver buffer at the other end of the link to decrease its fill level before receiving the next PDU.

Abstract: In one embodiment, a data element is passed between a first block and a second block of a block diagram during execution of the block diagram. The first block and the second block negotiate use of a particular input/output (I/O) type from a plurality of available I/O types. The particular I/O type is used with at least one I/O buffer employed in passing the data element between the first block and the second block. The first block may produce a signal representing the data element. The signal is received at the I/O buffer and the data element stored according to the particular I/O type. Subsequently, the data element may be read from the I/O buffer by the second block, which performs an operation, the result of which is used when the block diagram is executing.

Abstract: A distance calculating unit calculates a distance from a current position on a tape to the end of the tape. A command processing unit receives a write command. If the distance is small, a determining unit sets a usable capacity of a buffer to be equal to a maximum capacity of the buffer. If the distance is large, the determining unit sets the usable capacity of the buffer according to the distance. If a capacity for data indicated by the write command is less than or equal to a difference between the usable capacity and current usage of the buffer, a buffer managing unit stores the data in the buffer. When the command processing unit receives a write FM command, the buffer managing unit reads the data from the buffer, updates the current usage, and a channel input/output unit writes the data to the tape.

Abstract: A controller included in a flash memory system, which can be applied to a memory interface of a host computer is disclosed. A buffer is used for data exchange operation between the host computer and the controller, and data exchange operation between a flash memory and the controller. A host interface control block as a first control block controls data exchange operation between the buffer and the host computer. A flash sequencer block as a second control block controls data exchange operation between the buffer and the flash memory. The host interface control block controls input and output operation of the buffer, based on a memory control signal and a memory address signal supplied from the host computer. The flash sequencer block controls input and output operation of the buffer at a one-page size of the flash memory.

Abstract: A data processing method includes: sequentially receiving data transmitted by radio communication; sequentially accumulating the received data in a buffer memory in which data is not yet accumulated; starting reading the data from the buffer memory in an accumulating order when the amount of data accumulated in the buffer memory exceeds a first critical value; adding supplementary data to the data read from the buffer memory until the amount of data accumulated in the buffer memory reaches a second critical value larger than the first critical value after starting reading the data from the buffer memory; and reading the data from the buffer memory without adding the supplementary data when the amount of data accumulated in the buffer memory reaches the second critical value during the reading of the data from the buffer memory.

Abstract: A storage subsystem includes a variable-size write buffer that temporarily stores write data received from a host system. The storage subsystem is capable of adjusting the size of the write buffer so as to vary both the performance (e.g., sustained write speed) of the storage subsystem and a risk of data loss. In one embodiment, the storage subsystem implements a command set that enables the host system to directly control the size of the write buffer. The storage subsystem may additionally or alternatively be capable of adjusting the size of the write buffer based on monitored operating conditions, such as the temperature, the stability/consistency of a power signal received from the host system, and/or the elapsed time since the storage subsystem was last powered up.

Abstract: Data objects are sent using a data carousel and forward error correction. This involves segregating a file into groups, wherein each group represents k data blocks. From the k data blocks of each group, n erasure-encoded blocks are calculated, where n>k. The n erasure-encoded blocks are sent in a round-robin fashion using IP multicast technology: the first erasure-encoded block for each group, then the second block of each group, and so on. At a receiver, the blocks are stored on disk as they are received. However, they are segregated by group as they are stored. When reception is complete, each group is read into RAM, decoded, and written back to disk. In another embodiment, the receiver segregates allocated disk space into areas corresponding to sets of groups. Received blocks are then segregated only by set as they are written to disk. One or more RAM buffers can be used in this embodiment. When reception is complete, each set is read into RAM, decoded, and then written back to disk.

Abstract: A system for monitoring EF-on-EF jitter in a network node having an EP output queue into which EF packets are entered comprises a first counter that counts the packets entering the queue and also a second counter that counts the packets entering the queue when the queue depth is greater than an operator-determined maximum depth, whereby the operator can compare the two counts to determine the proportion of packets that might be subject to jitter corresponding to the maximum depth. Preferably, the system also includes a third counter that counts the number of packets entering the queue when the queue depth exceeds an alarm depth greater than the maximum depth.

Abstract: A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.

Abstract: In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been stored earliest in response to a read request signal. A remaining data amount detection portion detects a remaining data amount of the stored data which remain in the first-in first-out storage. A variable frequency oscillating portion generates an enable signal at a time rate according to frequency control information so as to enable generation of the write request signal or read request signal. A frequency control portion corrects the frequency control information so as to return the remaining data amount to an appropriate value when the remaining data amount detected by the remaining data amount detection portion varies away from the appropriate value toward an upper limit value or varies away from the appropriate value toward a lower limit value.

Abstract: A method and system for providing delay bound and prioritized packet dropping are disclosed. The system limits the size of a queue configured to deliver packets in FIFO order by a threshold based on a specified delay bound. Received packets are queued if the threshold is not exceeded. If the threshold is exceeded, a packet having a precedence level less than that of the precedence level of the received packet is dropped. If all packets in the queue have a precedence level greater than that of the packet received, then the received packet is dropped if the threshold is exceeded.

Abstract: A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

Abstract: A USB host system includes a USB host controller including a transfer memory for USB data transfer. In the transfer memory, a plurality of transfer descriptor regions are allocated. Transfer descriptor setting means sets, for the USB host controller, a transfer descriptor for executing USB transfer. The transfer descriptor setting means can set, for one end point of a USB device, a plurality of transfer descriptors using the plurality of transfer descriptor regions, respectively.

Abstract: A disk control device stores write requests from a cache memory or reads commands from a host in a queue for a disk drive in chronological order. When the number of write requests stored in the queue for the disk drive is greater than a predetermined value, the storage location of write requests is changed to a queue for an extra disk drive, and the write requests are stored in the queue for the extra disk drive. When the number of write requests stored in the queue for the disk drive becomes smaller than a predetermined threshold, the write requests stored in the extra disk drive are written back to the disk drive.

Abstract: A stream data buffer device suitable for a client program comprises a buffer having N numbered sub-buffers, a buffer agent having a sub-buffer table recording a state of a corresponding sub-buffer, wherein the state comprising a first state and a second state, and a FIFO queue to record numbers of the sub-buffers having the fist state. When client program receives and stores stream data to stream data buffer, client program requests for a first sub-buffer having second state to store, and after storage, buffer agent changes the state of first sub-buffer to first state and transmits the number of the first sub-buffer to the FIFO queue. When a number of a second sub-buffer having the first state is available, the client program pops the number of second sub-buffer out of FIFO queue and accesses the data thereof, and the buffer agent changes the state of second sub-buffer to second state.

Abstract: A buffer, a method, and a computer program product for DMA transfers are provided that are designed to save memory space within a local memory of a processor. The buffer is a return buffer with a portion reserved for DMA lists. A DMA controller accomplishes DMA transfers by: reading address elements from a DMA list located in the DMA list portion; reading the corresponding data from system memory; and copying the corresponding data to the return buffer portion. This buffer saves space because when the buffer begins to fill up the corresponding return data can overwrite the data in the DMA list. Accordingly, the DMA list overlays on top of the return buffer, such that the return data can destruct the DMA list and the extra storage space for the DMA list is saved.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A first node to cause flushing data units stored in a write buffer of a second node to a memory of the second node. While using a pin-based approach, the central processing unit (CPU) of the first node may activate a first pin coupled to a second pin of the second node that may cause a sequence of operations to flush the write buffer. While using a control-register based approach, the CPU or the memory controller hub (MCH) may configure the control register using an inter-node path such as the SMBus or a data transfer path that may cause a sequence of operations to flush the write buffer. While using an in-band flush mechanism, the CPU may send a message over the data transfer path after transferring the data units that may cause a sequence of operations to flush the write buffer.

Abstract: A variable latency elastic buffer comprises a plurality of memory locations in which to hold data. A write and read pointer may point to respective write and read addresses of the plurality of locations in which to write and read data. A controller may hold or increment the address of the read pointer upon determining that the amount of data within the buffer differs from a nominal fill level. In a particular embodiment, initialization circuitry may be operable to initialize the read and write addresses of the respective pointers responsive to an initialization request. The read and write addresses may differ from one another by an offset value equal to a value programmed for the nominal value.

Abstract: An oversampling system (oversampling apparatus), a decoding LSI chip, and an oversampling method capable of decreasing the memory capacity of an output buffer used to oversample and output decoded data for digital audio.

Abstract: In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.

Abstract: Methods and apparatus that allow recovery in the event that sequence counts used on receive and transmit sides of a communications link become out of sync are provided. In response to receiving a packet with an expected sequence count from a receiving device, a transmitting device may adjust pointers into a transmit buffer allowing the transmitting device to begin transmitting packets with the sequence count expected by the receiving device.

Abstract: A system for providing dynamic queue splitting to maximize throughput of queue entry processing while maintaining the order of queued operations on a per-destination basis. Multiple queues are dynamically created by splitting heavily loaded queues in two. As queues become dormant, they are re-combined. Queue splitting is initiated in response to a trigger condition, such as a queue exceeding a threshold length. When multiple queues are used, the queue in which to place a given operation is determined based on the destination for that operation. Each queue in the queue tree created by the disclosed system can store entries containing operations for multiple destinations, but the operations for a given destination are all always stored within the same queue. The queue into which an operation is to be stored may be determined as a function of the name of the operation destination.

Abstract: A multiprocessor system (100) for sharing memory has a memory (102), and two or more processors (104). The processors are programmed to establish (202) memory buffer pools between the processors, and for each memory buffer pool, establish (204) an array of buffer pointers that point to corresponding memory buffers. The processors are further programmed to, for each array of buffer pointers, establish (206) a consumption pointer for the processor owning the memory buffer pool, and a release pointer for another processor sharing said memory buffer pool, each pointer initially pointing to a predetermined location of the array, and adjust (208-236) the consumption and release pointers according to buffers consumed and released.

Abstract: Methods and apparatuses for flushing write-combined data from a buffer within a memory to an input/output (I/O) device.

Abstract: A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is delimited by only a tail pointer stored in a tail pointer list. Following dequeuing the string for processing, a pointer to the one command block of the string that was in the common queue is included in a string head pointer list. The tail pointer to the string is not changed in the tail pointer list following dequeuing of the string. This allows any new SCBs to be appended to the end of the string, while the string is being processed. This allows streaming of new SCBs to an I/O device that had previously been selected and is still connected to the host adapter.

Abstract: An integrated circuit comprises a first data interface configured to be coupled to a first memory device, a second data interface configured to be coupled to a second memory device, a first control interface configured to be coupled to the first memory device, and a second control interface configured to be coupled to the second memory device. The control interfaces are arranged between the first data interface and the second data interface or the data interfaces are arranged between the first control interface and the second control interface.

Abstract: Data objects are sent using a data carousel and forward error correction. This involves segregating a file into groups, wherein each group represents k data blocks. From the k data blocks of each group, n erasure-encoded blocks are calculated, where n>k. The n erasure-encoded blocks are sent in a round-robin fashion using IP multicast technology: the first erasure-encoded block for each group, then the second block of each group, and so on. At a receiver, the blocks are stored on disk as they are received. However, they are segregated by group as they are stored. When reception is complete, each group is read into RAM, decoded, and written back to disk. In another embodiment, the receiver segregates allocated disk space into areas corresponding to sets of groups. Received blocks are then segregated only by set as they are written to disk. One or more RAM buffers can be used in this embodiment. When reception is complete, each set is read into RAM, decoded, and then written back to disk.

Abstract: A method for executing input/output (I/O) operations based on priority involves receiving a first I/O request for a unit of data, receiving a second I/O request for the same unit of data, determining a priority of the first I/O request and a priority of the second I/O request, and executing the first I/O request based on priority, where the first I/O request is executed based on the higher of the priority of the first I/O request and the priority of the second I/O request.

Abstract: A data transfer control device including: a link controller which analyzes a packet received through a serial bus; a packet detection circuit which detects completion or start of packet reception based on analysis result of the received packet; first and second packet buffers into which the packet received through the serial bus is written; and a switch circuit which switches a write destination of the received packet. When a Kth packet has been written into one of the first and second packet buffers and completion of reception of the Kth packet or start of reception of a (K+1)th packet subsequent to the Kth packet has been detected, the switch circuit switching the write destination of the (K+1)th packet to the other of the first and second packet buffers.

Abstract: The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.

Abstract: Method and system for a dynamic FIFO flow control circuit. The dynamic FIFO flow control circuit detects one or more obsolete entries in a FIFO memory, retrieves the address of the next valid read pointer, and reads from the retrieved address during the next read operation.

Abstract: A method for managing under-runs and a device having under-run management capabilities. The method includes retrieving packets from multiple buffers, monitoring a state of a multiple buffers, determining whether an under-run associated with a transmission attempt of a certain information frame from a certain buffer occurs; if an under-run occurs, requesting a certain information frame transmitter to transmit predefined packets while ignoring packets that are retrieved from the certain buffer, until a last packet of the information frame is retrieved from the certain buffer; and notifying a processor that an under-run occurred after at least one predefined packet was transmitted; wherein each buffer out of the multiple buffers is adapted to store a fraction of a maximal sized information frame.

Abstract: A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system removes packets including a packet header and packet data from a packet buffer. The packet buffer is arranged into a plurality of packet buffer memory slots, each slot comprising a descriptor status array location including an availability bit set to “used” or “free”, and a packet buffer memory location comprising a descriptor memory slot and a data segment memory slot. The descriptor memory slot includes header information for each packet, and the data segment memory slot includes packet data. The memory controller operates on one or more queues of data, and data is placed into a particular queue in packet memory determined by priority information derived from incoming packet header or packet data.

Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers.

Abstract: A method and apparatus in a data controller in a storage drive for retrieving, evaluating, and processing a context that describes a direct memory access (DMA) request. The data controller includes a buffer for storing data transferred in response to execution of a DMA transfer request, a host address pointer pointing to a current location in the buffer, and a retrieval channel device. The retrieval channel device is configured to: fetch a context that describes a DMA transfer requested by a host computer, determine whether a current capacity of the buffer for transferring data exceeds a threshold, generate an instruction to transfer a second amount of data to complete at least a portion of the requested DMA transfer if the current capacity does exceed the threshold, assert the instruction generated by the retrieval channel device, and adjust the host address pointer by the second amount of data.

Abstract: An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Abstract: A queuing system wherein at least one input/output (I/O) interface having an outbound queue. A plurality of processing units is coupled to the at least one I/O interface. Each one of the processing units is coupled to a corresponding processing unit memory. Each one of the processing unit memories has an inbound queue for such coupled processing unit. The at least one I/O interface outbound queue stores outbound information being returned to the I/O interface after being processed by one of the processing units. The I/O interface creates queue indices for storage in the inbound queues of the processor unit memories. The I/O interface includes a translation table, such table storing at a location a producer index for the plurality of processing units and a consumer index for such plurality of processing units.

Abstract: Various aspects of the low cost line buffer system allow a reduction in circuitry versus conventional approaches to line buffer design. A plurality of line buffers such that the output of one line buffer in the plurality of line buffers may be coupled to an input of a succeeding line buffer in the plurality of line buffers. A first line buffer in the plurality of line buffers may be coupled to an input write data signal, while the width of a subsequent plurality of line buffers may be less than or equal to the width of the previous line buffers in the plurality of line buffers.

Abstract: Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.