Abstract: An electronic control unit has two microcomputers. Each microcomputer has a data buffer storing data first to be transmitted in every 8 ms, a second data buffer storing data to be transmitted in every 16 ms, and a third data buffer storing data to be transmitted in every 16 ms and being different from the first and second data buffers. The microcomputer transfers at the transmission timing of every 8 ms data in the first data buffer to the transmitting buffer, while it transfers alternately the data in the second data buffer and the data in the third data buffer to the transmitting buffer. The microcomputer also transfers an ID that indicates content of the present transmitting data to the transmitting buffer.

Abstract: An enhanced structure of extensible time-sharing bus, which essentially uses an address and data bus in time-sharing to send addresses and data between a microprocessor and a memory through a microprocessor interface and a memory interface, and a logic combination of two control lines to determine address transfer, data read or data write on the address and data bus, thereby reducing interface pins and obtaining flexible and multiplicative memory.

Abstract: A system, method, and product are disclosed in a data processing system for serializing hardware reset requests in a software communication request queue in a processor card. The processor card processes software communication requests utilizing the queue in a serial order. A hardware reset request is received by the processor card and put in the queue. The hardware reset request is processed from the queue in the serial order with all requests from the queue that are currently being serviced have completed being serviced.

Abstract: A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.

Abstract: On the basis of a period of a timing signal, a signal propagation delay in a device unit, signal propagation delay in the timing signal bus and the data bus, and a setup time of another device unit or a device connected to the data bus, a timing at which noise caused by active connection of the first device to the data bus is propagated to the other device unit or the device is computed in a step of noise propagation computing, and on the basis of the timing computed in the step of noise propagation computing, a connection timing at which the first device unit is connected to the data bus. With thes two steps, a noise caused by active connection of a device unit does not affect other device units and devices connected to the same data bus.

Abstract: An ATA/IDE host controller 100 generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers 121. An internal timing control module 110 provides either the default timing parameters or the override timing parameters to the IDE host interface 102, according to the programmable override control 301.

Abstract: A design method for a bus system comprising a noise propagation computation step and a connection timing computation step. Based on the cycle of a timing signal, a signal propagation delay in a device unit, signal propagation delays in a timing-signal bus and a data bus, and a setup time in the device unit or device connected on the data bus, the noise propagation computation step computes timing at which, when the device unit is connected on the data bus being active, noise propagates to other device units other than the connected device unit or to the device connected on the data bus. Based on the timing computed in the noise propagation computation step, the connection timing computation step computes connection timing at which the device unit is connected on the data bus.

Abstract: A memory system system includes a single in-line memory module (SIMM) which contains a memory device and a signal transmission line connected between the memory device and a connection terminal, and a dual in-line memory module (DIMM) which contains two memory devices and a signal transmission line connected between the two memory devices and a connection terminal. A length of the signal transmission line of the SIMM is longer than a length of the signal transmission line of the DIMM. The load of the memory device of the SIMM is less than the load of memory devices of the DIMM, and the longer length of the signal transmission line of the SIMM increases a signal delay time of the SIMM to compensate for the different loads of the SIMM and DIMM memory devices. The longer length of the signal transmission line of the SIMM may further compensate for a signal transmission line connected between the first and second sockets which receive the SIMM and DIMM, respectively.

Abstract: Techniques for utilizing a time-to-live timeout on a logical connection to a resource (e.g., a database) from a cache are provided. When a logical connection to the resource is obtained, a timeout is set specifying the amount of time the logical connection can be utilized. If the timeout expires, the logical connection is closed and the underlying physical connection can be returned to the cache.

Abstract: The present invention relates to a data processing circuitry and method of processing an input data pattern and out-putting an output data pattern after a processing delay which depends on a processing activity of the data processing circuitry, wherein the processing delay is estimated based on the input pattern and the processing is controlled in response to the estimated processing delay. The processing control may be a power control based on an activity monitoring or a clock control in a pipeline structure. Thereby, an efficient solution is provided to derive the current activity of the processing circuitry in order to dynamically adapt its operating conditions to its demands.

Abstract: A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.

Abstract: A data output device is disclosed having a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal, a second comparator for comparing second output data with the first output data on a bit-by-bit basis and outputting a second pre-flag signal, first and second logic units for performing logic operations with respect to pre-flag signals and data inversion flag signals, a first output unit for inverting or non-inverting and outputting a plurality of bits contained in the first output data in response to the first data inversion flag signal, a second output unit for inverting or non-inverting and outputting a plurality of bits contained in the second output data in response to the second data inversion flag signal, and an output data initializer for, when a no-operation period is generated in a series of data output operations, initializing the arbitrary output data and supplying the resulting data to the first comparator.

Abstract: A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data using a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.

Abstract: For use in a data storage system, a method of dynamically controlling accesses to and from the storage device array.

Abstract: A method and an apparatus in a computer system for connecting buses with different clock frequencies are provided. The method comprises receiving a request transmitted from a master to a slave. If the clock frequency of the master is lower than that of the slave such that the slave sees more requests than the master does, redundant cycles of the request signal are masked lest the slave repeatedly receive the request. The request is then transferred to the slave. If the clock frequency of the master is higher than that of the slave such that the slave cannot receive the request in time, then the request signal is lengthened so that the request signal is synchronized with the clock cycles of the slave. The output data responded from the slave is then transferred to the master.

Abstract: A process and software for achieving minimal latency in digital audio recording, which includes calculating a repeatable play cursor lead and a play cursor position and writing audio data at the play cursor position plus the play cursor lead.

Abstract: An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code pattern in the serial data stream and generating a code detection output in response thereto. The serialiser/deserialiser can also comprise a transition detector for detecting transitions in the serial data stream and reconstructing a serial data clock therefrom, and for generating a plurality of parallel data clocks from the serial data clock, each parallel data clock having a different phase. The data buffer can be responsive to the code detection output to adjust a parallel data group start position within the serial data stream and to cause a selection of one of the reduced frequency clocks having a phase corresponding to the adjusted parallel data group start position.

Abstract: The present invention describes a method and system for adjusting the rate of data transfer between a high-speed multi-channel tape drive and a slower-capability network interface. The present invention allows for selectively enabling/disabling active channels to adjust the data throughput to match the data transfer capabilities of the network interface. Such an adjustment optimizes the rate of data transfer between the system and the tape drive by reducing the amount of stop and start operations normally present in an environment where the network interface cannot support the high-speed data transfer rates of a tape drive. Such an enablement/disablement adjustment system allows for a greater range of varying data rates within the transfer.

Abstract: A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth of information from an input RAM that implements the input queue. The method further involves recognizing that an output queue has room to receive information and that an intermediate queue that provides information to the output queue does not have information waiting to be forwarded to the output queue. The method also involves generating a second request to read information from the input RAM so that at least a portion of the room can be filled. The method also involves granting one of the first and second requests.

Abstract: The present invention relates to a system and methodology to facilitate I/O access to a computer storage medium in a predictable and efficient manner. A scheduling system is provided that mitigates the problem of providing differing levels of performance guarantees for disk I/O in view of varying levels of data access requirements. In one aspect, the scheduling system includes an algorithm or component that provides high performance I/O updates while maintaining high throughput to the disk in a bounded or determined manner. This is achieved by dynamically balancing considerations of I/O access time and latency with considerations of data scheduling requirements. Also, the system provides latency boundaries for multimedia applications as well as managing accesses for other applications.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: A method and apparatus for avoiding bi-directional signal fighting of a serial interface is disclosed. The serial peripheral interface includes a clock signal line and a data line. In this method, during normal operation, a first clock signal is received and transformed to output a second clock signal in the clock signal line, wherein the second clock signal has a first duty period. When the output of the data in the data line switches to input, the second clock signal switches to have the second duty period, wherein the second duty period is larger than the first duty period.

Abstract: A hard disk controller having a latency-independent interface comprises a data gate circuit that transmits a data gate signal. A data circuit transmits or receives data under control of the data gate signal. A media gate circuit transmits a media gate signal. A mode selection circuit transmits mode selection information under control of the media gate signal, wherein said data gate signal controls the transfer of data between the hard disk controller and a read/write channel in accordance with the media gate signal.

Abstract: Disclosed is an interface (10, 40) between a master device (30) and a slave device (20). The interface includes a bit serial bidirectional signal line (10A) for conveying commands and associated data from the master device to the slave device, and for conveying a reset signal, an interrupt signal, and a learning sequence signal for specifying a duration of a bit time for data transferred from the slave device to the master device. The bit serial bidirectional signal line further indicates an accessory device connected/disconnected state to the master device.

Abstract: A hardware command queue for mass storage systems having a memory device. A plurality of entries are defined in the memory device, at least some of which are active entries. At least some of the active entries correspond to pending access commands and at least one entry is a head entry corresponding to an in-flight access command.

Abstract: Circuit board having a plurality of bus lines (6), which run on the circuit board (1) essentially parallel to a preferred direction of the circuit board (1), and having at least one integrated circuit (3) for the high-speed data processing of data, which integrated circuit is arranged on the circuit board (1), is integrated in a housing (4) having a plurality of housing sides (5) and has a plurality of parallel interfaces for connection to the bus lines (6), in which case the housing sides (5) of the integrated circuits (3) are oriented at an inclination with respect to the preferred direction of the circuit board (2).

Abstract: A memory management system adapted to process linked list data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of linked list files by the memories. The head and tail buffers and at any intermediate buffers of a linked list are written into the high speed memories. The intermediate buffers are immediately transferred from the high speed memories to said bulk memory while leaving the head buffer and the tail buffer of the linked list in the high speed memories. In read operations, the head and tail buffers are read from the high speed memories. The intermediate buffers are transferred from the bulk memory to said the high speed memory and then read from the high speed memories.

Abstract: A memory management system adapted to process large data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of data files by the memories. Large data files have a first part and an excess portion. Both parts of each file are written into the high speed memories. The excess portion of each file is immediately transferred from the high speed memories to the bulk memory while leaving the first part in the high speed memories. In read operations, the first part is read from the high speed memories. The excess portion is transferred from the bulk memory to the high speed memory in a burst mode and then read from the high speed memories.

Abstract: Cancellation of transmission of print data from a host computer to a printer is implemented under a USB Printer Class protocol without increasing the burden upon a printer on the receiving side. Specifically, when the host computer issues a transmit-abort request to the printer during the transmission of print data, the host computer notifies the printer of cancellation of data transmission via a channel different from that used for the data transmission. Upon being so notified, the printer suspends processing and discards the data that has been received. After suspending the processing, discarding the received data completing the preparation of receiving next data stream the printer notifies the host computer of the completion of abort procedure. Host computer will not send next data stream until receiving the completion of abort procedure from printer.

Abstract: A method for transferring variable isochronous data and an apparatus therefor are provided. The method for transferring variable isochronous data includes the steps of (a) determining isochronous transfer to be terminated when the bus is in an idle state for a time interval which is larger than an isochronous gap period, (b) detecting a residual gap having a time interval which is larger than the time interval of an isochronous gap and smaller than the time interval of a subaction gap, (c) checking whether bandwidth for the transfer of isochronous data remains when the residual gap is detected in the step (b), and (d) transferring the isochronous data when it is determined that the bandwidth remains in the step (c).

Abstract: A method for selectively inserting cache entries into a cache memory is proposed in which incoming data packets are directed to output links according to address information. The method comprises the following steps: a) an evaluation step for evaluating for each incoming data packet classification information which is relevant to the type of traffic flow or to the traffic priority to which the data packet is associated; b) a selection step for selecting based on the result of the evaluation step whether for the data packet the cache entry is to be inserted into the cache memory; c) an entry step for inserting as the cache entry into the cache memory, in the case the result of the selection step is that the cache entry is to be inserted, for the data packet the address information and associated output link information.

Abstract: A modem architecture and a method of reducing on-chip memory requirements in a downloadable modem architecture are provided. The preferred architecture consists of a Digital Signal Processor (DSP) (6) with on-chip Random Access Memory (RAM) (12). A procedure which exploits inactivity intervals in a modem modulation function is provided. The procedure dynamically downloads the requisite code segments for each phase of the function from a cheaper, slower external memory (14) into the DSP on-chip RAM during inactivity intervals, thereby reducing the DSP on-chip RAM requirements.

Abstract: In one embodiment, a method is provided. The method of this embodiment may include receiving an indication that a first device has been granted access to a bus. In response, at least in part, to the indication, a signal may be provided that may result in the coupling of a signal line of a second device to the bus. After the provision of the signal, the first device may configure the second device. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: A method and apparatus for re-synchronizing a remote mirroring pair including first and second storage systems which are connected to each other via a path, the first storage system being connected to a host. A primary volume is provided to the first storage system and a remote secondary volume is provided to the second storage system. The remote secondary volume is a copied volume of the primary volume which is in synchronous mode with the remote secondary volume. A local secondary volume is provided in the first storage system and has stored therein journal logs of write I/O's from the host and old data including write data of previous write I/O's. Recovery of data on the primary volume based on the local secondary volume is conducted when necessary by applying the journal logs to the old data without suspending the synchronous mode between the primary and remote secondary volumes.

Abstract: A system and method for low impact backup. In one embodiment, a method may comprise monitoring utilization of a system resource and a data management process selectively performing I/O operations dependent upon the monitored utilization of the system resource. The data management process may include functionality to backup desired data from a storage medium to a backup medium. In one particular implementation, the I/O operations may be allowed to be performed in response to the utilization of the system resource falling below a predetermined threshold. In another embodiment a method may comprise performing a plurality of I/O operations to complete a data management process executed by an application. The application separates said plurality of I/O operations with intermittent delays to achieve time-slicing of the data management process with respect to one or more other applications.

Abstract: A parallel processing system includes a plurality of stages operatively coupled in parallel and operating simultaneously. Each stage including a process unit generating a predetermined function and a buffer coupled via a slow output and a slow input ports to the process unit. The buffer also includes a fast input port and a fast output port. A controller drives the buffer to operate in a Slow Read Phase when data is written from the buffer into the process unit, a Slow Write Phase when data is written into the buffer from the process unit, a Fast Write Phase when data is written at a fast rate into the buffer and a Fast Read Phase when data is read from the buffer.

Abstract: A source-synchronous data receiver includes a storage device for sequentially storing data received from a data source, a data output device for sequentially outputting the data that is stored in the storage device, and a control for controlling the data output device, so that the data output device makes available particular data previously stored by the data storage device a programmable predetermined number of clock states after data is called for, e.g., a read command to the data source is initiated.

Abstract: The present invention relates to a storage unit comprising: a channel control portion for receiving a data input/output request; a cache memory for storing data; a disk control portion for performing input/output processing on data in accordance with the data input/output request; and a plurality of disk drives for storing data, wherein at least two of the disk drives input data to and output it from the disk control portion at different communication speeds. Further, the storage unit has a plurality of communication paths provided to connect at least one of the disk drives in such a manner as to constitute a loop defined by the FC-AL fiber channel standards, so that the communication speeds can be set differently for these different communication paths.

Abstract: A method and design tool are provided for modifying a design of a bus interconnect block for a data processing apparatus in order to meet a requirement for a chosen characteristic of the bus interconnect block. The bus interconnect block provides a plurality of connections via which one or more master devices may access one or more slave devices, each connection comprising one or more paths, and each path having one or more path portions separated by storage elements. The method comprises the steps of: (a) selecting one or more candidate paths from said paths; (b) for each candidate path, applying predetermined criteria to determine whether modification of the number of storage elements in said path will assist in meeting the requirement for said chosen characteristic; and (c) modifying the number of storage elements in each candidate path for which it is determined at said step (b) that modification will assist in meeting the requirement for said chosen characteristic.

Abstract: A clock signal arbitration method includes arbitrating between first and second request signals generated in respective first and second clock domains that are asynchronously timed relative to each other, to obtain first arbitration results. These first arbitration results identify a relative queue priority between the first and second request signals. Additional steps are performed to transfer the first arbitration results into a third clock domain that is asynchronously timed relative to the first and second clock domains. The transfer operation may include arbitrating the first arbitration results in a third clock domain to obtain second arbitration results that confirm or correct the first arbitration results.

Abstract: A recording and/or reproducing apparatus for causing data recorded on a first recording medium to be stored in a second recording medium. This recording and/or reproducing apparatus includes a reproducing unit for reading out data from the first recording medium at a transmission rate faster than a standard readout rate of the first recording medium, a storage unit for storing the data read out from the first reproducing unit, a recording unit for storing the data read out from this storage unit on the second recording medium and a controlling unit for controlling the operation of the reproducing unit, storage unit and the recording unit. The controlling unit causes data to be read out from the storage unit at a transmission rate equal to the standard recording rate of the second recording medium and routed to the recording unit to record the supplied data in the second recording medium.

Abstract: A low-level function which enforces logical partitioning establishes a set of virtual indicator lights for certain physical components, the virtual indicator lights being only data in memory, a separate set of virtual indicator lights corresponding to each respective partition. Processes running in a partition can switch and sense the virtual indicator lights corresponding to the partition, but have no direct capability to either switch or to sense the virtual lights of any other partition. The low-level enforcement function alone can switch the state of the physical indicator light, which is generally the logical OR of the virtual indicator lights of the different partitions.

Abstract: A system and method for distributing a portion of the processing of a received packet among a plurality of service threads. When an ISR or similar process retrieves a packet from a communication interface via a receive descriptor ring, it places the packet on one of a plurality of service queues. Each queue has an associated service thread or process that initiates upper layer protocol processing for queued packets. The ISR may select a particular service queue based on the packet's communication flow or connection. Alternatively, the ISR may use a processor identifier provided by the communication interface to select a queue (e.g., in a multi-processor computer system). Or, other information provided by the interface may be used.

Abstract: A robust packet arrival time detector using a power estimate to validate a packet arrival time measurement. A packet arrival time measurement is considered valid when the value of the power estimate signal indicates that a packet is being received. A power estimator comprises a bandpass filter, a Hilbert transform, two squaring devices, an adder, and a lowpass filter.

Abstract: Method for measuring performance of a storage device including rotatable media, for storing data to and/or retrieving data from said media via one or more data buffers. The measurement method includes the steps of: specifying one or more access patterns for transferring data to/from the media; and for each access pattern, specifying one or more different required data transfer rates, measuring the actual data transfer time of the storage device for transferring the data according to that access pattern, and determining performance of the storage device in relation to each required data transfer rate based on the actual data transfer time for the data.

Abstract: A system and methods are shown for generating a transport stream. An application reads a transport stream file stored in memory. The application provides access to the transport stream file to a graphics card using a multimedia peripheral port (MPP). The MPP is used to provide data from the transport stream file to a transport stream demultiplexer. The application determines a desired transmission rate from the data present between program clock references in the transport stream file. The application suspends transmissions to the transport stream demultiplexer to allow a transmission bit-rate to match the desired bit-rate. The application also suspends transmission when the receiving transport demultiplexer determines its buffers are nearly full.

Abstract: In one embodiment, a method may include, if an amount of data requested to be transferred by a data transfer request according to a first protocol exceeds a maximum data transfer amount permitted to be requested by a single data transfer request according to a second protocol, generating one data transfer request according to the second protocol and a data structure, and modifying, at least in part, another data structure. This data transfer request may request transfer of a portion of the data. The data structure may include one or more values identifying, at least in part, another portion of the data. The modifying may be based, at least in part, upon the one or more values. The other data structure may include, prior to being modified, one or more other values indicating, at least in part, one or more parameters of the one data transfer request.

Abstract: The present invention focuses on the aggregation of flows belonging to different classes of non-guaranteed-delay traffic into a single FIFO queue in a downstream stage of the multi-stage switch. These include the guaranteed flows requiring bandwidth reservation, the best-effort flows that require a fair share of the excess bandwidth, and the flows that require both types of guarantee. We disclose a credit-based backpressure scheme which selectively controls the traffic originating from the previous stage of the system while achieving the goal of meeting the requirements of the individual flows. The credit function is maintained for each controlled traffic component in the aggregate session, and its objective is to balance the actual arrival rate of the component with the service rate dynamically granted by the downstream scheduler. The number of flows that can be aggregated is related to the complexity of maintaining the credit functions for the different traffic components.

Abstract: An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.