Abstract: Managing data traffic among three or more bus agents configured in a topological ring includes numbering each bus agent sequentially and injecting messages that include a binary polarity value from the bus agents into the ring in a sequential order according to the numbering of the bus agents during cycles of bus agent activity. Messages from the ring are received into two or more receive buffers of a receiving bus agent, and the value of the binary polarity value is alternated after succeeding cycles of bus ring activity. The received messages are ordered for processing by the receiving bus agent based on the polarity value of the messages and a time at which each message was received.

Abstract: An access control device having a number-of-waits setting circuit determining a wait periodicity corresponding to an operating speed of peripheral devices connected to a second bus according to an address corresponding to an access request to the second bus sent from a first bus, responsive to the access request, and a count value generator generating a count value up to the wait periodicity set to the number-of-waits setting circuit. A control signal holding circuit holds a control signal for holding a state of the second bus at the setting of the wait periodicity by the number-of-waits setting circuit during a count period of the count value generator and maintains the access state of the status controller. A clock control circuit divides a clock for the first bus according to the wait periodicity set and outputs the result of division to the second bus.

Abstract: A threshold mechanism is provided so that a producer and a corresponding consumer, executing on the same resource (e.g., CPU) are able to switch context between them in a manner that reduces the total number of such context switches. The threshold mechanism is associated with a buffer into which the producer stores packets up to a given threshold before the consumer is allowed to remove packets. The buffer has an associated upper limit on the number of packets that can be stored in the buffer. A flush empties the buffer of any remaining packets when no more packets are to be produced. This reduction in the total number of context switches in general leads to better performance at the cost of more latency.

Abstract: A computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.

Abstract: A real-time control system for executing exactly a cyclic task, preventing a delay of the processing start time due to accumulation of a plurality of overhead times, thereby executing control enabling a more detailed response and control enabling a quick and reliable response to a plurality of instructions is provided. The real-time control system includes a driver unit for receiving an input signal and outputting an interruption signal corresponding to each task process, a polling unit for polling on the basis of the concerned interruption signal, and a task processor for performing a task process on the basis of the interruption signal, wherein the polling unit outputs a task processing signal on the basis of the polling when the task is finished and the task processor performs the task process on the basis of the task processing signal.

Abstract: The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data. When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.

Abstract: The present invention relates to a storage unit comprising: a channel control portion for receiving a data input/output request; a cache memory for storing data; a disk control portion for performing input/output processing on data in accordance with the data input/output request; and a plurality of disk drives for storing data, wherein at least two of the disk drives input data to and output it from the disk control portion at different communication speeds. Further, the storage unit has a plurality of communication paths provided to connect at least one of the disk drives in such a manner as to constitute a loop defined by the FC-AL fiber channel standards, so that the communication speeds can be set differently for these different communication paths.

Abstract: Methods and systems are disclosed for detecting a presence of a device that includes providing a clock driver having a pair of differential clock signal lines capable of connection to a device, providing a presence detection signal for transmission through the pair of differential clock signal lines, determining whether the presence detection signal is received through the pair of differential clock signal lines, and identifying the presence of the device if the presence detection signal is received through the pair of differential clock signal lines.

Abstract: A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to an input inversion flag and transmits the inverted input data group to a memory cell array. In an output mode, the data input/output circuit inverts a data group, output from the memory cell array, when the output data group satisfies a predetermined inversion condition, and transmits the inverted output data group to the outside of the data input/output circuit. In this case, an output inversion flag, indicating that the output data group is to be inverted, is generated. Further, the data input/output circuit stores the input inversion flag in the memory cell array in the input mode, and compares the input inversion flag, stored in the memory cell array, with the output inversion flag in the output mode.

Abstract: A highly-reliable system, a management apparatus and method that can enhance the reliability of a storage system is provided.

Abstract: Systems and methods for driving data over a data bus are disclosed. One embodiment of a system may comprise a bus clock signal that is a copy of a system clock signal that controls the timing associated with transferring data over the bus, a data clock signal that is designed to lead the system clock by a portion of a clock cycle to drive data over the bus ahead of the bus clock signal, an output latch device that drives data over the data bus in response to an edge of the data clock signal and a skew corrector that mitigates racing of data over the data bus in the event that the data clock lags the bus clock.

Abstract: The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by t

Abstract: A method for transferring variable isochronous data and an apparatus therefor are provided. The method for transferring variable isochronous data includes the steps of (a) determining isochronous transfer to be terminated when the bus is in an idle state for a time interval which is larger than an isochronous gap period, (b) detecting a residual gap having a time interval which is larger than the time interval of an isochronous gap and smaller than the time interval of a subaction gap, (c) checking whether bandwidth for the transfer of isochronous data remains when the residual gap is detected in the step (b), and (d) transferring the isochronous data when it is determined that the bandwidth remains in the step (c).

Abstract: Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

Abstract: There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

Abstract: Methods and systems are described for a system for transitioning a target device to a first operative state, such as a service operating system. The target device in the first operative state then receives a set of one or more instructions, and processes the received set of one or more instructions to perform a set of one or more operations with regard to an indirect target device. Further, after processing of the set of one or more instructions, the target device transitions from the first operative state to a second operative state.

Abstract: Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

Abstract: A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received data item and for serializing the data item which is to be sent, having a second data interface for writing the parallelized data item to a memory arrangement via a memory data bus and for receiving the data item read from the memory arrangement via the memory data bus; having a write buffer storage for buffer-storing the data item which is to be written, having a control unit in order, after reception of a data item which is to be written via the first data interface in line with a write command, to interrupt the data from being written from the write buffer storage via the second data interface upon a subsequent read command.

Abstract: Disclosed herein is a transfer apparatus including, a connection status detection block, a storage status detection block, a no-operation status detection block, and a transfer block.

Abstract: An information processing apparatus includes a communication unit that transmits/receives data to and from an external device; a detection unit that detects communication connection with the external device by the communication unit; an operation input unit that accepts an operation input; a command allocation unit that, when the detection unit detects communication connection with the external device, allocates a data transmission command with respect to a one-click operation to a symbol corresponding to a data storage place to be displayed on a display unit, which is accepted by the operation input unit; and a control unit that, when the operation input unit accepts the one-click operation to the symbol, in case the data transmission command is allocated with respect to the one-click operation, controls so that the communication unit transmits data stored in the data storage place corresponding to the symbol to the external device.

Abstract: When a first mode (with-SOF mode) has been set, data transfer is performed while SOF packets are transferred at frame periods, and when a second mode (non-SOF mode) has been set and also non-periodic (bulk) transfer is being performed, the periodic transfer of SOF packets is disabled and non-periodic data is transferred. If there is no non-periodic data to be transferred, a SOF packet is transferred in the frame period, even if the second mode has been set. During host operation with USB on-the-go (OTG), pipe regions are allocated to the packet buffer, and non-periodic data is transferred automatically to or from end points while the periodic transfer of SOF packets is disabled. When all of the automatic transfer instruction signals of the pipe regions are inactive, SOF packets are transferred periodically even if the second mode has been set.

Abstract: A method and apparatus improves a link rate to a plurality of storage devices accessible through a port multiplier. An SATA/STP Transport Layer Transmit Processor in a FIS-based switching Port Multiplier system may service a next task to be transmitted to a next device accessible through the port multiplier even if the current task to a current device is stalled.

Abstract: One embodiment of a long-distance synchronous bus includes a sending unit and a receiving unit. The sending unit and receiving unit are configured to use credit-based handshaking signals to regulate data flow between themselves. The receiving unit includes a skid buffer for storing data packets received from the sending unit. The sending unit transmits one data packet to the receiving unit for each credit in possession and consumes one credit for each such transmitted data packet. The receiving unit transmits one credit to the sending unit for each data packet that is read out of the skid buffer. In another embodiment, transmitted data may be broadcast to multiple receiving units by routing the data from the sending unit to the multiple receiving units and maintaining separate credit-based handshaking signals for each receiving unit.

Abstract: A method and multi-component electronic module device are provided that control the timing of output of data from a plurality of components on the multi-component module. One or more of the components are programmed to delay outputting data by a corresponding amount of time. In one embodiment, the one or more components are programmed such that all of the components output data at substantially the same time when they respond to a control signal. This is particularly useful for multi-component modules that are configured to respond to control signals in a so-called fly-by (or other) configuration that results in the control signal arriving at the components at different times causing the components to react to the control signal at different times.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: A transaction switch and integrated circuit incorporating said for switching data through a shared memory between a plurality of data interfaces that support different data protocols, namely packetized interfaces like InfiniBand and addressed data interfaces like PCI. The transaction switch also switches transactions commanding data transfers between the disparate protocol data interfaces and between those of the data interfaces having like protocols. For example, the transaction switch enables a hybrid InfiniBand channel adapter/switch to perform both InfiniBand packet to local bus protocol data transfers through the shared memory as well as InfiniBand packet switching between the multiple InfiniBand interfaces. The transactions are tailored for each interface type to include information needed by the particular interface type to perform a data transfer.

Abstract: A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory element comprises at least one extra memory position more than the parallel memory element for the storage of the data signals.

Abstract: There is provided a system and a method for increasing input/output (“I/O”) throughput in a data storage system. More specifically, in one embodiment, there is provided a method comprising determining an owning controller associated with each of a plurality of storage units of a storage system, receiving an I/O transaction for one of the plurality of storage units, determining if the I/O transaction is a read transaction, and selecting a path to the owning controller associated with the storage unit if the I/O transaction is a read transaction.

Abstract: A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a periodic authorization signal to cause the memory access controller to remove the inhibition and write a predetermined amount of data to the memory through a data bus, and 2) releasing the data bus following writing of the predetermined amount of data to the memory by inhibiting the memory access controller from writing further data.

Abstract: When it is detected that a USB cable has been connected, a status of a function is discriminated. If there is no problem even if a USB enumeration is started, a USB signal is pulled up and the enumeration is started. If it is determined that trouble occurs as a function when the enumeration is started, the pull-up of the USB signal is extended and, after the trouble is solved, the USB signal is pulled up and the enumeration is started.

Abstract: A computer device is disclosed comprising at least one component operable to process commands at command intervals, and control circuitry operable to set an idle mode timeout interval. The control circuitry stores a plurality of the command intervals, and then evaluates the command intervals to set the timeout interval by finding a qualifying number of the command intervals that fall within a sliding window. The component is configured into an idle mode if a most recent command interval exceeds the timeout interval. In this manner, after entering the idle mode the probability that the next command will be processed within the sliding window is reduced, thereby helping to optimize power consumption.

Abstract: A system and method for performing speculative writestream transactions in a computing system. A computing system including a plurality of subsystems has a requesting subsystem configured to initiate a writestream ordered (WSO) transaction to perform a write operation to an entire coherency unit by conveying a WSO request to a home subsystem of the coherency unit. The requester is configured to perform the write operation without first receiving a copy of the coherency unit and complete WSO transactions initiated in the order in which they are initiated. The home subsystem is configured to process multiple WSO transactions directed to a given coherency unit in the order in which they are received. When the requester initiates a WSO transaction to a given coherency unit, the coherency unit is locked. Responsive to receiving the WSO request, the home subsystem conveys a pull request for the write data to the requester.

Abstract: A wireless bridge includes a first universal asynchronous receiver/transmitter (UART) for coupling to a serial bus that receives data packets. A protocol independent module has a timer set to a desired time to detect a start and/or an end of a data packet received from the serial bus. A wireless transceiver is coupled to the universal asynchronous receiver/transmitter for sending and receiving data packets.

Abstract: Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is converted to an output port. Incoming WRITE data is strobed-into the memory device and the resulting data pattern is compared to a desired pattern. If the incoming WRITE data and strobed-in data match, that result is sent to the graphical processing system by setting the DM pin HIGH. If the incoming WRITE data and the strobed-in data do not match, that result is sent to the graphical processing system by setting the DM pin LOW. Beneficially, the incoming data and the desired pattern are derived from pseudo random bit sequence (PRBS) sources.

Abstract: A computer system includes a central processing unit (CPU) including at least one compensation port, a register setting part to set a control value corresponding to a predetermined specification of the compensation port, and a controlling part to save the set control value and to output a control signal corresponding to the control value.

Abstract: A data transfer control system includes a buffer controller that controls access to a data buffer and a transfer controller that controls data transfer between a PC connected to a BUS1 and the logical units LUN1 and LUN2 connected to a BUS2. The transfer controller includes: a command processing section that starts data transfer to or from the LUN1 based on a command indicated by an ORB for the LUN1 when the ORB is received, and starts data transfer to or from the LUN2 based on a command indicated by an ORB for the LUN2 when the ORB is receive; and a wait processing section that waits the processing of the ORB for the LUN2, when a bus reset occurs during the processing of the ORB for the LUN1 and the ORB for the LUN2 is received after the bus reset has occurred.

Abstract: Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference clock signal, marked by the assertion of a periodic sync signal. The periodic sync signal, synchronous with the source clock, is used to output to an unload pointer counter in the target clock domain the deassertion of a reset signal prior to the nominal alignment of the source clock and the target clock for sampling on the nominally aligned target clock edge. The deassertion of the reset signal is output to a load pointer in the source clock domain coincident with the nominally-aligned edges of the source clock and the target clock. Both loading and unloading start based on the reset deassertion being sampled on the nominally aligned edges in the appropriate clock domain.

Abstract: A system improves reconstruction of real-time data in a packetized network. The system includes the following elements. A play-out buffer receives packets from the network. A playback element, coupled with the play-out buffer, retrieves packets from the play-out buffer and outputs data for the reconstruction of real-time data. A time adjuster alters the rate at which the data is output in accordance with the availability of the packets.

Abstract: Methods and Apparatuses are provided for automatically converting a word length of sample data being transmitted over a serial link. A serial interface transmits and/or receives one or more data words comprising digital signals, a bit clock synchronizes transmission of individual bits, and a word clock is used to group the bits into sample words. A desired word length is determined based on the relationship between the bit clock and the word clock during the transmission or reception of a data word. Based on the desired word length, the sample data is either truncated or padded, and an appropriate amount of dither is added to the sample words to reduce the distortion and quantization artifacts introduced by the word length conversion.

Abstract: Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional interference between the split units is prevented and stable remote copying is realized. SLPRs which are dedicated regions for the respective users are set inside the disk array device 10. Each SLPR is constituted by dividing various types of resources of ports, cache memories, logical units and the like, and cannot be accessed by an unauthorized host computer 1. Furthermore, a manager of one of the SLPRs likewise cannot refer to or alter the constructions of the other SLPRs. During remote copying, the amount of transfer within the unit time is detected for each of the SLPRs. If the amount of transfer within the unit time exceeds the maximum amount of transfer, a response to the host computer 1 from this SLPR is deliberately delayed, so that the inflow of data from the host computer 1 is restricted.

Abstract: A system and method for buffering bidirectional digital input/output (I/O) lines. The system (e.g., data acquisition system) may comprise a device including circuitry for buffering bidirectional digital lines. A first integrated circuit (IC) of the device includes a first and a second bidirectional buffer coupled to a first bidirectional digital I/O line, and a second IC of the device includes a third bidirectional buffer. The first IC and the second IC each include a control unit to control the driving direction of the corresponding bidirectional buffers independently to change the direction of the data flow through the first bidirectional digital I/O line from the output direction to the input direction or vice versa. The driving direction of the bidirectional buffers are changed at different times in a particular sequence, and the order depends on whether the direction change is from the output direction to the input direction or vice versa.

Abstract: A computer having an operating system is connected to a first memory. The computer operates to execute an on screen display (OSD) program in a first memory and a basic input output system (BIOS) application in a second memory. The BIOS application operates to display user information from user information data stored in the second memory on a display before the computer's operating system is loaded. The OSD program operates to display user information from the user information data stored in the second memory on the display after the computer's operating system is loaded. A process determines if a user input is selected, reads a memory for user information data if the user input is selected, and displays user information on a display before an operating system is loaded.

Abstract: A measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications. The system control loop may include the real-time monitoring circuit, a data acquisition device, a processing unit, and a plurality of subsystems. The subsystems may be comprised in the data acquisition device or may be external to the data acquisition device. The real-time monitoring circuit may receive a plurality of timing signals from the plurality of subsystems and may select a control loop timing signal out of the plurality of timing signals. The real-time monitoring circuit may determine whether the operations of the control loop are performed within a particular period of time by monitoring the control loop timing signal and communicating with the processing unit. In response to an error notification, the processing unit may take appropriate action, such as shutting down the system and/or reporting an error or warning.

Abstract: The present invention relates to a print subsystem architecture in which a port monitor buffers data received from a spooler and asynchronously reads the buffered print data and transmits it to a printer.

Abstract: An interrupt control device for issuing interrupts to a central processing unit (CPU) includes an object acquiring unit for acquiring data or resource(s) for use by the CPU and an interrupt issuing unit for issuing interrupts to the CPU. The interrupt issuing unit issues each interrupt to the CPU before the object acquiring unit actually acquires the data or the resource, but the interrupt indicates that the data or the resource is available. The interrupt control device further includes a use delay unit for delaying the use of the data or resource by the CPU unit until the object acquiring unit acquires the data or the resource if the CPU which has received the interrupt requests the use of the data or the resource before the object acquiring unit acquires the data or the resource. By adjusting the exact timing of the issuance of the interrupt according to the actual delays experienced by the CPU, the overall delays associated with interrupt handling are minimized.

Abstract: A method for increasing transmission efficiency of an electronic device using a serial peripheral interface includes receiving data from a first pin of the serial peripheral interface of the electronic device during a first duration according to a clock signal received from a clock pin of the serial peripheral interface of the electronic device, and outputting data from the first pin during a second duration according to the clock signal.

Abstract: Methods and systems are disclosed for detecting a presence of a device that includes providing a clock driver having a pair of differential clock signal lines capable of connection to a device, providing a presence detection signal for transmission through the pair of differential clock signal lines, determining whether the presence detection signal is received through the pair of differential clock signal lines, and identifying the presence of the device if the presence detection signal is received through the pair of differential clock signal lines.

Abstract: A signal processing device includes a start time obtaining part that obtains a start time when a predetermined process is started in response to an interrupt request associated with a valid edge of a pulse input signal, an edge occurrence time obtaining part that obtains a time of occurrence of the valid edge of the pulse input signal after the start time of the predetermined process is obtained, and a processing part that selectively performs a process based on a time relationship between the start time of the predetermined process and the time of occurrence of the valid edge.

Abstract: A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a first formatted input signal or a second formatted input signal to produce an amplified input signal. The data sampling module converts the amplified input signal into a first data stream in accordance with at least one first sampling clock signal when the interface is configured in the first mode and to converts the amplified input signal into a second data stream in accordance with at least a second sampling clock signal when the interface is in a second mode. The clocking module generates the first sampling clock signals from a reference clock when the multi-protocol interface is in a first operational mode and generates the second sampling clock signals based on the reference clock when the interface is in the second operational mode.

Abstract: An improved target and initiator. The initiator provides a starting address and length information on a bus synchronously with a clock signal. While the starting address and length information are present on the bus, the initiator provides a write or a read request signal that is activated and deactivated synchronously. The initiator then receives from the target unit a grant signal that is activated and deactivated synchronously. After the grant signal is deactivated, for a write operation, the initiator provides a number of write data items on the bus synchronously for capture by the target unit. For a read operation, the target provides a number of read data items on the bus synchronously for capture by the initiator unit. One data item provided in each clock cycle of the clock signal and the number of data items is determined by the length information provided.