Abstract: Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory and a controller which are configured such that the controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which is not a battery and may include, for example, a capacitor or capacitor array. The memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or the controller when the volatile memory is interacting with the host system.

Abstract: The present invention relates generally to the field of telecommunications systems and methods. More specifically, the present invention is directed to systems and methods for identifying and/or distributing music and other types of useful information for users in a very simple and convenient manner. A variety of systems and methods are disclosed which provide users with quick and convenient access to various forms of information, such as, for example, audio information including music and news items as well as coupons and other information. The systems and methods allow users to store data representative of a time of transmission and preferably a source of transmission so that data of interest may be identified for ordering an/or downloading.

Abstract: A memory controller includes a mixed buffer and an arbiter. The mixed buffer includes at least one single-port buffer and at least one multi-port buffer for managing data flow between a host and a storage device. The arbiter determines an order of access to the mixed buffer among a plurality of masters. The data to be written or read are partitioned into at least two parts, which are then moved to the single-port buffer and the multi-port buffer, respectively.

Abstract: Data communications through a host Fibre Channel adapter (‘HFCA’) implemented with a computer that includes two or more logical partitions, each logical partition including a separate instance of an operating system, each instance of an operating system including an instance of a low-level, switched fabric input/output (‘I/O’) library, including establishing, in the HFCA by instances of the I/O library in two or more logical partitions and by the hypervisor, separate logical Fibre Channel adapters (‘LFCAs’) for at least two of the logical partitions, each LFCA including an association of an LFCA identifier with at least one range of I/O memory addresses in the address space of a logical partition and transferring, at the behest of application programs in the two or more logical partitions, data between the RAM of the logical partitions and the data storage devices through the LFCAs, the HFCA, and the Fibre Channel fabric.

Abstract: A method of storing log entries of events from a plurality of network elements in a communication network, comprising the steps of: a) receiving log entries at a control processor of events from a plurality of different elements positioned, the log entries grouped into threads based on a common purpose; b) converting each log entry into a compact log record in a logging module, and c) storing the compact log records in a first memory buffer in random access memory (RAM) forming a first log file.

Abstract: A motherboard assembly includes a serial advanced technology attachment dual-in-line memory module (SATA DIMM) with a circuit board, a memory slot, and an interface. An edge connector is set on a bottom edge of the circuit board. A SATA connector is arranged on the circuit board, and connected to a control chip and the interface, enabling a motherboard communication with the SATA DIMM module.

Abstract: Embodiments of the invention provide a memory allocation module that adopts memory-pool based allocation and is aware of the physical configuration of the memory blocks in order to manage the memory allocation intelligently while exploiting statistical characters of packet traffic. The memory-pool based allocation makes it easy to find empty memory blocks. Packet traffic characteristics are used to maximize the number of empty memory blocks.

Abstract: An electronic apparatus is provided, which includes a central processing unit (CPU), a first memory unit which performs communication with the CPU, and a second memory unit which stores therein conditional access system (CAS) software and platform software. According to the method of controlling the apparatus, upon booting, the CPU copies the CAS software to an internal memory area which may be within the CPU, copies the platform software to the first memory unit and executes the CAS and platform software, and executes CAS operations through communication between the CAS software and the platform software.

Abstract: Systems, methodologies, media, and other embodiments associated with (de)compressing data at a time and in a location that facilitates increasing memory transfer bandwidth by selectively controlling a burst-mode protocol used to transfer data to and/or from a memory are described. One exemplary system embodiment includes a memory controller configured to (de)compress memory, to manipulate size data associated with compressed data, and to selectively manipulate a burst-mode protocol employed in transferring compressed data to and/or from random access memory.

Abstract: Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or processing may be reduced. First, data is received and pre-scanned to generate a sample fingerprint. Fingerprints stored in a faster memory that are similar to the sample fingerprint are identified. Data stored in the slower memory associated with the identified stored fingerprints is copied into the faster memory. The copied data may be compared to the received data. Various embodiments may be included in a network memory architecture to allow for faster data matching and instruction generation in a central appliance.

Abstract: Various embodiments of the present invention relate to a Unified Memory Architecture. The Unified Memory Architecture may use MRAM, phase change memory, and/or any other storage having similar features.

Abstract: A data storage system includes: a data storage medium configured to store data; a main controller configured to control an operation of the data storage medium; and a bridge chipset configured to convert a signal provided from the main controller according to a control information provided from an external source to the data storage medium and the main controller and to provide the converted signal to the data storage medium.

Abstract: An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtual machine instructions configured to access the volatile memory with a first virtual machine. The instructions including second virtual machine instructions configured to access the volatile memory with a second virtual machine. The instructions including virtual machine monitor instructions configured to page data out from a shared memory to a reserved memory section in the volatile memory responsive to the first virtual machine or the second virtual machine paging the data out from the shared memory or paging the data in to the shared memory. The shared memory is shared across the first virtual machine and the second virtual machine. The volatile memory includes the shared memory.

Abstract: A process of interacting with a memory module to restore data backed up from volatile memory to nonvolatile memory of the memory module involves a host system configuring the volatile memory of the module to interoperate with a host memory controller via a DIMM memory interface to the module; the host configuring a controller of the module to copy data from the nonvolatile memory to a peripheral I/O bus, the configuration of the controller of the module carried out via the peripheral I/O bus; a host I/O controller receiving the data copied to the peripheral I/O bus and communicating the received data to a host memory controller; and the host memory controller copying the received data to the volatile memory via the DIMM memory interface, thus completing a restore of the data from nonvolatile memory to the volatile memory.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.

Abstract: An integrated circuit for executing external program codes comprises a processor, a read only memory for storing program codes of a first routine and a second routine, and a random access memory comprising a first memory block and a second memory block. The processor executes the first routine and uses a plurality of first memory units in the first memory block for accessing data. The processor executes the second routine and uses a plurality of second memory units in the first memory block for accessing data. The first and second memory units comprise one or more common memory units. The processor executes a third routine stored in an external read only memory and accesses the data of the third routine in the second memory block.

Abstract: A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools of nodes with various sizes of PM. A node manager uses the pools of nodes to load applications to the nodes according to the size of the available PM. The PM Manager can dynamically adjust the size of the PM according to the needs of the applications based on historical use or as determined by a system administrator. The PM Manager works with an operating system kernel on the nodes to provide persistent memory for application data and system metadata. The PM Manager uses the persistent memory to load applications to preserve data from one application to the next. Also, the data preserved in persistent memory may be system metadata such as file system data that will be available to subsequent applications.

Abstract: An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).

Abstract: A memory manager in a computer system that ages memory for high performance. The efficiency of operation of the computer system can be improved by dynamically setting an aging schedule based on a predicted time for trimming pages from a working set. An aging schedule that generates aging information that better discriminates among pages in a working set based on activity level enables selection of pages to trim that are less likely to be accessed following trimming. As a result of being able to identify and trim less active pages, inefficiencies arising from restoring trimmed pages to the working set are avoided.

Abstract: A method, computer program product, and cache management system for receiving an indication of a data portion update within an electromechanical storage system. Information concerning the data portion update is provided to at least one proprietary, solid-state, non-volatile, cache memory system. The proprietary, solid-state, non-volatile, cache memory system is associated with at least a first of a plurality of computing devices and is not associated with at least a second of the plurality of computing devices.

Abstract: A microcontroller includes a RAM control unit configured to: perform a RAM access operation when an address designated by a CPU is within a range of a designated area; and read a program from a Flash EEPROM when the address is out of the range of the designated area. As the RAM access operation, the RAM control unit is configured to: read the program from the Flash EEPROM, store the read program into the RAM, and change valid bit information into a valid state, when the valid bit information indicates an invalid state; and output the program stored in the RAM to the CPU when the valid bit information indicates the valid state.

Abstract: The system of the present invention includes an instruction fetch unit 10, an instruction cache 20, a macro cache unit 30 for associating an instruction with one or more addresses in the main memory storing the instruction and holding the instruction and addresses, and a macro registration determining means 40 for holding instructions in the instruction cache 20 with a high cache hit frequency in the macro cache unit 30. The macro cache unit 30 associates the address specifying the instruction with an already held instruction and holds the address when the instruction specified for holding by the macro registration determining unit 40 is the same instruction already held, and associates the instruction with an address specifying the instruction and holds the instruction and the address when the instruction specified for holding by the macro registration determining unit 40 is not the same instruction being held.

Abstract: Paging memory from random access memory (‘RAM’) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.

Abstract: A wireless communication device is provided. The device is connectable to a first wireless network including an access point and a second wireless network including a terminal having an access point function. The device includes a setting section which stores setup data in a volatile storage area, a communication section which performs wireless communication using the setup data stored in the volatile storage area, and a determination section which determines which wireless networks the device is to be connected to. If the device is to be connected to the first wireless network, the setting section stores first setup data from the access point into the volatile storage area and a non-volatile storage area. If the device is to be connected to the second wireless network, the setting section stores second setup data from the terminal into the volatile storage area without storing it into the non-volatile storage area.

Abstract: A method of storing data includes receiving data to be written to a memory device. The method includes selecting a scrambling operation from at least a first scrambling operation and a second scrambling operation. The scrambling operation is selected based on a transition characteristic associated with the data. The method includes scrambling the data according to the selected scrambling operation and storing the scrambled data in the memory device. Additionally, the method may include descrambling the scrambled data to produce descrambled data.

Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

Abstract: An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory.

Abstract: A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.

Abstract: A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.

Abstract: A memory system architecture is provided in which a memory controller controls operations of memory devices in a serial interconnection configuration. The memory controller has an output serial interface for sending memory commands and an input serial interface for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, flash memory (e.g., NAND- and NOR-type flash memories). In an initialization phase, the memory devices are assigned with consecutive number addresses. The memory controller sends a target address and can recognize the type of the targeted memory device. A data path for the memory commands and the memory responses is provided by the interconnection.

Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

Abstract: An embedded device is hibernated by storing state data of the embedded device to a non-volatile data storage medium, and powering off the embedded device. The embedded device is later woken up in response to the detection of a wakeup event. The state data stored in the RAM of the embedded device comprises one or more registers of a Central Processing Unit (CPU) of the embedded device, one or more registers of a system-on-chip (SOC) of the embedded device, and the system and applications code and data. Waking the embedded device comprises loading, from the non-volatile data storage medium, initial memory sections that are used to run a kernel of the embedded device. State data that is stored in the RAM of a system is compressed by dividing the RAM into a plurality of sections and independently choosing, for each section in the plurality of sections, a compression arithmetic.

Abstract: Embodiments of the present invention provide an adaptive cache system and an adaptive cache system for a hybrid storage system. Specifically, in a typical embodiment, an input/out (I/O) traffic analysis component is provided for monitoring data traffic and providing a traffic analysis based thereon. An adaptive cache algorithm component is coupled to the I/O traffic analysis component for applying a set of algorithms to determine a storage schema for handling the data traffic. Further, an adaptive cache policy component is coupled to the adaptive cache algorithm component.

Abstract: A data processing apparatus includes an auxiliary storage device having target verification data stored therein, a program memory having a validity verification program stored therein, a first RAM (Random Access Memory), a second RAM, and an execution unit configured to execute a validity verification process in accordance with the validity verification program stored in the program memory. The execution unit is configured to copy the target verification data from the auxiliary storage device into the first RAM, execute the validity verification process on the copied target verification data in the first RAM, and use the second RAM as a work area in a case of executing the validity verification process.

Abstract: The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.

Abstract: A boot sequence method comprises a determination step 110 and 200, a first starting step 120, 210 or 240 for starting a first interface, a first negotiation step 140 or 220 wherein a power negotiation is performed, a second negotiation step 140 or 230 for determining the interfaces to activate simultaneously, and a second starting step 150 or 230 wherein the interfaces that can be activated simultaneously are started one after each other.

Abstract: An electronic data system comprises memory storage having stored data, file system software, and a transaction file. The transaction file is maintained by the file system software, and includes a plurality of transaction records corresponding to transactions that have been or are to be executed on one or more files and/or the or more directories of the file system. The file system software operates to organize and maintain the stored data in the files and directories and also to coalesce multiple transaction records meeting one or more criteria into fewer coalesced transaction records. The physical memory space required by the transaction file is reduced by the transaction record coalescing. The coalesced transaction records may be constructed so that they represent a logical result of applying each transaction record of a transaction record set in chronological order.

Abstract: A system and method for clients, a control module, and storage modules to participate in a unified address space in order to and read and write data efficiently using direct-memory access. The method for reading data includes determining a first location in a first memory to write a first copy of the data, a second location in a second memory to write a second copy of the data, where the first memory is located in a first storage module including a first persistent storage and the second memory is located in a second storage module including a second persistent storage. The method further includes programming a direct memory access engine to read the data from client memory and issue a first write request to a multicast address, where the first location, the second location, and a third location are associated with the multicast address.

Abstract: Systems, methods, and computer storage media for storing and retrieving data from a data store in a distributed computing environment are provided. An embodiment includes receiving data at a data store comprising a sequential journal store, RAM, and a non-sequential target store. When RAM utilization is below a threshold, received data is stored to the RAM as a write cache for the target store and the journal store. But, when the utilization is above the threshold, the data is stored to the journal store without write-caching to the RAM for the target store. When the RAM utilization falls below a threshold, data committed to the journal store, but not write-cached to the RAM for the target store, is later read from the journal store and write-cached to the RAM for a target store.

Abstract: A system, method and computer program product for scalable metadata acceleration with datapath metadata backup as disclosed includes providing a plurality of metadata comprising variable block pointers for the physical location of system data. The method also includes storing at least a first and a second metadata in two or more solid state memories accelerated with respect to a read and a write of a memory in a datapath, each solid state memory configured as a logical copy of the other. The method additionally includes interleaving a backup metadata in a datapath memory at a variable interval based on a table of block pointers. The method further includes querying the accelerated metadata for an accelerated datapath operation of the system and querying the interleaved metadata and/or a logical mirror of the accelerated metadata for a rebuild operation of the accelerated metadata, each query determinable by the table of block pointers.

Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.

Abstract: A computer-implemented method for transferring data from a computer system programmed to perform the method includes receiving in a memory buffer in a first memory module hosted by the computer system, a request for data stored in RAM of the first memory module from a host controller of the computer system, retrieving with the memory buffer, the data from the RAM, in response to the request, formatting with the memory buffer, the data from the RAM into formatted data in response to a defined software transport protocol, and initiating with the memory buffer, transfer of the formatted data to a storage destination external to the first memory module via an auxiliary interface of the memory buffer, bypassing the host controller of the computer system.

Abstract: A method and system are disclosed for handling host write commands associated with both data aligned with physical page boundaries of parallel write increments in non-volatile storage areas in a non-volatile storage device and data unaligned with the physical page boundaries. The method may include a controller of a storage device identifying the aligned and unaligned portions of received data, temporarily storing the aligned and unaligned portions in different queues, and then writing portions from the unaligned data queue or the aligned data queue in parallel to the non-volatile memory areas when one of the queues has been filled with a threshold amount of data or when the controller detects a timeout condition. The system may include a storage device with a controller configured to perform the method noted above, where the non-volatile memory areas may be separate banks and the queues are random access memory.

Abstract: A memory device which includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable write of the data units of the burst of data, the memory device allowing a next burst write or read command to begin before the completion of the burst write operation and while receiving data units of the next burst of data to be written or providing read data.

Abstract: The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory management device. The first memory includes a normal access memory bank and at least one switching access memory bank. The secondary memory includes at least one secondary access memory bank corresponding to the switching access memory bank. The memory management device reads/writes the normal access memory bank or the secondary access memory bank.

Abstract: An integrated circuit device includes a first plurality of non-volatile memory locations such as fuses that supply programmed values corresponding to initially selected device features such as voltage, frequency, clock speed, and cache parameters. The device is programmed with a lock value in a second plurality of non-volatile memory locations. That lock value may be a randomly generated number that is unique for each device. After initial programming of the device, access to the device is prevented by appropriately programming access control. In order to unlock the device and modify device features, an unlock key value is supplied to the device. If the unlock key value correctly corresponds to the lock value, the device features can be modified. In that way device features can be modified, but security is maintained to prevent unauthorized modification to device features.

Abstract: A hardware memory control unit that includes a register block and hardware logic. The register block includes, for a hardware memory segment, an access count register, a low threshold register, and a high threshold register. The hardware logic includes functionality to increment the access count stored in the access count register for each memory access to the hardware memory segment performed during a predefined duration of time, and, at the end of the predefined duration of time, perform a response action when the access count stored in the access count register is less than the low threshold stored in the low threshold register, and perform a response action when the access count stored in the access count register is greater than the high threshold stored in the high threshold register. A power saving mode of the hardware memory segment is modified based on performing the response action.

Abstract: A computing system includes computer memory of a number of different memory types. An application program compiled for execution on the computing system controls access to a field of a record in the computer memory of the computing system by defining a record that includes one or more fields, the one or more fields including a restricted field having a specification of restricted accessibility when the restricted field is allocated in a particular memory type; allocating an instance of the record in memory of the particular memory type; and denying each attempted access of the restricted field while the record is allocated in the particular memory type.

Abstract: One embodiment of the present invention sets forth a hybrid memory module that combines memory devices of different types while presenting a single technology interface. The hybrid memory module includes a number of super-stacks and a first interface configured to transmit data between the super-stacks and a memory controller. Each super-stack includes a number of sub-stacks, a super-controller configured to control the sub-stacks, and a second interface configured to transmit data between the sub-stacks and the first interface. Combining memory devices of different types allows utilizing the favorable properties of each type of the memory devices, while hiding their unfavorable properties from the memory controller.

Abstract: A memory system including a primary memory storage partition, a secondary memory storage partition, and a memory controller that is connected to read and write to the primary memory storage partition and detect a permanent bit error at an address associated with the primary memory storage partition. In response to a detected permanent bit error, the memory controller stores data from the address associated with the permanent bit error to an address associated with the secondary memory storage partition.