Abstract: When a relaying apparatus receives communication unit data transmitted from a processing apparatus that performs data processing, the relaying apparatus extracts preset data from the received communication unit data as trace information and calculates the number of pieces of the received communication unit data. History information of the received communication unit data is selected from the extracted trace information and statistical information obtained from the result of the calculation. The selected information is recorded in a storage apparatus available to the processing apparatus.

Abstract: Provided are memory control apparatus and methods for controlling data transfer between a memory controller and at least two logical memory busses connected to memory, comprising a memory controller; a buffer; a bidirectional data bus connecting the controller and the buffer; a control interface connecting the controller and the buffer, the buffer being connected to at least two logical memory busses for memory read and write operations, the buffer comprising data storage areas to buffer data between the controller and the logical memory busses, and logic circuits to decode memory interface control commands from the controller; and a data access and control bus connecting the buffer and each of the logical memory busses to control memory read and write operations.

Abstract: A memory device includes a block of memory cells and a cache. The block of memory cells is not a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.

Abstract: A file comprising an application and data corresponding to a status of the application at a particular time is maintained in a first memory of a user device, the first memory comprising a persistent storage. The application may be a software application, for example. In response to a request, the file is transferred to a second memory of the device, the second memory comprising a random-access memory. The file is activated, or set up, as a running application. The user device may be a cell phone, a wireless telephone, a personal digital assistant, a personal computer, a laptop computer, a workstation, a mainframe computer, etc. In one embodiment, the file is brought to a foreground of the user device.

Abstract: According to one embodiment, an information processor configured to execute codes described in Open Computing Language (OpenCL) includes: a first cache; a second cache; a global memory; and an arithmetic module. The first cache is with local scope and configured to be capable of being referred to by all work items in one workgroup. The second cache is with global scope and configured to be capable of being referred to by all work items in a plurality of workgroups. The global memory is with global scope and configured to be capable of being referred to by all work items in a plurality of workgroups. The arithmetic module is configured to execute a code referring to the second cache as a scratch-pad memory.

Abstract: A security context management system within a security accelerator that can operate with high latency memories and can provide line-rate processing on several security protocols. The method employed hides the memory latencies by having the processing engines working in a pipelined fashion. It is designed to auto-fetch security context from external memory, and will allow any number of simultaneous security connections by caching only limited contexts on-chip and fetching other contexts as needed. The module does the task of fetching and associating security context with ingress packet, and populates the security context RAM with data from the external memory.

Abstract: A memory apparatus includes multiple memory circuits an interface circuit having one or more first components of a first type and one or more second components of a second type different from the first type, each of the one or more first components and second components being electrically couplable to a host system. The interface circuit is operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one memory circuit of the plurality of memory circuits. The at least one aspect includes a timing that relates to a refresh operation latency, in which each memory circuit of the plurality of memory circuits is electrically coupled to at least one first component and to at least one second component.

Abstract: Embodiments include a system, an apparatus, a device, and a method. The apparatus includes a processor, a dynamic memory, and a hardware-implemented memory control circuit. The hardware-implemented control circuit includes a control circuit for establishing an extended refresh period of the dynamic memory based at least in part on a monitored result that indicates an occurrence of a memory loss in the dynamic memory. The hardware-implemented control circuit also includes a control circuit for causing a refresh of the dynamic memory during each of at least two extended refresh periods.

Abstract: A computing device is provided and includes a memory module, a sweep engine, a root snapshot module, and a trace engine. The memory module has a memory implemented as at least one hardware circuit. The memory module uses a dual-ported memory configuration. The sweep engine includes a stack pointer. The sweep engine is configured to send a garbage collection signal if the stack pointer falls below a specified level. The sweep engine is in communication with the memory module to reclaim memory. The root snapshot engine is configured to take a snapshot of roots from at least one mutator if the garbage collection signal is received from the sweep engine. The trace engine receives roots from the root snapshot engine and is in communication with the memory module to receive data.

Abstract: In a particular embodiment, a storage device with a memory, a controller, and a host interface has a write-once read-many device configuration. The memory contains a database having entries, each entry for a logical memory address. The memory further contains information for converting each logical memory address to a redirected logical memory address that corresponds to a physical memory location. The controller receives a command specifying a logical memory address and interprets the command based on information extracted from the database. The controller executes the command according to the information.

Abstract: A memory apparatus includes multiple memory circuits and an interface circuit to present to a host system emulated memory circuits. The interface circuit includes a first component of a first type and a second component of a second type, the first component and the second component being operable to present a host-system interface to the host system and to present a memory-circuit interface to the plurality of memory circuits, in which there is a difference in at least one aspect between the host-system interface and the memory circuit interface. At least one of the first and second components is operable to identify one or more memory circuits that is not being accessed and to perform a power-saving operation on the one or more memory circuits identified as not being accessed, where the power-saving operation includes placing the memory circuits identified as not being accessed in a precharge power down mode.

Abstract: One embodiment of the present invention sets forth a technique for providing a L1 cache that is a central storage resource. The L1 cache services multiple clients with diverse latency and bandwidth requirements. The L1 cache may be reconfigured to create multiple storage spaces enabling the L1 cache may replace dedicated buffers, caches, and FIFOs in previous architectures. A “direct mapped” storage region that is configured within the L1 cache may replace dedicated buffers, FIFOs, and interface paths, allowing clients of the L1 cache to exchange attribute and primitive data. The direct mapped storage region may used as a global register file. A “local and global cache” storage region configured within the L1 cache may be used to support load/store memory requests to multiple spaces. These spaces include global, local, and call-return stack (CRS) memory.

Abstract: A method and apparatus for accessing a storage media employed to store data from a host includes identifying a module as a block storage device. The block storage device is coupled to a host and includes a bridge controller and magnetic random access memory (MRAM). The MRAM has a buffer window for storing data from a host, the buffer window is movable throughout the MRAM. The bridge controller has a bridge controller buffer and controller registers. A request to access the block storage device is intercepted and a command to the block storage device is issued. If the command is a write command, at least a portion of the data to be saved into the MRAM is saved. The size of the at least a portion of the data is based on the capacity of the bridge controller buffer. Further, at least a portion of the data to the buffer window is transferred and upon having additional data to be saved into the MRAM, the buffer window is moved within the MRAM.

Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: There is provided a method and computer system for object persistency that includes: running a program; storing an object of the program into a random access memory in response to determining that the object is a non-persistent object; and storing the object into a phase change memory in response to determining that the object is a persistent object. The method and computer system of the present disclosure do not need separate persistency layers, such that the programming model is light weighted, the persistency of object data is more simple and fast, and implicit transaction process is supported, thereby a great deal of development and runtime costs are saved.

Abstract: A storage battery control device detects an overhead wire supply current value showing a sum of a current value output from a storage battery and a current value output from a transformer substation, and charging or discharging of the storage battery is controlled so that a charging rate of the storage battery becomes a charging rate target value when the detected overhead wire supply current value is less than a first threshold. In addition, charging or discharging of the storage battery is controlled so that the output voltage of the storage battery control device is maintained at a constant voltage control mode when the detected overhead wire supply current value is greater than or equal to the first threshold.

Abstract: A method and system are disclosed for allowing access to processing resources of one or more idle memory devices to an active memory device is disclosed, where the idle and active memory devices are associated with a common host. The resources shared may be processing power, for example in the form of using a processor of an idle memory to handle some of the logical-to-physical mapping associated with a host command, or may be other resources such as RAM sharing so that a first memory has expanded RAM capacity. The method may include exchanging tokens with resource sharing abilities, operation codes and associated data relevant to the requested resources.

Abstract: Systems for automatically calibrating a storage memory controller are disclosed. In some embodiments, the systems may be realized as a solid state device system with an electro-static discharge (ESD) protection capability. The system can include a memory controller electrically coupled to a channel, where the memory controller is configured to select at least one of a plurality of flash memory devices. The system can also include at least one isolation device including an ESD protection circuit, configured to electrically couple the channel to the at least one of the plurality of flash memory devices and to decouple the channel from the remaining of the plurality of flash memory devices.

Abstract: A storage controlling apparatus includes a command decoder and command processing section. The command decoder decides whether or not a plurality of access object addresses of different commands included in a command string correspond to words different from each other in a same one of blocks of a memory cell array which have a common plate. The command processing section collectively and successively executes, when it is decided that the access object addresses of the commands correspond to the words different from each other in the same block of the memory cell array, those of operations in processing of the commands in which an equal voltage is applied as a drive voltage between the plate and a bit line.

Abstract: The present disclosure involves a method. As a part of the method, a logically sequential range of memory blocks is allocated for sequential access. A pointer is initialized with an address of a first memory block that is within the range of the memory blocks. In response to a data write next request, data is written into the range of the memory blocks, starting with the first memory block and continuing sequentially in subsequent memory blocks within the range until the data write next request is completed. Thereafter, the pointer is updated based on a last memory block in which data is written.

Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

Abstract: A method and controller for implementing storage adapter performance optimization with chained hardware operations completion coalescence, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines, and a processor. A plurality of the command blocks are selectively arranged by firmware in a predefined chain including a plurality of simultaneous command blocks. All of the simultaneous command blocks are completed in any order by respective hardware engines, then the next command block in the predefined chain is started under hardware control without any hardware-firmware (HW-FW) interlocking with the simultaneous command block completion coalescence.

Abstract: Described is using flash memory, RAM-based data structures and mechanisms to provide a flash store for caching data items (e.g., key-value pairs) in flash pages. A RAM-based index maps data items to flash pages, and a RAM-based write buffer maintains data items to be written to the flash store, e.g., when a full page can be written. A recycle mechanism makes used pages in the flash store available by destaging a data item to a hard disk or reinserting it into the write buffer, based on its access pattern. The flash store may be used in a data deduplication system, in which the data items comprise chunk-identifier, metadata pairs, in which each chunk-identifier corresponds to a hash of a chunk of data that indicates. The RAM and flash are accessed with the chunk-identifier (e.g., as a key) to determine whether a chunk is a new chunk or a duplicate.

Abstract: Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or processing may be reduced. First, data is received and pre-scanned to generate a sample fingerprint. Fingerprints stored in a faster memory that are similar to the sample fingerprint are identified. Data stored in the slower memory associated with the identified stored fingerprints is copied into the faster memory. The copied data may be compared to the received data. Various embodiments may be included in a network memory architecture to allow for faster data matching and instruction generation in a central appliance.

Abstract: Described is using flash memory, RAM-based data structures and mechanisms to provide a flash store for caching data items (e.g., key-value pairs) in flash pages. A RAM-based index maps data items to flash pages, and a RAM-based write buffer maintains data items to be written to the flash store, e.g., when a full page can be written. A recycle mechanism makes used pages in the flash store available by destaging a data item to a hard disk or reinserting it into the write buffer, based on its access pattern. The flash store may be used in a data deduplication system, in which the data items comprise chunk-identifier, metadata pairs, in which each chunk-identifier corresponds to a hash of a chunk of data that indicates. The RAM and flash are accessed with the chunk-identifier (e.g., as a key) to determine whether a chunk is a new chunk or a duplicate.

Abstract: In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.

Abstract: Embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. Additional embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, a variety of different types of electronic devices. One embodiment of the present invention comprises a memory controller implemented in a first integrated circuit or other electronic system and one or more separate memory devices. Alternative embodiments of the present invention incorporate the memory controller within one or more memory devices that are connected to, and accessed by, an integrated-circuit-implemented computational engine or another electronic device.

Abstract: A method and a system are disclosed for storing initial data from an image detecting device in a camera system initial storage medium and making the data accessible. The initial data is stored consecutively in blocks, where file specific pointers representing the starting address for each stored file and file sequence, and dynamic memory pointers that points out the next writable address, are managed and stored during real time writing of the data. The data is made accessible through a virtual representation of the data in a virtual file system with a format known by an external storage medium controller, the virtual representation being related to the file specific pointers.

Abstract: To increase the number of analog inputs at low cost, an analog input system includes: one or more analog slave units each connected to a bus to which a CPU unit is connected, and each including an A/D-conversion device converting an analog value outputted by an external device into a first digital value, a buffer memory buffering a second digital value to be transferred to the CPU unit, and a nonvolatile storage device containing specific information of its own unit; and an analog master unit connected to the bus and including an operation section performing operation processing based on the specific information stored in the storage device with the first digital value being used as an input, to calculate the second digital value, the master unit performing on each of the slave input units the operation processing and processing of transferring the calculated second digital value to the buffer memory.

Abstract: A system and associated method for monitoring the execution of software on one or more computers by receiving traffic from within the monitored computer(s). The monitoring may take place passively, such that the operation of the monitored computer or computers is completely unaffected by the monitoring. More intensive monitoring, such as maintenance of a shadow copy of the RAM of the monitored computer, may be initiated upon recognition of a pattern in the data received from the monitored computer. The execution of software on the monitored computer may be halted by the monitoring module. The monitoring module may also read from or write to the memories of the monitored computer.

Abstract: A nonvolatile memory system comprises a temporary power supply that supplies power in the event of an unexpected power interruption. The temporary power supply provides power while metadata stored in one or more buffers is compressed and transferred to a nonvolatile memory device.

Abstract: A system and method for clients, a control module, and storage modules to participate in a unified address space in order to and read and write data efficiently using direct-memory access. The method for reading data includes determining a first location in a first memory to write a first copy of the data, a second location in a second memory to write a second copy of the data, where the first memory is located in a first storage module including a first persistent storage and the second memory is located in a second storage module including a second persistent storage. The method further includes programming a direct memory access engine to read the data from client memory and issue a first write request to a multicast address, where the first location, the second location, and a third location are associated with the multicast address.

Abstract: A method and apparatus manages a buffer cache. An extended buffer is used to perform a page replacement algorithm using reference time information regarding a time at which a page is referred. Pages replaced through the page replacement algorithm, when re-referred to, may be retrieved from the extended buffer, instead of a hard disk. As a result, write/read operations with respect to the disk are made efficient and the page input/output speed is increased.

Abstract: At least one of configuration information of a storage volume stored on a storage system and characteristics of a snapshot, including characteristics of one or more files stored in the snapshot, are identified. Snapshot content metadata, comprising the at least one of the identified characteristics and the configuration information, is created. The snapshot content metadata is associated with the snapshot.

Abstract: Systems, devices and methods according to these exemplary embodiments provide for memory management techniques and systems for storing data. Data is segmented for storage in memory. According to one exemplary embodiment, each fragment is routed via a different memory bank and forwarded until they reach a destination memory bank wherein the fragments are reassembled for storage. According to another exemplary embodiment, data is segmented and stored serially in memory banks.

Abstract: An apparatus for adjusting a memory transfer setting includes a storage device storing machine-readable code and a processor executing the machine-readable code. The machine-readable code includes a determination module determining that an amount of main memory exceeds a threshold percentage of secondary storage on an information handling device. The machine readable code also includes an adjustment module adjusting a memory transfer setting on the information handling device in response to the determination module determining that the amount of main memory exceeds the threshold percentage.

Abstract: One embodiment of the present invention relates to a CPU cache system that stores tag information and cached data in the same SRAM. The system includes an SRAM memory device, a lookup buffer, and a cache controller. The SRAM memory device includes a cache data section and a cache tag section. The cache data section includes data entries and the tag section includes tag entries associated with the data entries. The tag entries include memory addresses that correspond to the data entries. The lookup buffer includes lookup entries associated with at least a portion of the data entries. The number of lookup entries is less than the number of tag entries. The cache controller is configured to perform a speculative read of the cache data section and a cache check of the lookup buffer simultaneously or in a single cycle.

Abstract: Methods, systems, and computer readable storage medium embodiments for configuring a lookup table, such as an access control list (ACL) for a network device are disclosed. Aspects of these embodiments include storing a plurality of data entries in a memory, each of the stored plurality of data entries including a header part and a body part, and encoding each of a plurality of bit-sequences in the header part of a stored data entry from the plurality of data entries to indicate a bit comparing action associated with a respective bit sequence in the body part of the stored data entry. Other embodiments include searching a lookup table in a network device.

Abstract: A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.

Abstract: Using integrated circuits, such as field programmable gate arrays, it is possible to transfer data to common off the shelf storage devices at high speeds which would normally be associated with special purpose hardware created for a particular application. Such high speed storage can include prefetching data to be stored from a memory element into a cache, and translating the commands which will be used in accomplishing the transfer into a standard format, such as peripheral component interconnect express.

Abstract: A method of securely transferring data. The source data stored in a source memory (NV_MEM) is compared with the transferred data (COPY_ELT_X_V_MEM) that has been copied from the source memory (NV_MEM) into a “destination” memory (V_MEM). The method consists in reading from the source memory (NV_MEM) an integrity value (PI_ELT_X) associated with an element (ELEMENT_X_NV_MEM) such as file containing the source data, in calculating the integrity of a reconstituted element made up of the transferred data (COPY_ELT_X_V_MEM) associated, where appropriate, with the data of the source element (ELEMENT_X_NV_MEM) other than the data that was transferred, and in deciding that the transferred data (COPY_ELT_X_V_MEM) is identical to the source data when the integrity calculation gives a value identical to the integrity value of the source element (PI_ELT_X). The method applies to transferring data between components of a smart card.

Abstract: An auto-commit memory is capable of implementing a pre-configured, triggered commit action in response to a failure condition, such as a loss of power, invalid shutdown, fault, or the like. A computing device may access the auto-commit memory using memory access semantics (using a memory mapping mechanism or the like), bypassing system calls typically required in virtual memory operations. Since the auto-commit memory is pre-configured to commit data stored thereon in the event of a failure, users of the auto-commit memory may view these memory semantic operations as being instantly committed. Operations to commit the data are taken out of the write-commit path.

Abstract: Apparatus and method for placing data based on the content of the data in random access memory such that indexing operations are not required. A strong (e.g., cryptographic) hash is applied to a data element resulting in a signature. A weaker hash function is then applied to the signature to generate a storage location in memory for the data element. The weaker hash function assigns multiple data elements to the same storage location while the signature comprises a unique identifier for locating a particular data element at this location. In one embodiment a plurality of weak hash functions are applied successively to increase storage space utilization. In other embodiments, the assigned storage location can be determined by one or more attributes of the data element and/or the storage technology, e.g, long-lived versus short-lived data and/or different regions of the memory having different performance (e.g., access latency memory lifetime) characteristics.

Abstract: Techniques are described for controlling availability of memory. As memory write operations are processed, the contents of memory targeted by the write operations are read and compared to the data to be written. The availability of the memory for subsequent write operations is controlled based on the outcomes of the comparing. How many concurrent write operations are being executed may vary according to the comparing. In one implementation, a pool of tokens is maintained based on the comparing. The tokens represent units of power. When write operations require more power, for example when they will alter the values of more cells in PCM memory, they draw (and eventually return) more tokens. The token pool can act as a memory-availability mechanism in that tokens must be obtained for a write operation to be executed. When and how many tokens are reserved or recycled can vary according to implementation.

Abstract: A system for booting an operating system from a virtual hard disk. A partitioned memory segment is formed within a memory by a preconfigured amount. A boot application is loaded into the partitioned memory segment to form a virtual hard disk. In response to determining that the virtual hard disk contains an operating system, the operating system is booted from the virtual hard disk.

Abstract: The present invention is directed to systems and methods for optimizing garbage collection in data storage. The data storage may be a shingled disk drive or a non-volatile solid-state memory device. Garbage collection is optimized by selectively saving data read from certain locations of the data storage in response to host read commands and using the saved data for subsequent garbage collection operations. The decision of whether to save data may be based on a number of criteria, including whether the data is located in an area of the data storage that is due to be garbage collected in the near future. In this manner, certain garbage collection operations can be performed without having to re-read the saved data.

Abstract: A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.

Abstract: Presented herein are system(s), method(s), and apparatus for reducing on-chip memory requirements for audio decoding. In one embodiment, there is presented a method for decoding encoded audio signals. The method comprises fetching a first one or more tables from an off-chip memory; loading the first one or more tables to an on-chip memory; applying a first function to the encoded audio signals using the first one or more tables; fetching a second one or more tables from an off-chip memory after applying the first function; loading the second one or more tables to an on-chip memory; and applying a second function to the encoded audio signals, using the second one or more tables.

Abstract: A RAM disk driver 112 receives the user's specification for the capacity of a RAM disk 122 via an operation screen image 10 (step S20). The RAM disk driver 112 sets a continuous region in an OS invisible area, which is beyond management of an operating system installed in a computer, on a RAM 120 for a storage area of the RAM disk 122 having the user's specified capacity (step S30). When the user's specified capacity is greater than the capacity of the OS invisible area on the RAM 120, the RAM disk driver 112 reduces the range of an OS visible area, which is managed by the operating system, on the RAM 120 and sets the storage area of the RAM disk 122 in the expanded OS invisible area. This arrangement effectively boosts up access to the RAM 120 as the primary storage in the computer.