Abstract: Systems, apparatuses and methods may provide for associating a first instruction pointer with an IF block of a primary IF-ELSE conditional construct associated with a thread and activating a second instruction pointer in response to a dependency associated with the IF block. Additionally, the second instruction pointer may be associated with an ELSE block of the primary IF-ELSE conditional construct. In one example, the IF block and the ELSE block are executed, via the first instruction pointer and the second instruction pointer, one or more of independently from or parallel to one another.

Abstract: An image processing apparatus includes a plurality of cores and an arithmetic processing device. The plurality of cores are configured to be allocated to a plurality of tiles obtained by dividing a single image data; a configured to control allocation of the plurality of cores based on the divided tiles. The arithmetic processing device is configured to control allocation of the plurality of cores based on the divided tiles. The arithmetic processing device allocates all of the plurality of cores to a single line of the plurality of tiles in a second direction, when the single image data is divided into the plurality of tiles in a first direction and the second direction different from the first direction.

Abstract: Transactional memory accesses are tracked using read and write sets based on actual program flow. A read and write set is associated with a range of instructions of a transaction. When execution follows a predicted branch, loads and stores are marked as being of selected read and write sets. Then, when a misprediction is processed, and execution is rewound, speculatively added read and write set indications are removed from the read and write sets.

Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

Abstract: Transactional memory accesses are tracked using read and write sets based on actual program flow. A read and write set is associated with a range of instructions of a transaction. When execution follows a predicted branch, loads and stores are marked as being of selected read and write sets. Then, when a misprediction is processed, and execution is rewound, speculatively added read and write set indications are removed from the read and write sets.

Abstract: An apparatus and method for adaptive spatial accelerated prefetching. For example, one embodiment of an apparatus comprises: execution circuitry to execute instructions and process data; a Level 2 (L2) cache to store at least a portion of the data; and a prefetcher to prefetch data from a memory subsystem to the L2 cache in anticipation of the data being needed by the execution unit to execute one or more of the instructions, the prefetcher comprising a buffer to store one or more prefetched memory pages or portions thereof, and signature data indicating detected patterns of access to the one or more prefetched memory pages; wherein the prefetcher is to prefetch one or more cache lines based on the signature data.

Abstract: A system for archiving includes an active memory, an archive memory, an interface, and a processor. The interface is to receive an indication to archive an object in the active memory. The object has a relation to an other object. The processor is to archive the object in the archive memory. The other object maintains the relation with the object that has been archived.

Abstract: Techniques and apparatuses are described that enable power-conserving cache memory usage. Main memory constructed using, e.g., DRAM can be placed in a low-power mode, such as a self-refresh mode, for longer time periods using the described techniques and apparatuses. A hierarchical memory system includes a supplemental cache memory operatively coupled between a higher-level cache memory and the main memory. The main memory can be placed in the self-refresh mode responsive to the supplemental cache memory being selectively activated. The supplemental cache memory can be implemented with a highly- or fully-associative cache memory that is smaller than the higher-level cache memory. Thus, the supplemental cache memory can handle those cache misses by the higher-level cache memory that arise because too many memory blocks are mapped to a single cache line. In this manner, a DRAM implementation of the main memory can be kept in the self-refresh mode for longer time periods.

Abstract: A storage system with temperature control. The system includes a plurality of storage devices such as solid state drives, a system controller such as a baseboard management controller, and one or more cooling fans. Each storage devices includes a controller configured to estimate the heat load in the storage device and/or an effective temperature, resulting from operations performed in the storage device. The system controller employs active disturbance rejection control to adjust the fan speed based on the estimated heat loads, the estimated temperatures, and/or the sensed internal temperatures, of the storage devices.

Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

Abstract: A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.

Abstract: Described herein are a method and apparatus for memory vulnerability prediction. A memory vulnerability predictor predicts the reliability of a memory region when it is first accessed, based on past program history. The memory vulnerability predictor uses a table to store reliability predictions and predicts reliability needs of a new memory region. A memory management module uses the reliability information to make decisions, (such as to guide memory placement policies in a heterogeneous memory system).

Abstract: In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to generate prefetch requests to prefetch data into the mid-level cache; and a prefetcher selector to select a prefetcher configuration for the first prefetcher and the second prefetcher based on at least one memory access metric, wherein the prefetcher configuration is to specify whether the first prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of a particular page and whether the second prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of the particular page.

Abstract: In some embodiments, a memory initialization detection process includes detecting a read instruction of a program, where the read instruction addresses a particular memory location, and where data corresponding to the particular memory location is cached in a particular cache line of a memory cache. The memory initialization detection process further includes determining, based on metadata stored in the memory cache, that a section of the particular cache line does not store valid data of the program. The memory initialization detection process further includes obtaining validity data from the section of the particular cache line. The memory initialization detection process further includes determining, based on the validity data, whether the read instruction is authorized to proceed.

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

Abstract: A method and system for prefetching instructions is disclosed. A signature may be updated in response to determining that a received instruction initiates a transition in function. A plurality of entries stored in a memory may be searched in response to determining the signature has been updated and a prefetch operation may be initiated in response to determining that the signature matches a given entry of the plurality of entries.

Abstract: Technologies for protocol execution include a command device to broadcast a protocol message to a plurality of computing devices and receive an aggregated status message from an aggregation system. The aggregated status message identifies a success or failure of execution of instructions corresponding with the protocol message by the plurality of computing devices such that each computing device of the plurality of computing devices that failed is uniquely identified and the success of remaining computing devices is aggregated into a single success identifier.

Abstract: A method for caching reads in a data replication environment is disclosed. In one embodiment, such a method includes receiving a read request at a primary site of a data replication environment. The method executes the read request at the primary site. In the event data associated with the read request is not already cached at the primary site, the method stores the data in cache at the primary site. The method also notifies a secondary site of the read request at the primary site. This notification may be sent synchronously or asynchronously as time and resources allow. In the event the data is not already cached at the secondary site, the method stores the data in cache at the secondary site. A corresponding system and computer program product are also disclosed.

Abstract: An embodiment of a memory apparatus may include a tag cache to cache tag information, and a memory controller communicatively coupled to the tag cache to determine if a request for a memory line results in a tag cache miss, bring tag information for the missed memory line into the tag cache if the request results in a cache miss, and bring tag information for at least one additional memory line adjacent to the missed memory line into the tag cache if the request results in a cache miss. Additional embodiments are disclosed and claimed.

Abstract: Systems and methods are disclosed to abort a command at a data storage controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a data storage controller configured to receive an abort indicator from a host device, generate an abort tracking indicator at a receiving unit configured to receive commands from the host device, monitor to determine when the selected command is received at the receiving unit based on the abort tracking indicator, and abort the selected command when the selected command is received at the receiving unit. In some embodiments, the data storage controller may generate an abort tracking indicator at a completion unit configured to notify the host device of completed commands, and monitor for the selected command at the completion unit based on the abort tracking indicator.

Abstract: Techniques for retrieving data blocks from memory devices are provided. In one aspect, a request to retrieve a block of data may be received. The block of data may be in a line in a rank of memory. The rank of memory may include multiple devices. The devices used to store the line in the rank of memory may be determined. The determined devices may be read.

Abstract: An enhanced FTL system and method are provided for eliminating redundant write operations. A method is disclosed, including: processing a data write operation from a host that deploys a journaling scheme, wherein the data write operation includes a specified LBA that maps to a PBA in a SSD memory; calculating a signature of a data block during a write operation; detecting whether the data write should be handled as journal or non-journal write operation without assistance from the host; in response to a detected journal write operation, allocating a new PBA, writing the data block to the new PBA, updating a mapping table with a new LBA-PBA mapping, and inserting the signature into a signature table for the new LBA-PBA mapping; and in response to a detected non-journal write operation, mapping the specified LBA to an existing PBA if the signature matches a stored signature in the mapping table.

Abstract: A method includes monitoring a request rate of speculative memory read requests from a penultimate-level cache to a main memory. The speculative memory read requests correspond to data read requests that missed in the penultimate-level cache. A hit rate of searches of a last-level cache for data requested by the data read requests is monitored. Core demand speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding core demand data read request based on the request rate and the hit rate. Prefetch speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding prefetch data read request based on the request rate and the hit rate.

Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

Abstract: Disclosed herein are techniques for pre-processing a multiple-channel image for compression. The multiple-channel image can be composed of a collection of pixels that are represented using a floating-point format (e.g., half-precision/16-bit) for display on devices optimized for wide-gamut color space. The techniques can include a first step of quantizing the pixels into a fixed range of values, and applying invertible color-space transformations to the sub-pixels of each pixel—which can include red, green, blue, and alpha sub-pixels—to produce transformed sub-pixels including luma and chroma values. Next, the luma sub-pixels are placed into a luma data stream, the first and second chroma values are placed into a chroma data stream, and the alpha sub-pixels are placed into an alpha data stream. Predictive functions are then applied to the luma and chroma data streams. Finally, the various streams are separated into buffers and compressed to produce a multiple-channel image.

Abstract: A cache control device for content delivery, includes: an interface module to communicate with a cache device and a content server; a storage module to store a service list in which service types of respective content servers are recorded; and a control module to identify the content server from at least one of (i) a content request message received from the interface module and requesting content and (ii) a content response message received from the interface module and delivering the content, determine a service type of the content server with reference to the service list stored in the storage module, and perform control so that an indicator indicating the determined service type is transmitted to the cache device through the interface module.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. External system memory is used as a last-level cache and includes one of a variety of types of dynamic random access memory (DRAM). A memory controller generates a tag request and a separate data request based on a same, single received memory request. The sending of the tag request is prioritized over sending the data request. A partial tag comparison is performed during processing of the tag request. If a tag miss is detected for the partial tag comparison, then the data request is cancelled, and the memory request is sent to main memory. If one or more tag hits are detected for the partial tag comparison, then processing of the data request is dependent upon the result of the full tag comparison.

Abstract: A processor includes a hierarchical cache memory having a higher-order cache memory and a lower-order cache memory. The hierarchical cache memory is in an inclusive state in which data stored in the higher-order cache memory is included in the lower-order cache memory. The processor also includes a cache hit determination unit configured to determine a cache hit/miss with respect to the higher-order cache memory and the lower-order cache memory at the time of accessing predetermined data, and a control unit configured to perform control to realize the inclusive state, based on the determination results of the cache hit/miss with respect to the higher-order cache memory and the lower-order cache memory.

Abstract: A memory system has a first memory to store first-granularity data having a granularity smaller than second-granularity data, the first memory having a memory capacity smaller than a memory capacity of a second memory storing the second-granularity data, a controller to read third-granularity data having a granularity equal to or greater than the first-granularity from the data stored in the second memory, and a data extractor to extract the first-granularity data from the third-granularity data read by the controller and to store the extracted data in the first memory.

Abstract: Systems and methods for management of a computer-based cache are provided. A system can include a processor, a cache, a memory device, and a storage device. The processor can be configured to evict a page from the cache to a history index based upon a greater weight respectively assigned to a least frequently used (LFU) and least recently used policy (LRU) policy, detect a requested page that was evicted to the history index, and adjust the respective weights assigned to the policies based upon the requested page being in the history index.

Abstract: In an example embodiment, one or more pages from a database are stored in a page cache stored in a shared memory, the one or more pages stored in a packed format. One or more rows from the database are stored in a row cache stored in the shared memory, the one or more rows stored in an unpacked format. A request for a row of the database is received. Then, the row cache is searched for the row. In response to a determination that the row cannot be found in the row cache, the page cache is searched for the row. Finally, the row is returned.

Abstract: An arithmetic processing device includes clusters, each including cores and a last level cache shared by the cores; a home agent connected to the last level caches; and a memory controller connected to the home agent to control accesses to a memory. In response to a memory request from a first last level cache in a first cluster, the home agent issues a first replace request to the first last level cache to evict a first victim line in the first last level cache, the home agent issues a second replace request to a second last level cache in a second cluster in an idle state other than the first cluster to evict a second victim line in the second last level cache, and the second last level cache fills data of the first victim line to the second victim line.

Abstract: The claimed invention discloses system comprising a plurality of logical nodes comprised in a single or plurality of stages, with defined properties and resources associated with each node, for reducing compute resources, said system further comprising: at least a recirculating ring buffer holding only any one of a control information, input, and, or out data necessary to stream a temporary data between node and, or nodes in an execution graph, thereby reducing size of said recirculating ring buffer; said recirculating ring buffer being sufficiently reduced in size to reside in an on-chip cache, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory; wherein the control information further comprises a command related to invalidating any one of the input and, or out data held in a recirculating ring data buffer, clearing the buffer of tasked data; and wherein a producer is stalled from writing any more control information into a recirculati

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an “Owned” state and a Forward state together with protocol mechanism for handling various memory requests.

Abstract: A system includes one or more processor cores and a cache hierarchy. The cache hierarchy includes a first-level cache, a second-level cache, and a third-level cache. The cache hierarchy further includes cache hierarchy control logic configured to implement a caching policy in which each cacheline cached in the first-level cache has a copy of the cacheline cached in at least one of the second-level cache and the third-level cache. The caching policy further provides that an eviction of a cacheline from the second-level cache does not trigger an eviction of a copy of that cacheline from the first-level cache, and that an eviction of a cacheline from the third-level cache triggers the cache hierarchy control logic to evict a copy of that cacheline from the first-level cache when the cacheline is not present in the second-level cache.

Abstract: A method and an apparatus for performing task-level cache management in an electronic device are provided. The method may be applied to a processing circuit of the electronic device, and may include: before a task of a plurality of tasks runs on a processor core, performing at least one checking operation on the task to generate at least one checking result, wherein the at least one checking result indicates whether the task is a risky task with risk of evicting cached data of an urgent task from a cache, and the cache is dedicated to a set of processor cores including the processor core; and according to the at least one checking result, determining whether to temporarily limit cache access permission of the processor core during a time period in which the task runs on the processor core, for preventing cache eviction of the cache due to the task.

Abstract: Various aspects include methods for implementing retaining high locality data in a higher level cache memory on a computing device. Various aspects may include receiving a cache access request for a first cache line in the higher level cache memory indicating a locality of the first cache line, determining whether the access request indicates high locality, and setting a high locality indicator of the first cache line in response to determining that the cache access request indicates high locality. Various aspects may include determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold, setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter exceeds the lower level cache locality threshold and resetting the lower level cache memory hit counter of the first cache.

Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

Abstract: Systems and methods associated with page modification are disclosed. One example method may be embodied on a non-transitory computer-readable medium storing computer-executable instructions. The instructions, when executed by a computer, may cause the computer to fetch a page to a buffer pool in a memory. The page may be fetched from at least one of a log and a backup using single page recovery. The instructions may also cause the computer to store a modification of the page to the log. The modification may be stored to the log as a log entry. The instructions may also cause the computer to evict the page from memory when the page is replaced in the buffer pool. Page writes associated with the eviction may be elided.

Abstract: Systems and methods for improved process caching through iterative feedback are disclosed. In embodiments, a computer implemented method comprises retrieving updated metadata of a process to be executed, wherein the updated metadata includes information regarding cache misses from a prior execution of the process; automatically modifying a setting of a data stream control register based on the updated metadata; automatically setting a hint at a data cache block touch module; performing an initial execution of the process after the steps of retrieving the updated metadata, automatically modifying the setting of the data stream control register, and automatically setting the hint at the data cache block touch module; and modifying the updated metadata of the process after the execution of the process based on cache miss statistical data gathered during the execution of the process, to produce newly updated metadata.

Abstract: An event-driven-cache service receives a request from a client to establish a cache. In response, the event-driven-cache service registers a cache function in an event-driven compute service and defines events that trigger the cache function in the event-driven compute service. The event-driven compute service receives a request to get data from or set data to the cache. In response to the request, the event-driven compute service sends event information to a selected container and the container launches the cache function. For a set request, the cache function adds data to a dedicated persistent storage of the container. For a get request, the cache function determines whether requested data is valid in the dedicated persistent storage and returns the data or a miss indication to the client. Upon completion of the request, the container terminates the cache function and the data remains in the dedicated persistent storage of the container.

Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die, a local memory connected to (or part of) the controller and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations. When the memory system receives instructions to use the compute engine to perform data manipulation operations, the local memory is reallocated such that an amount of space allocated in the local memory for logical to physical translation information is changed based on the one or more data manipulation instructions.

Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.

Abstract: A namespace is provided in a file system that employs logical volumes. With the namespace, the file system can withstand data storage units going offline without compromising accessibility of the files in the data storage units that remain online. The files in the online data storage units remain accessible through the use of path lookup tables that are stored in the online data storage units.

Abstract: Systems and methods which provide a modular processor framework and instruction set architecture designed to efficiently execute applications whose memory access patterns are irregular or non-unit stride are disclosed. A hybrid multithreading framework (HMTF) of embodiments provides a framework for constructing tightly coupled, chip-multithreading (CMT) processors that contain specific features well-suited to hiding latency to main memory and executing highly concurrent applications. The HMTF of embodiments includes an instruction set designed specifically to exploit the high degree of parallelism and concurrency control mechanisms present in the HMTF hardware modules. The instruction format implemented by a HMTF of embodiments is designed to give the architecture, the runtime libraries, and/or the application ultimate control over how and when concurrency between thread cache units is initiated.

Abstract: A memory system has a first memory to be accessed per first data size, a second memory to be accessed per second data size smaller than the first data size, the second memory being accessible at a higher speed than the first memory; and a third memory to store address conversion information that converts an address for accessing the second memory into an address for accessing the first memory. The first and third memories are non-volatile memories.

Abstract: Embodiments include techniques for receiving a cacheline of data, hashing the cacheline into a plurality of chunks, wherein each chunk includes a pattern of bits, storing the plurality of chunks in a pattern table, wherein the plurality of chunks are indexed in the pattern table based on the pattern of bits of each chunk, and identifying a repeated pattern of bits of the plurality of chunks and selecting the repeated pattern of bits as candidate pattern. Techniques include comparing a threshold number of bits of the candidate pattern to the pattern of bits of the plurality of chunks in the pattern table; based on the comparison, inserting valid bits and a tag into the pattern table for the candidate pattern by replacing bits in the candidate pattern, and writing the candidate pattern, including the valid bits and the tag, into a location of the memory corresponding to the candidate pattern.

Abstract: A multi-core processor supporting cache consistency, a method and apparatus for data writing, and a method and apparatus for memory allocation, as well as a system by use thereof. The multi-core processor supporting cache consistency includes a plurality of cores, the plurality of cores corresponding to respective local caches. A local cache of a core of the plurality of cores is responsible for caching data in a different range of addresses in a memory space and a core of the plurality of cores accesses data in a local cache of another core of the plurality of core via an interconnect bus.

Abstract: The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device.