Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

Abstract: Techniques related to a server-side extension of client-side caches are provided. A storage server computer receives, from a database server computer, an eviction notification indicating that a data block has been evicted from the database server computer's cache. The storage server computer comprises a memory hierarchy including a volatile cache and a persistent cache. Upon receiving the eviction notification, the storage server computer retrieves the data block from the persistent cache and stores it in the volatile cache. When the storage server computer receives, from the database server computer, a request for the data block, the storage server computer retrieves the data block from the volatile cache. Furthermore, the storage server computer sends the data block to the database server computer, thereby causing the data block to be stored in the database server computer's cache. Still further, the storage server computer evicts the data block from the volatile cache.

Abstract: Techniques and apparatuses are described that enable power-conserving cache memory usage. Main memory constructed using, e.g., DRAM can be placed in a low-power mode, such as a self-refresh mode, for longer time periods using the described techniques and apparatuses. A hierarchical memory system includes a supplemental cache memory operatively coupled between a higher-level cache memory and the main memory. The main memory can be placed in the self-refresh mode responsive to the supplemental cache memory being selectively activated. The supplemental cache memory can be implemented with a highly- or fully-associative cache memory that is smaller than the higher-level cache memory. Thus, the supplemental cache memory can handle those cache misses by the higher-level cache memory that arise because too many memory blocks are mapped to a single cache line. In this manner, a DRAM implementation of the main memory can be kept in the self-refresh mode for longer time periods.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Abstract: A method, computer system, and a computer program product for execution of a stateless service on a node in a workload execution environment is provided. The present invention may include defining for each node a workload container including a cache component of a cache-mesh. The present invention may include, upon receiving a state request from a stateless requesting service from one of the cache components of the cache-mesh in an execution container, determining whether a requested state is present in the cache component of a related execution container. The present invention may include, upon a cache miss, broadcasting the state request to other cache components of the cache-mesh, determining, by the other cache components, whether the requested state is present in respective caches, and upon any cache component identifying the requested state, sending the requested state to the requesting service using a protocol for communication.

Abstract: A computing device's trusted platform module (TPM) is configured with a cryptographic watchdog timer which forces a device reset if the TPM fails to solve a cryptographic challenge before the expiration of the timer. The computing device's TPM is configured to generate the cryptographic challenge, to which the computing device does not possess the cryptographic token for resolution. While the watchdog timer counts down, the computing device requests a cryptographic token from a remote service to solve the challenge. The remote service transmits the cryptographic token to the computing device so long as the remote service identifies no reason to withhold the token, such as the computing device being infected with malware. The interoperability of the computing device and remote service enables the remote service to exercise control and reset capabilities over the computing device.

Abstract: A method for accessing a memory of a multi-core system, a related apparatus, a system, and a storage medium involve obtaining data from a system memory according to a prefetch instruction, and sending a message to a core that carries the to-be-accessed data. Each segment of data is stored in an intra-core cache based on the prefetch instruction.

Abstract: A massively parallel database management system includes an index store and a payload store including a set of storage systems of different temperatures. Both the stores each include a list of clusters. Each cluster includes a set of nodes with storage devices forming a group of segments. Nodes and clusters are connected over high speed links. The list of clusters within the payload store includes clusters of different temperatures. The payload store transitions data of a segment group from a higher temperature to a segment group in a lower temperature cluster in parallel. A node moves data of a segment in the higher temperature cluster to a corresponding node's segment in the lower temperature cluster. Once the data is written in the destination segment in the lower temperature cluster, the source segment is freed to store other data. The temperatures include blazing, hot, warm and cold.

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

Abstract: A method for moving data includes identifying, by a staging manager in a container, a trigger condition associated with data being used by an application external to the container, performing an analysis on the trigger condition, making a first determination, based on the analysis, that the trigger condition is satisfied, and processing, based on the first determination, a data movement action.

Abstract: Described herein are technologies directed to lazy lock queue reduction in computing clusters. The disclosed lazy lock queue reduction techniques can be performed in preparation for cluster group changes. Prior to a cluster group change operation, such as a merge or a split of a node with a group, a notification of a planned group change operation can be sent to the nodes of a group. In response to the notification, the nodes of the group can perform lazy lock queue reduction techniques disclosed herein. In one disclosed lazy lock queue reduction technique, a node can set a drain goal for a lazy lock queue, and the node can drain the lazy lock queue according to the drain goal. In another disclosed lazy lock queue reduction technique, a node can set an age limit for lazy lock queue entries, and the node can remove lazy lock queue entries which are expired or over the age limit.

Abstract: A cache system includes a cache memory having a plurality of blocks, a dirty line list storing status information of a predetermined number of dirty lines among dirty lines in the plurality of blocks, and a cache controller controlling a data caching operation of the cache memory and providing statuses and variation of statuses of the dirty lines, according to the data caching operation, to the dirty line list. The cache controller performs a control operation to always store status information of a least-recently-used (LRU) dirty line into a predetermined storage location of the dirty line list.

Abstract: The disclosure herein pertains to a security vulnerability scanner. The security vulnerability scanner parses a URL into a network portion and a fragment portion. The security vulnerability scanner then runs the URL on a network-side browser to generate processed results. Advantageously, the security vulnerability scanner is able to mimic a client side browser by running various fragment portions in order to analyze security risks.

Abstract: The technology described in this document can be embodied in an integrated circuit device comprises a first data processing unit comprising one or more input ports for receiving incoming data, one or more inter-unit data links that couple the first data processing unit to one or more other data processing units, a first ingress management module connected to the one or more inter-unit data links, the first ingress management module configured to store the incoming data, and forward the stored data to the one or more inter-unit data links as multiple data packets, and a first ingress processing module. The integrated circuit device also comprises a second data processing unit comprising one or more output ports for transmitting outgoing data, and a second ingress management module connected to the one or more inter-unit data links.

Abstract: A fabric controller is provided for a coherent accelerator fabric. The coherent accelerator fabric includes a host interconnect, a memory interconnect, and an accelerator interconnect. The host interconnect communicatively couples to a host device. The memory interconnect communicatively couples to an accelerator memory. The accelerator interconnect communicatively couples to an accelerator having a last-level cache (LLC). An LLC controller is provided that is configured to provide a bias check for memory access operations on the fabric.

Abstract: Techniques herein accelerate graph querying by caching neighbor vertices (NVs) of super-node vertices. In an embodiment, a computer receives a graph query (GQ) to extract result paths from a graph in a database. The GQ has a sequence of query vertices (QVs) and a sequence of query edges (QEs). The computer successively traverses each QE and QV to detect paths of the graph that match the GQ. Traversing each QE and QV entails retrieving NVs of a current graph vertex (CGV) of a current traversal path. If the CGV is a key in a cache whose keys are graph vertices having an excessive degree, then the computer retrieves NVs from the cache. Otherwise, the computer retrieves NVs from the database. If the degree is excessive, and the CGV is not a key in the cache, then the computer stores, into the cache, the CGV as a key for the NVs.

Abstract: Techniques are disclosed relating to filtering cache accesses. In some embodiments, a control unit is configured to, in response to a request to process a set of data, determine a size of a portion of the set of data to be handled using a cache. In some embodiments, the control unit is configured to determine filtering parameters indicative of a set of addresses corresponding to the determined size. In some embodiments, the control unit is configured to process one or more access requests for the set of data based on the determined filter parameters, including: using the cache to process one or more access requests having addresses in the set of addresses and bypassing the cache to access a backing memory directly, for access requests having addresses that are not in the set of addresses. The disclosed techniques may reduce average memory bandwidth or peak memory bandwidth.

Abstract: Disclosed herein are computer-implemented methods; computer-implemented systems; and non-transitory, computer-readable media, for sending cross-chain messages. One computer-implemented method includes storing, through consensus of blockchain nodes of a first blockchain network, an authenticable message (AM) associated with a first account to a blockchain associated with the first blockchain network, where the AM comprises an identifier of the first blockchain network, information of the first account, information of a recipient of the AM, and content of the AM. The AM and location information is transmitted to a relay to be forwarded to the recipient located outside of the first blockchain network, where the location information identifies a location of the AM in the blockchain and the recipient includes one or more accounts outside of the first blockchain network.

Abstract: Techniques for filesystem management for cloud object storage are described. In one embodiment, a method includes writing, by a filesystem layer, a plurality of entries to a log structured file tree, including filesystem metadata and filesystem data. The method includes performing a flush operation of the entries from the filesystem layer to one or more objects in a distributed cloud object storage layer. The method includes storing the filesystem metadata and the filesystem data to the one or more objects in the distributed cloud object storage layer. The method further includes storing flush metadata generated during each flush operation, including a flush sequence number associated with each flush operation. Each object of the one or more objects in the distributed cloud object storage layer is identified by a key that identifies the flush sequence number, an object identifier, and a rebirth identifier.

Abstract: Memory devices including a controller for access of an array of memory cells that is configured to accept a sequence of commands to cause the memory device to read a first set of data from the array of memory cells into a first register, load the first set of data into a first portion of a second register, write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, read the set of test data from the second portion of the second register during the reading of the second set of data, and output the set of test data from the memory device during the reading of the second set of data.

Abstract: A processing unit includes a plurality of processing elements and one or more caches. A first thread executes a program that includes one or more prefetch instructions to prefetch information into a first cache. Prefetching is selectively enabled when executing the first thread on a first processing element dependent upon whether one or more second threads previously executed the program on the first processing element. The first thread is then dispatched to execute the program on the first processing element. In some cases, a dispatcher receives the first thread four dispatching to the first processing element. The dispatcher modifies the prefetch instruction to disable prefetching into the first cache in response to the one or more second threads having previously executed the program on the first processing element.

Abstract: A router device may receive a request for access to a file from a user device, wherein a master version of the file is stored in a data structure associated with a server device. The router device may generate, based on the request, a copy of a cached version of the file, wherein the cached version of the file is stored in a data structure associated with the router device. The router device may send the copy of the cached version of the file to the user device.

Abstract: A storage device includes a nonvolatile memory device that includes a plurality of pages, each of which includes a plurality of memory cells, and a controller that receives first write data expressed by 2m states (m being an integer greater than 1) from an external host device. The controller in a first operating mode shapes the first write data to second write data, which are expressed by “k” states (k being an integer greater than 2) smaller in number than the 2m states, performs first error correction encoding on the second write data to generate third write data expressed by the “k” states, and transmits the third write data to the nonvolatile memory device for writing at a selected page from the plurality of pages.

Abstract: A hybrid cache memory and a method for controlling the same are provided. The method for controlling a cache includes: receiving a request for data; determining whether the requested data is present in a first portion of the cache, a second portion of cache, or not in the cache, wherein the first portion of cache has a smaller access latency than the second portion of cache; loading the requested data from a memory of a next level into the first portion of the cache and the second portion of the cache if the requested data is not in the cache, and retrieving the requested data from the first portion of the cache; and retrieving the requested data from the first portion of the cache or the second portion of the cache without writing data to the second portion of the cache if the requested data is in the cache.

Abstract: A processor system includes a processor core, a cache, a cache controller, and a cache assist controller. The processor core issues a read/write command for reading data from or writing data to a memory. The processor core also outputs an address range specifying addresses for which the cache assist controller can return zero fill, e.g., an address range for the read/write command. The cache controller transmits a cache request to the cache assist controller based on the read/write command. The cache assist controller receives the address range output by the processor core and compares the address range to the cache request. If a memory address in the cache request falls within the address range, the cache assist controller returns a string of zeroes, rather than fetching and returning data stored at the memory address.

Abstract: A processor includes a page table walk cache that stores address translation information, and a page table walker. The page table walker fetches first output addresses indicated by first indexes of a first input address by looking up the address translation information and at least a part of page tables, and compares a matching level between second indexes of a second input address and the first indexes of the first input address with a walk cache hit level obtained by looking up the page table walk cache using the second indexes.

Abstract: There is disclosed in an example a peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space. The PCIe controller may include extensions to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space. The extensions may include: a mapping engine to provide opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI, a tunneling engine to provide scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI, host-bias-to-device-bias (HBDB) flip engine to enable the accelerator to flush a host cache line, and a QoS engine comprising a plurality of virtual channels.

Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

Abstract: An apparatus and method for a speculative conditional move instruction. A processor comprising: a decoder to decode a first speculative conditional move instruction; a prediction storage to store prediction data related to previously executed speculative conditional move instructions; and execution circuitry to read first prediction data associated with the speculative conditional move instruction and to execute the speculative conditional move instruction either speculatively or non-speculatively based on the first prediction data.

Abstract: Techniques for replicating virtual machine data is provided. A plurality of compute nodes running on a primary cluster determine the amount of virtual machine data cached within each compute node. Based on the amount of virtual machine data for a particular virtual machine, a particular compute node is assigned to replicate the data to a secondary cluster. The amount of particular virtual machine data copied to the secondary cluster is based on updated virtual machine data that belongs to a particular state of the virtual machine. The destination of the particular virtual machine data is based on available cache space and prior replication statistics for target compute nodes on the secondary cluster.

Abstract: A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.

Abstract: Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.

Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

Abstract: An upper level cache receives from an associated processor core a plurality of memory access requests including at least first and second memory access requests of differing first and second classes. Based on class histories associated with the first and second classes of memory access requests, the upper level cache initiates, on the system interconnect fabric, a first interconnect transaction corresponding to the first memory access request without first issuing the first memory access request to the lower level cache via a private communication channel between the upper level cache and the lower level cache.

Abstract: Mechanisms for reducing register bank conflicts based on software hint and hardware thread switch are disclosed. In some embodiments, an apparatus for thread switching includes a graphics processing unit (GPU) that includes a plurality of register banks to store operands that are assigned at least partially to avoid register bank conflicts. Decoding circuitry checks a thread switching field of a first instruction to be executed by a first thread. The GPU performs a thread switch mechanism to cause a second instruction to be executed by a second thread when the thread switching field of the first instruction is set.

Abstract: A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.

Abstract: Provided are a computer program product, system, and method for staging data from storage to a fast cache tier of a multi-tier cache in a non-adaptive sector caching mode in which data staged in response to a read request is limited to track sectors required to satisfy the read request. Data is also staged from storage to a slow cache tier of the multi-tier cache in a selected adaptive caching mode of a plurality of adaptive caching modes available for staging data of tracks. Adaptive caching modes are selected for the slow cache tier as a function of historical access ratios. Prestage requests for the slow cache tier are enqueued in one of a plurality of prestage request queues of various priority levels as a function of the selected adaptive caching mode and historical access ratios. Other aspects and advantages are provided, depending upon the particular application.

Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.

Abstract: Aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for use in receiving devices employing at least one iterative process for decoding messages. In certain example aspects, a receiving device may comprise a user equipment (UE) or other like device that may be configured to support device-to-device (D2D) communications, such as vehicle-to-vehicle (V2V) communications, or the like.

Abstract: A memory system implements any combination of zero or more cache eviction policies, zero or more cache prefetch policies, and zero or more virtual address modification policies. A memory allocation technique implements parameter receiving and processing in accordance with the cache eviction policies, the cache prefetch policies, and the virtual address modification policies. A compiler system optionally processes any combination of zero or more indicators of extended data types usable to indicate one or more of the cache eviction policies, the cache prefetch policies, and/or the virtual address modification policies to associate with a variable, an array of variables, and/or a section of memory. The indicators comprise any combination of zero or more compiler flags, zero or more compiler switches, and/or zero or more pseudo-keywords in source code.

Abstract: Embodiments of the invention are directed to methods for improving performance of a multi-core processor. A non-limiting method includes increasing a first operating frequency to a first elevated operating frequency of a first core of a gang of cores, the gang of cores comprising a plurality of cores of the multi-core processor. The method further includes upon a determination that an operating temperature of the first core is above a threshold temperature, switching processing of a thread from the first core to a second core in the gang of cores. The method further includes reducing the first operating frequency of the first core. The method further includes increasing the operating frequency of the second core to a second elevated operating frequency.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

Abstract: A semiconductor memory device may include a memory cell array; and a cache latch circuit that exchanges data with the memory cell array through a plurality of bit lines extended in a second direction crossing a first direction. The memory cell array may include a plurality of cache latches arranged in a plurality of columns in the first direction and in a plurality of rows in the second direction. Each of the cache latches may be coupled to any one of a plurality of input/output (IO) pins. Cache latches coupled to the IO pins at the same time may constitute one IO cache latch unit. The cache latches included in the one IO cache latch unit may be arranged in 2×2 array units.

Abstract: Embodiments are provided for deferring allocation of storage for segments. The method includes receiving, at a first moment in time, a request to allocate a first segment within a memory. Information corresponding to the first segment is stored in a first entry in a hash table, and memory is allocated for the first segment. Information about the first segment is returned to an entity that requested the allocation of the first segment, where the first segment is not allocated auxiliary storage until predefined criteria are satisfied. At a second moment in time, upon receiving an indication to deallocate the first segment, memory corresponding to the first segment is deallocated, where the first segment is never allocated auxiliary storage and the first entry in the hash table is deleted.

Abstract: A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.

Abstract: Systems, apparatuses, and methods for maintaining separate pending load and store counters are disclosed herein. In one embodiment, a system includes at least one execution unit, a memory subsystem, and a pair of counters for each thread of execution. In one embodiment, the system implements a software based approach for managing dependencies between instructions. In one embodiment, the execution unit(s) maintains counters to support the software-based approach for managing dependencies between instructions. The execution unit(s) are configured to execute instructions that are used to manage the dependencies during run-time. In one embodiment, the execution unit(s) execute wait instructions to wait until a given counter is equal to a specified value before continuing to execute the instruction sequence.

Abstract: An example method of managing persistent memory (PM) in a computing system includes: issuing, by an application executing in the computing system, store instructions to an address space of the application, the address space including a region mapped to the PM; recording, by a central processing unit (CPU) in the computing system, cache line addresses in a log, the cache line addresses corresponding to cache lines in the address space of the application targeted by the store instructions; and issuing, by the application, one or more instructions to flush cache lines from cache of the CPU identified by the cache line addresses in the log.

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate a packed data register of the plurality of packed data registers that is to store a source packed memory address information. The source packed memory address information is to include a plurality of memory address information data elements. An execution unit is coupled with the decode unit and the plurality of packed data registers, the execution unit, in response to the instruction, is to load a plurality of data elements from a plurality of memory addresses that are each to correspond to a different one of the plurality of memory address information data elements, and store the plurality of loaded data elements in a destination storage location. The destination storage location does not include a register of the plurality of packed data registers.

Abstract: According to embodiments described herein, the hierarchical complexity for coherence protocols associated with clustered cache architectures can be encapsulated in a simple function, i.e., that of determining when a data block is shared entirely within a cluster (i.e., a sub-tree of the hierarchy) and is private from the outside. This allows embodiments to eliminate complex recursive coherence operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through but which are restricted to operate where a data block is shared. Thus embodiments recognize that, in the context of clustered cache hierarchies, data can be shared entirely within one cluster but can be private (unshared) to this cluster when viewed from the perspective of other clusters. This characteristic of the data can be determined and then used to locally simplify coherence protocols.