Abstract: A computer-implemented method, according to one approach, includes: receiving an I/O request which includes supplemental information pertaining to an anticipated workload of the I/O request. The supplemental information is used to determine whether to satisfy the I/O request using a primary cache. In response to determining to satisfy the I/O request using the primary cache, the I/O request is initiated using the primary cache, and performance characteristics experienced by the primary cache while satisfying the I/O request are evaluated. The supplemental information and the performance characteristics are further used to determine whether to satisfy a remainder of the I/O request using the secondary cache. In response to determining to satisfy a remainder of the I/O request using the secondary cache, the I/O request is demoted from the primary cache to the secondary cache, and a remainder of the I/O request is satisfied using the secondary cache.

Abstract: A method of implementing a multi-threaded device driver for a computer system is disclosed. A polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread.

Abstract: Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative is disclosed. The updating of at least one cache state in the cache memory resulting from a data request is deferred until the data request becomes non-speculative. Thus, a cache state in the cache memory is not updated for requests resulting from mispredictions. Deferring the updating of a cache state in the cache memory can include deferring the storing of received speculative requested data in the main data array of the cache memory as a result of a cache miss until the data request becomes non-speculative. The received speculative requested data can first be stored in a speculative buffer memory associated with a cache memory, and then stored in the main data array if the data request becomes non-speculative.

Abstract: Systems and methods for operating a robotic surgical system are provided. The system includes a surgical tool, a manipulator comprising links for controlling the tool, a navigation system comprising a tracker coupled to the manipulator or the tool and a localizer to monitor a state of the tracker. Controller(s) determine a raw (or lightly filtered) relationship between one or more components of the manipulator and one or more components of the navigation system by utilizing one or more of raw kinematic measurement data from the manipulator and raw navigation data from the navigation system. The controller(s) utilize the raw (or lightly filtered) relationship to determine whether an error has occurred relating to at least one of the manipulator and the navigation system.

Abstract: In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: In a network device, a hash-based lookup system includes a hash generator configured to apply respective hash functions to a lookup key to generate respective hash values. Each hash function corresponds to a respective logical hash bank in a hash table. A number of hash values generated by the hash generator corresponds to the number of logical hash banks in the hash table, and the number of hash values generated by the hash generator is configurable. The hash-based lookup system also includes an address generator that is configured to generate respective addresses to a memory that stores the hash table, the respective addresses within respective address spaces of respective logical hash banks of the hash table. The address generator uses i) a parameter N that specifies the number of logical hash banks in the hash table, and ii) N hash values generated by the hash generator, to generate the respective addresses.

Abstract: Content-aware systems and methods for improving de-duplication, or single instancing, in storage operations. In certain examples, backup agents on client devices parse application-specific data to identify data objects that are candidates for de-duplication. The backup agents can then insert markers or other indictors in the data that identify the location(s) of the particular data objects. Such markers can, in turn, assist a de-duplication manager to perform object-based de-duplication and increase the likelihood that like blocks within the data are identified and single instanced. In other examples, the agents can further determine if a data object of one file type can or should be single-instanced with a data object of a different file type. Such processing of data on the client side can provide for more efficient storage and back-end processing.

Abstract: An apparatus and method are provided for managing a cache hierarchy. The apparatus has processing circuitry for executing instructions, and a cache hierarchy for storing content for access by the processing circuitry when executing those instructions. The cache hierarchy has a plurality of levels of cache including a highest level of cache that is accessed prior to the other levels of cache in response to a request from the processing circuitry. Eviction control circuitry is provided in association with each level of cache, and the eviction control circuitry associated with a chosen level of cache in arranged to implement a most recently read eviction policy that causes content most recently read from the chosen level of cache to be selected for eviction from that chosen level of cache. It has been found that such an approach can significantly increase the effective cache capacity within the cache hierarchy, without the complexities often associated with other schemes.

Abstract: Disclosed herein is an apparatus which comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units.

Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, write and read commands from a client device are placed into a command queue pending servicing to transfer data between the client device and a non-volatile memory (NVM). A write cache temporarily stores sets of writeback data pending transfer. A cache manager detects an overlap condition in which a subsequently received command at least partially overlaps a pending write command. In response, the cache manager enacts a change in caching policy that includes retention of the cached writeback data to aid in the servicing of the subsequently received command. The changes in caching policy can include an increase in the size of the write cache, delays in the writing of hot writeback data sets, the coalescing of different writeback data sets, cache hits using the cached writeback data, etc.

Abstract: In exemplary aspects of managing the ejection of entries of a coherence directory cache, the directory cache includes directory cache entries that can store copies of respective directory entries from a coherency directory. Each of the directory cache entries is configured to include state and ownership information of respective memory blocks. Information is stored, which indicates if memory blocks are in an active state within a memory region of a memory. A request is received and includes a memory address of a first memory block. Based on the memory address in the request, a cache hit in the directory cache is detected. The request is determined to be a request to change the state of the first memory block to an invalid state. The ejection of a directory cache entry corresponding to the first memory block is managed based on ejection policy rules.

Abstract: Disclosed is an operating method of a semiconductor device, including acquiring resource information on a plurality of hardware resources, receiving a compression request or a decompression request for data, acquiring context information on the semiconductor device, in response to receiving the compression request or the decompression request for the data, selecting a compression algorithm for compressing or decompressing the data, based on the context information, selecting, among the plurality of hardware resources, a hardware resource for performing the selected compression algorithm, based on the acquired resource information, and compressing or decompressing the data using the selected compression algorithm and the selected hardware resource.

Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

Abstract: A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. The cache controller then transfers the data with the status tag indicating the higher level cache location to a lower level cache. When the data is subsequently updated or evicted from the lower level cache, the cache controller reads the status tag location information and transfers the data back to the location in the higher level cache from which it was originally transferred.

Abstract: Non-volatile Memory Express over Fabric (NVMeOF) using Volume Management Device (VMD) schemes and associated methods, systems and software. The schemes are implemented in a data center environment including compute resources in compute drawers and storage resources residing in pooled storage drawers that are communicatively couple via a fabric. Compute resources are composed as compute nodes or virtual machines/containers running on compute nodes to utilize remote storage devices in pooled storage drawers, while exposing the remote storage devices as local NVMe storage devices to software running on the compute nodes. This is facilitated by virtualizing the system's storage infrastructure through use of hardware-based components, firmware-based components, or a combination of hardware/firmware- and software-based components. The schemes support the use of remote NVMe storage devices using an NVMeOF protocol and/or use of non-NVMe storage devices using NVMe emulation.

Abstract: Computing device and method for inferring a predicted number of physical blocks erased from a flash memory. The computing device stores a predictive model generated by a neural network training engine. A processing unit of the computing device executes a neural network inference engine, using the predictive model for inferring the predicted number of physical blocks erased from the flash memory based on inputs. The inputs comprise a total number of physical blocks previously erased from the flash memory, an amount of data to be written on the flash memory, and optionally an operating temperature of the flash memory. In a particular aspect, the flash memory is comprised in the computing device, and an action may be taken for preserving a lifespan of the flash memory based at least on the predicted number of physical blocks erased from the flash memory.

Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

Abstract: In one aspect of storage device status management in accordance with the present description, a host can determine not only whether a particular volume maintained by a storage unit controlled by a storage controller is on-line with respect to another host, but also whether that volume is actually in use by another host. Accordingly, should one host determine that a volume is in use by another host, the one host can defer its use of the volume until the volume is no longer in use by another host. In this manner, conflicts which may lead to loss of data integrity may be reduced or eliminated, providing a significant improvement in computer technology. Other features and aspects may be realized, depending upon the particular application.

Abstract: In accordance with an embodiment, described herein is a system and method for use of lock-less data structures and processes with a multidimensional database computing environment. Lock-less algorithms or processes can be implemented with specific hardware-level instructions so as to provide atomicity. A memory stores an index cache retaining a plurality of index pages of the multidimensional database. A hash table indexes index pages in the index cache, wherein the hash table is accessible by a plurality of threads in parallel through application of the lock-less process.

Abstract: This disclosure provides a method for tagging control information associated with a physical address in a processing system, including setting a hardware tag for the control information, the hardware tag being invisible to a software system in the processing system; joining the hardware tag with the physical address to form a compound physical address, the hardware tag including M bits carried by a dedicated hardware tag control line, the physical address including N bits carried by a physical address bus, M and N being positive integers; and tagging the control information with the hardware tag in the compound physical address.

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.

Abstract: Techniques for configuring and operating a multimedia aware cloud, particularly configured for mobile device computing, are described herein. In some instances, clusters of servers are organized for general computing, graphic computing and data storage. A load balancing server may be configured to: identify multimedia types currently being processed within the multimedia edge cloud; determine desired quality of service levels for each identified multimedia type; evaluate individual abilities of devices communicating with the multimedia edge cloud; and assess bandwidth of each network over which the multimedia edge cloud communicates with a mobile device. With that information, multimedia data may be adapted accordingly, to result in an acceptable quality of service level when delivered to a specific mobile device. In one example of the techniques, graphic computing server clusters may be configured to process workload using a configuration that includes elements of both parallel and serial computing.

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.

Abstract: Aspects of the disclosure provide a network device. The network device includes a search engine, a ternary content addressable memory (TCAM) cache engine, a search key generation unit and an output controller. The search engine stores a lookup table of entries for rules of packet processing, and searches the lookup table in response to packets received from a network interface of the network device. The TCAM cache engine caches a subset of the entries in the lookup table based on hit statistics of the entries. The search key generation unit generates a search key based on a received packet and provides the search key to the search engine and to the TCAM cache engine. The output controller outputs a search result from the TCAM cache engine when the TCAM cache engine has a matching entry to the search key.

Abstract: A memory access system includes a memory, a controller, and a redundancy elimination unit. The memory is a multi-way set associative memory, and the redundancy elimination unit records M record items. Each record item is used to store a tag of a stored data block in one of storage sets. The controller determines a read data block and a target storage set of the read data block and sends a query message to the redundancy elimination unit. The query message carries a set identifier of the target storage set of the read data block and a tag of the read data block. The redundancy elimination unit determines a record item corresponding to the set identifier of the target storage set, matches the tag of the read data block with a tag of a stored data block in the record item corresponding to the target storage set of the read data block.

Abstract: Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.

Abstract: One embodiment provides for a general-purpose graphics processing unit multiple processing elements having a single instruction, multiple thread (SIMT) architecture, the multiple processing elements to perform hardware multithreading during execution of multiple warps of threads, wherein a warp is a group of parallel threads; a scheduler to schedule a set of sub-warps to the multiple processing elements at sub-warp granularity, wherein a sub-warp is a sub-group of parallel threads, a warp includes multiple sub-warps, and the scheduler is to schedule threads in a first sub-warp of a first warp of threads to execute concurrently with the threads in a second sub-warp of a second warp of threads; and a logic unit including hardware or firmware logic, the logic unit to group active threads for execution on the multiple processing elements.

Abstract: Disclosed herein are methods, systems, and processes to select storage tiers for data replication and data recovery. A replication stream is received from a replication appliance that is configured to replicate data to a storage tier of multiple storage tiers. Each storage tier differs from at least one other storage tier in at least one storage characteristic. Portions of the replication stream are identified based on input/output (I/O) characteristics. The portions are stored in one storage tier other than the storage tier based on the I/O characteristics, and a storage cost associated with each storage tier, where the storage cost associated with each storage tier is based on storage characteristics of each storage tier.

Abstract: One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores cache blocks that at least partially include a subset of cache blocks stored by near memory circuitry. The near memory circuitry is configured in an n-way set associative format that references the cache blocks stored by the near memory circuitry using set identifiers and way identifiers. The cache management circuitry stores way identifiers for the cache blocks of the near memory circuitry within the cache blocks in the last level cache circuitry. Storing way identifiers in the cache blocks of the last level cache enables the cache management circuitry or memory controller circuitry to write back a cache block without reading tags in one or more ways of the near memory circuitry.

Abstract: Examples of the present disclosure provide apparatuses and methods related to a translation lookaside buffer in memory. An example method comprises receiving a command including a virtual address from a host translating the virtual address to a physical address on volatile memory of a memory device using a translation lookaside buffer (TLB).

Abstract: A multiprocessor device includes cores and at least one ingress-write ordering circuitry (IWOC) including first and second counters associated with first and second destinations. The IWOC is configured to assign sequential numbers to write transactions received from a source, according to an order of reception at the IWOC, and to forward the write transactions from the IWOC to the first and second write-transaction destinations, while preserving the order, by incrementing the first and second counters such that both the first counter and the second counter track a sequential number of a next write transaction that the IWOC will forward, forwarding a first write transaction to the first destination only provided that the sequential number of the first write transaction matches the first counter, and forwarding a second write transaction to the second destination only provided that the sequential number of the second write transaction matches the second counter.

Abstract: Disclosed herein are techniques associated with a Direct Memory Access (DMA) engine that can include a data generation module. The DMA engine can receive, from a processing entity, a particular type of write command with an indicator to write a data pattern to an address. Upon receipt of the particular type of write command, the DMA engine can generate, using a data generation module of the DMA engine, the data pattern to be written to the address. The processing entity can be Central Processing Unit (CPU) including a core configured to process serial commands. The DMA engine can be disposed on a same die as a processing entity or a network interface port.

Abstract: A method for operating a database and a cache of at least a portion of the database may include receiving a plurality of read requests to read a data entity from the database and counting respective quantities of the requests serviced from the database and from the cache. The method may further include receiving a write request to alter the data entity in the database and determining whether to update the cache to reflect the alteration to the data entity in the write request according to the quantity of the requests serviced from the database and the quantity of the requests serviced from the cache. In an embodiment, the method further includes causing the cache to be updated when a ratio of the quantity of the requests serviced from the database to the quantity of the requests serviced from the cache exceeds a predetermined threshold.

Abstract: Storage circuitry comprises an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of two or more entries of the row buffer. The comparison circuitry identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.

Abstract: A processor employs a hierarchical register file for a graphics processing unit (GPU). A top level of the hierarchical register file is stored at a local memory of the GPU (e.g., a memory on the same integrated circuit die as the GPU). Lower levels of the hierarchical register file are stored at a different, larger memory, such as a remote memory located on a different die than the GPU. A register file control module monitors the status of in-flight wavefronts at the GPU, and in particular whether each in-flight wavefront is active, predicted to be become active, or inactive. The register file control module places execution data for active and predicted-active wavefronts in the top level of the hierarchical register file and places execution data for inactive wavefronts at lower levels of the hierarchical register file.

Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.

Abstract: In a memory controller, a prefetch indication can be sent to memory to prepare the memory for a potential future read or write. Statistics can be used to select when such a prefetch should occur. The prefetch can occur without any read or write command being commenced. As a result, the memory controller predicts when to perform the prefetch. Some examples of when a prefetch can be sent include when there are other requests for the same memory page, or how often the page is requested. The page can remain open to prevent it from closing until the relevant read or write arrives. In the case that a read or write does not occur after a predetermined period of time, then a precharge can be performed to release the memory page.

Abstract: The system includes a data synchronization module and a heat data module. The data synchronization module is configured to communicate with a first storage volume and a second storage volume to provide a backup for the first storage volume by synchronizing information from the first storage volume to the second storage volume. The information includes at least one of data chunks, heat map data, and first metadata relating to the first storage volume. The heat data module is coupled to the second storage volume to read the first metadata and the heat map data and adjust a location of at least one of the data chunks in the second storage volume based on the heat map data.

Abstract: Techniques for dynamically altering weights to re-weight attributes of an ordering model based on feedback in a streaming environment are described. In an embodiment, a system accesses, based on a candidate stream definition comprising a role including a title, one or more stream-related information sources, and extracts attributes from the sources. Additionally, the system inputs the attributes to a combined ordering model that is trained by a machine learning algorithm to output ordering scores for member profiles of an online system (e.g., hosting a social networking service). The combined ordering model includes weights assigned to the attributes. Moreover, the system orders, based on the ordering scores, the profiles. Furthermore, the system presents, on a display, of top-ordered profiles. Then, the system accesses feedback regarding the top-ordered profiles and dynamically trains the weights assigned to each of the attributes to alter the weights assigned to the attributes based on the feedback.

Abstract: Various embodiments of the present invention relate to an apparatus and a method for managing memory in an electronic device. The electronic device comprises a volatile memory, a non-volatile memory and a processor, wherein the processor is configured to store first data and second data, stored in a first specified area of the volatile memory, in a second specified area of the volatile memory, to check the stored order of the first data and the second data stored in the second specified area, and to move at least one of the first data and the second data from the second specified area of the volatile memory to a third specified area of the non-volatile memory if the states of the first data and the second data satisfy a specified condition on the basis of the order. Other embodiments may be possible.

Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Abstract: Embodiment of a storage stack are disclosed whereby increased performance and other technical improvements are achieved by an application requesting access (e.g., asynchronously) to an address, returning a buffer, and the application issuing a buffer release when the operation is complete.

Abstract: The present invention relates to a hybrid memory system with live page migration for virtual machine, and the system comprises a physical machine installed with a virtual machine and being configured to: build a channel for a shared memory between the virtual machine and a hypervisor; make the hypervisor generate to-be-migrated cold/hot page information and writing write the to-be-migrated cold/hot page information into the shared memory; make the virtual machine read the to-be-migrated cold/hot page information from the shared memory; and make the virtual machine according to the read to-be-migrated cold/hot page information perform a page migration process across heterogeneous memories of the virtual machine without stopping the virtual machine.

Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

Abstract: Apparatuses and method for an integrated circuit device are described. In an apparatus thereof, there is a plurality of memory controllers coupled to a plurality of memory banks. A network of switches is coupled to the plurality of memory controllers. A plurality of data processing devices is coupled to the network of switches and is configured to generate memory requests. A network controller is coupled to the network of switches and is configured to queue the memory requests and selectively issue requests to memory from the memory requests queued responsive to corresponding response times associated with the plurality of memory banks.

Abstract: Disclosed embodiments relate to a system with configurable cache sub-domains and cross-die memory coherency. In one example, a system includes R racks, each rack housing N nodes, each node incorporating D dies, each die containing C cores and a die shadow tag, each core including P pipelines and a core shadow tag, each pipelines associated with a data cache and data cache tags and being either non-coherent or coherent and one of X coherency domains, wherein each pipeline, when needing to read a cache line, issues a read request to its associated data cache, then, if need be, issues a read request to its associated core-level cache, then, if need be, issues a read request to its associated die-level cache, then, if need be, issues a no-cache remote read request to a target die being mapped to hold the cache line.

Abstract: A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.