Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: A method of passing message data from a first device to a second device in a software defined radio (SDR) apparatus. A shared memory is defined in the apparatus for access by either one of the first and the second devices. A priority message originating from one of the devices and destined to the other device is loaded into a buffer of the shared memory, and the address of the buffer is passed to the other device. The message in the buffer of the shared memory is then accessed directly from the other device.

Abstract: A system, method and computer program product for booting a computer system from the backup and working with the backup as if it were a normal storage device, including loading an initialization application to run in a single thread mode and that identifies a storage media with the backup that includes boot blocks; installing and activating a handler of a Basic Input/Output System (BIOS) interrupt module, for intercepting boot loader requests to the storage media, and for redirecting them to the backup; creating a bitmap of the data blocks stored in the backup and of a writable data storage device to which new data will be written; initiating the BIOS to load and execute the boot blocks from the backup; transferring control to a routine defined by a boot record stored in the backup's boot blocks; installing and activating an I/O filter for intercepting the requests to the writable data storage device, and after a write request is received, the I/O filter writes a corresponding data block to the writable data

Abstract: A plural-partitioned type nonvolatile storage device which solves the problem that a memory card composed of a flash memory and a controller, when a storage area is divided into a plurality of partitions, cannot be correctly used with a conventional host apparatus incapable of recognizing plural partitions. The memory card includes, as its storage areas, a device characteristic data storage area, a division table storage area, and a device storage area, where the device storage area is partitioned into plural partitions. The memory card can have different modes for adapting different accesses from the external host, and allows the external host to access partitions corresponding to the mode. Division information as to a dividing method for the plural partitions, and access information as to the host-accessible partitions corresponding to each individual mode are stored in the division table storage area.

Abstract: A method and apparatus are provided in a computing environment for scheduling access to a resource. The method grants access to the resource by a non-real-time request when the non-real-time request can be completed before the latest possible start time at which a first real-time request must start service to timely complete all actual and anticipated real-time requests, otherwise granting the first real real-time request access to the resource.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: Copy pair monitoring is provided for a storage system having plural host computers, at least one storage subsystem, and a management computer. The storage subsystem including volumes storing data requested by the host computer, the management computer being accessible to the host computer and the storage subsystem. The copy pair monitoring includes obtaining every piece of copy pair definition information that is stored in the host computer, removing duplicate copy pair definition information from the whole copy pair definition information obtained, and collecting the copy pair status based on the obtained copy pair definition information from which duplicate copy pair definition information has been removed. Each host computer is assigned a priority level, and, when more than one host computer includes the same copy pair, the host computer with the lowest priority obtains the copy pair information to reduce the load on the higher priority host computers.

Abstract: A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.

Abstract: A memory access controller including a command analysis unit to receive write access request and command data and to analyze access to a memory, a command execution unit to output command and data control signals to the memory based on write data, and the analysis result, a mode setting unit to switch between a first operation mode in which a write access request is issued when both the command data and the corresponding write data are available, and a second operation mode in which a write access request is issued when the command data is available independently of availability of the write data corresponding to the command data, and a timing arbitration unit provided for each bus master to output the write access request and command data to the command analysis unit and output the write data to the command execution unit in accordance with the mode setting unit.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: Various embodiments of the invention relate to an apparatus and a method of managing a snapshot storage pool (SSP) associated with a storage unit of a distributed data storage system. According to some embodiments of the invention, the apparatus may include a logic module and a processor. The logic module may be adapted to provide a threshold corresponding to a ratio between a current amount of storage resources used for storing snapshots in the SSP and a total storage capacity defined for the SSP. The processor may be adapted to trigger an action that may be effective for managing the SSP in response to the amount of storage resources used for storing snapshots in the SSP crossing the threshold.

Abstract: A memory management method for a non-volatile memory and a controller using the same are provided. The non-volatile memory is substantially divided into a plurality of blocks. First, non-erasing information of a plurality of memory units comprising at least one block is recoded and used as a reference to establish an evaluation value. Then, whether to move data of at least one block on the memory units to another memory unit according to the evaluation value is determined. Accordingly, problems of read disturb and data retention due to excessive reading times can be resolved.

Abstract: A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device.

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract: A system for processing routing according to priorities of logical interfaces is provided. The system includes a priority setting unit for setting priorities of a plurality of logical interfaces set in a physical interface, and a priority scheduler for determining a priority of a respective logical interface from an input frame, and for outputting the input frame to a driver queue of the physical interface when the input frame is output from a logical interface having the highest priority. Traffic burstiness caused by queuing can be reduced in a network routing system employing at least one logical interface.

Abstract: A method is provided for a first logical processor to determine a running status of a target logical processor of an information processing system. In such method, an instruction is issued by the first logical processor running on the information processing system for determining whether the target logical processor is running. In response to issuing the instruction, a state descriptor belonging to the target logical processor is queried to determine whether the target logical processor is currently running. A result is then returned to the first logical processor, the result indicating whether or not the target logical processor is currently running.

Abstract: A Common System Storage Repository replaces all the different system support storages distributed across a server system topology transparent to various subsystems by providing a central non-volatile repository for all the different system data. Each of the various subsystems communicate with the Common System Storage Repository via the individual system support storage interfaces.

Abstract: A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism.

Abstract: A device and a method to efficiently process the symbols coded in OFDM according to the various protocols available. This is achieved through a device to process OFDM-based symbols comprising a base band input data and a base band output data, and comprising at least two programmable execution units connected to at least one working memory, this device being characterized in that, the programmable execution units (EU) are connected to the memory (M-1, M-2, M3, . . .

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: The device comprises a memory (3) for storing several user share parameters and several amounts capable of advancing. A decision means (6) allocates a chosen service slice of the resource to a user selected as possessing the least advanced amount. It subsequently advances his amount according to a chosen increment. A memory link means (5) defines user queues of “FIFO” type, such that the user having the least advanced amount in a queue appears at the head of this queue. According to the invention, the memory (3) stores a limited number of values of increments. The memory link means (5) associates one of these values of increments with each user and allocates an increment value to each queue.

Abstract: A method for providing quality of service to a plurality of hosts accessing a common resource is described. The common resource may be a middle-tier or back-end server. A client IO request is received at one host of the plurality of hosts from one of a plurality clients executing as software entities on respective hosts. The host determines whether an issue queue is full. The IO request is issued to the common resource when the issue queue is not full. A current average latency observed at the host and an adjusted window size is calculated, based at least in part on the current average latency. The issue queue is resized to correspond with the adjusted window size.

Abstract: Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.

Abstract: A conflict avoidance system is provided. The conflict avoidance system comprises a first data store provided at a first geographic location and a second data store at a second geographic location, where the first and second data stores are replications of one another. The conflict avoidance system also comprises a conflict avoidance module operable to receive a data store request from applications, wherein the conflict avoidance module communicates update data store requests to the first data store and communicates create data store requests and delete data store requests to the second data store.

Abstract: A method, circuit arrangement, and design structure utilize a lock prediction data structure to control ownership of a cache line in a shared memory computing system. In a first node among the plurality of nodes, lock prediction data in a hardware-based lock prediction data structure for a cache line associated with a first memory request is updated in response to that first memory request, wherein at least a portion of the lock prediction data is predictive of whether the cache line is associated with a release operation. The lock prediction data is then accessed in response to a second memory request associated with the cache line and issued by a second node and a determination is made as to whether to transfer ownership of the cache line from the first node to the second node based at least in part on the accessed lock prediction data.

Abstract: An optic module is disclosed having a memory configured to store data. To selectively control access to the memory and data stored in memory, a method and apparatus for memory access control is provided which creates access levels. The access levels include associated passwords, and read/write capability control, and address access range. During use a technician or other party would enter a password via an interface and the entered password is compared to the password associated with each access level. If a match is not found, then access to the memory, a hence data within the memory is denied. If a match is found the technician gains access to the data stored in the memory address range associated with the access level. Read and write access may also be granted or denied.

Abstract: Unsecure system software and secure system software on the same computer system is switched between. A computer system includes one or more processors, which may not have any built-in security features, memory, and firmware. The memory stores secure system software and unsecure system software. In response to receiving a user signal, the firmware switches from the unsecure system software running on the processors to the secure system software running on the processors (and back again). While the unsecure system software is running, the secure system software is protected from tampering by the unsecure system software.

Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.

Abstract: A system and method for controlling access to a computer provides for loose security within a local network while retaining strong security against external access to the network. In one embodiment, a user has access to trusted nodes in a secured group within an unmanaged network, without being required to choose, enter and remember a login password. To establish such a secure blank password or one-click logon account for the user on a computer, a strong random password is generated and stored, and the account is designated as a blank password account. If the device is part of a secured network group, the strong random password is replicated to the other trusted nodes. When a user with a blank password account wishes to log in to a computer, the stored strong random password is retrieved and the user is authenticated.

Abstract: Systems and methods are provided to manage access to computing resources. More specifically, certain embodiments are described in which a resource or resource consumer can engage access controls or request that access controls be engaged if the age of a request exceeds one or more thresholds. For example, a requester may, after the age of a request meets or exceeds a threshold, indicate to a destination that a control should be engaged.

Abstract: Provided is a data storage device. The data storage device includes an interface, a buffer controller, a memory controller, a non-volatile memory, and a self-powered semiconductor device adjacent to and electrically connected to the buffer controller. The self-powered semiconductor device includes a semiconductor chip and a rechargeable micro-battery attached to the semiconductor chip. The rechargeable micro-battery includes a first current collector and a second current collector, which face each other, a first polarizing electrode in contact with the first current collector and facing the second current collector, a second polarizing electrode in contact with the second current collector and facing the first polarizing electrode, and an electrolyte layer formed between the first and second polarizing electrodes.

Abstract: A system and method for dynamic redistribution of parity groups is described. The system and method for dynamic redistribution of parity groups operates on a computer storage system that includes a plurality of disk drives for storing parity groups. Each parity group includes storage blocks. The storage blocks include one or more data blocks and a parity block that is associated with the data blocks. Each of the storage blocks is stored on a separate disk drive such that no two storage blocks from a given parity set reside on the same disk drive. The computer system further includes a redistribution module to dynamically redistribute parity groups by combining some parity groups to improve storage efficiency.

Abstract: A method, system, and medium are provided for managing cache allocation between a primary storage and a secondary storage. The system includes a device with a primary storage, secondary storage, and cache manager. The method includes downloading a web resource, storing the web resource in the primary storage, determining the amount of time required to download the web resource, and determining the amount of time required to retrieve the web resource from the secondary storage. If the amount of time required to retrieve the web resource from the secondary storage is less than the amount of time required to download the web resource, the method stores the web resource in the secondary storage. Additionally, web resources may be moved from the secondary storage to the primary storage based on their likelihood of being utilized.

Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.

Abstract: In order to provide HSM that can effectively use the storage capacity of an upper Tier in an HSM system, a lower Tier of the HSM system detects a group of files having the same data content from a plurality of files stored in the lower Tier, and keeps at least one of the real data of the group of files having the same data content while deleting the rest of the data. The upper Tier receives the process result from the lower Tier. Then, in response to a read request from the host computer that specifies a file included in the group of files and transferred to the upper Tier from the lower Tier, the upper Tier identifies the at least one of the data that is kept and corresponding to the specified file, and responds to the host computer.

Abstract: A method of validating a digital certificate comprises retrieving from a first data store a digital certificate, retrieving from a second data store a plurality of certificate revocation lists (CRLs), and selecting one of the plurality of CRLs to validate the digital certificate as of a date which is before the current date.

Abstract: An allocation control apparatus may access an address table storing addresses of slice areas allocated in a storage area for an entire storage system having a plurality of storage devices and addresses that do not correspond to allocated slice areas. The allocation control apparatus includes a reception unit receiving a request for allocating an arbitrary storage capacity an allocation unit allocating, by referring to the address table, an address that does not correspond to the allocated slice area for at least a part of the requested storage capacity and allocates an address for the slice area to the remaining storage capacity when the reception unit receives the allocation request, and a transmission unit transmitting the result allocated by the allocation unit to a requesting source of the allocation request.

Abstract: A device having a shared memory and a shared memory controlling method are disclosed. A digital processing device can include a shared memory, having a storage area including at least one common section, coupled to each of the processors through separate buses and outputting access information to whether a processor is accessing a common section. With the present invention, each processor can efficiently use or/and control a shared memory by using access information.

Abstract: A storage system maintains consistency of the stored contents between volumes even when a plurality of remote copying operations are executed asynchronously. A plurality of primary storage control devices and a plurality of secondary storage control devices are connected by a plurality of paths, and remote copying is performed asynchronously between respective first volumes and second volumes. Write data transferred from the primary storage control device to the secondary storage control device is held in a write data storage portion. Update order information, including write times and sequential numbers, is managed by update order information management portions. An update control portion collects update order information from each update order information management portion, determines the time at which update of each second volume is possible, and notifies each-update portion. By this means, the stored contents of each second volume can be updated up to the time at which update is possible.

Abstract: Provided is a copy pair monitoring method which is for a storage system having at least one host computer, at least one storage subsystem, and a management computer, the storage subsystem including volumes storing data requested by the host computer to be written, the management computer being accessible to the host computer and the storage subsystem. The copy pair monitoring method is characterized by including the steps of: obtaining every piece of copy pair definition information that is stored in the host computer; removing duplicate copy pair definition information from the whole copy pair definition information obtained; and collecting the copy pair status based on the obtained copy pair definition information from which duplicate copy pair definition information has been removed.

Abstract: A system and method for providing roaming access on a network are disclosed. The network includes a plurality of wireless and/or wired access points. A user may access the network by using client software on a client computer (e.g., a portable computing device) to initiate an access procedure. In response, a network management device operated by a network provider may return an activation response message to the client. The client may send the user's username and password to the network provider. The network provider may rely on a roaming partner, another network provider with whom the user subscribes for internet access, for authentication of the user. Industry-standard methods such as RADIUS, CHAP, or EAP may be used for authentication. The providers may exchange pricing and service information and account information for the authentication session. A customer may select a pricing and service option from a list of available options.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.

Abstract: In a separating device that separates a processor configured to perform process by using data recorded in a cache memory connected to the processor, a stopping unit, upon receiving a processor separation request, stops the processor from performing a new process; and a separation executing unit, upon completion of process being performed by the processor, separates the processor after invalidating the data recorded in the cache memory.

Abstract: In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.

Abstract: A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism.

Abstract: A playback apparatus which plays back video or music contents, includes: a playback unit playing back the video or music contents recorded on a recording medium; an output unit outputting the video or music contents played back in the playback unit; and a control unit controlling at least an operation of the playback unit, wherein in the video or music contents, a quick reference mark is set at multiple places, in response to user manipulation, the control unit finds a start of a sequence in accordance with the quick reference mark to control the operation of the playback unit to play back the video or music contents, in response to user manipulation for the quick reference, the control unit varies a priority that expresses a degree served for the quick reference, and for the mark having a low priority, the control unit accepts no user manipulation for quick reference.

Abstract: Interrupts and code threads are assigned in a particular way to the core CPUs of a network file server in order to reduce latency for processing client requests for file access. Threads of the network stack are incorporated into real time threads that are scheduled by a real-time scheduler and executed exclusively by a plurality of the core CPUs that are not interrupted by disk adapter interrupts so that the disk adapter interrupts do not interrupt execution of the network stack. Instances of a storage access driver are hard affinity threads, and soft affinity threads include a multitude of instances of a thread of the file system stack for file access request processing so that file access request processing for a multitude of concurrent file access requests is load balanced over the core CPUs.

Abstract: LAN-managed storage volumes are managed by a LAN storage manager installed on a storage management server. In processing a LAN-free storage volume request, the LAN tape manager selects a LAN-managed storage volume responsive to the LAN-free storage volume allocation request wherein the LAN-managed storage volume is initialized as a candidate for a LAN-free storage operation. The LAN-managed storage volume may be initialized by the LAN storage manager as a candidate for a LAN-free storage operation prior to the LAN storage manager receiving the LAN-free storage volume allocation request or in response to the LAN storage manager receiving the LAN-free storage volume allocation request. Additionally, prior to being initialized as a candidate for a LAN-free storage operation, the LAN-managed storage volume may be a pre-existing storage volume or a scratch storage volume.

Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.