Abstract: A memory card system and memory card. The memory card system may include a host and a memory card able to be received by the host. The memory card may transfer an application program index to the host in response to a command from the host. Time spent finding information relating to the application programs loaded in the memory card may be saved and a convenient and efficient interface may be provided to a user.

Abstract: Media distribution systems may include methods and apparatus to perform memory management on a wireless devices configured to receive non-real time portions of media services. Such methods and apparatus may be based upon an allowable capacity of presentations storable in device memory, as well as on a required memory associated with each presentation in a media service. Such methods and apparatus allow a device to subscribe to a media service based upon sufficient available memory in the device to support the service.

Abstract: A data processing method using a data processing apparatus on a transmitting side having an application for performing processing using an internal device set in the data processing apparatus, a driver that accepts an access request to the internal device from the application, a handler that performs access processing to the internal device and transmitting a message to an external device set outside the data processing apparatus, and a storage device that stores a device ID as a transmission destination for specifying the internal or external device and the handler in association with each other, and a data processing apparatus on a receiving side that receives the message transmitted from the data processing apparatus on the transmitting side.

Abstract: An apparatus includes a programmable device that has an interface and command ports that can each receive commands, each command requesting an information transfer through the interface. A technique relating to the device involves: selecting during field programming a number of priority definitions; configuring each of the priority definitions during field programming to specify an order of priority for a group of the command ports; and using the priority definitions in succession and, for each of the priority definitions, causing a command to be accepted from the command port of highest priority that contains a command.

Abstract: Recording control with additional information superposed on data and recording control in response to a type of a recording medium on which data are recorded are disclosed. A recording apparatus for recording data onto a recording medium includes an identification data detection section for detecting identification data for identification of data from the data, a copying count data detection section for detecting copying count data for limiting the number of times of copying the data from the data, and a recording control section for controlling recording of the data onto the recording medium based on the identification data detected by the identification data detection section and the copying count data detected by the copying count data detection section.

Abstract: A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message.

Abstract: A priority control register 104 dynamically controls the internal transition state based on the issuability state of a memory request obtained in the memory request issuability signal generation unit 106 and retaining state of the memory request in the REQ_BUF 102 obtained by each of determination circuits 105 #2 through #5. Thus, the jump control of the priorities corresponding to the access regulation of the DRAM module 109 can be realized.

Abstract: In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to t

Abstract: A method of controlling a shared memory and a user terminal controlling the operation of the shared memory are disclosed. The portable terminal according to an embodiment of the present invention has a memory unit with a storage area partitioned to blocks in a quantity of n and a plurality of processors reading or writing data by accessing a partitioned block. At least one of the partitioned blocks is assigned as a common storage area, accessible by a processor having an access privilege, and the processor having the access privilege performs an operation of maintaining the data stored in the common storage area. With the present invention, the common storage area can be accessed by a plurality of processors, and thus the data transmission time between the processors can be minimized.

Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.

Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.

Abstract: A memory access control apparatus includes a plurality of memory access request generating modules and an arbitrator. When one of the memory access request generating modules receives a second memory access event while a memory device is performing a first memory access operation according to a first memory access request in response to a first memory access event, the memory access request generating module outputs a second memory access request corresponding to the second memory access event to the memory device after a delay time. The arbitrator is implemented for arbitrating memory access requests respectively outputted from the memory accessing request generating modules.

Abstract: A number of coherence domains are maintained among the multitude of processing cores disposed in a microprocessor. A cache coherency manager defines the coherency relationships such that coherence traffic flows only among the processing cores that are defined as having a coherency relationship. The data defining the coherency relationships between the processing cores is optionally stored in a programmable register. For each source of a coherent request, the processing core targets of the request are identified in the programmable register. In response to a coherent request, an intervention message is forwarded only to the cores that are defined to be in the same coherence domain as the requesting core. If a cache hit occurs in response to a coherent read request and the coherence state of the cache line resulting in the hit satisfies a condition, the requested data is made available to the requesting core from that cache line.

Abstract: In one embodiment, a processor is configured to operate in a first mode in which privilege level protection is disabled and paging is enabled. In another embodiment, a method is contemplated including intercepting a write to a control register by a guest executing in a processor; determining that the write attempts to establish a first mode in the processor in which privilege level protection is disabled and paging is disabled; and causing the guest to execute in a second mode in which privilege level protection is disabled and paging is enabled instead of the first mode. A computer accessible medium comprising instruction implementing at least a portion of the method is also described.

Abstract: Read commands on a mirrored memory computer system are scheduled by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory system. The conflict queue determines a predicted latency on each memory port based on the contents of each of the read/write queues. A compare logic unit is coupled to the conflict queue, wherein the compare logic unit compares a predicted latency of a primary memory and a mirrored memory and schedules read commands to the memory port with the lowest predicted latency.

Abstract: Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Abstract: Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.

Abstract: Methods and apparatuses for processing input and/or output requests for data storage devices are disclosed. Method embodiments generally comprise receiving a number of requests, wherein at least one of the requests is an isochronous request having an initial deadline value, calculating a new deadline value for the isochronous request, and issuing the isochronous request when the new deadline value is less than a threshold value. Apparatus embodiments generally comprise a request receiver to receive a number input or output requests, a logic module to calculate a deadline value for an isochronous request, where the calculated deadline value relates to the amount of time which has transpired between the creation of the isochronous request and the time the calculation is made, and an issuance module to issue the isochronous request if the calculated deadline value is equal or less than a threshold value.

Abstract: The invention provides a technology applicable to technologies other than a main frame technology and monitors data recovery available time while suppressing a monitoring error within a certain range in a storage system that performs Asynchronous Remote Copy among storage devices. A management computer in the storage system stores latest or quasi-latest management data corresponding to data staying in a buffer of the first storage device with temporal information at certain monitoring intervals, calculates an estimated value of the data recovery available time which is time of data stored in the second storage device corresponding to data stored in the first storage device, based on the temporal information stored, and based on a certain management data among earliest or quasi-earliest management data or a number of the data staying in the buffer at the certain time and displays the estimated value on a display section.

Abstract: Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple independently-addressable memory banks, and one location per bank can be accessed in parallel. Parallel processing engines executing the threads generate a group of parallel memory access requests. Address conflict logic determines whether the requests can be satisfied in parallel (e.g., based on bank access constraints) and serializes the requests to the extent needed to avoid conflicts. In some embodiments, data read from one address in the shared memory can be broadcast to multiple processing engines.

Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.

Abstract: Included are embodiments for a method for servicing memory read requests. At least one embodiment of a method includes receiving read requests from the I/O device; testing predetermined fields from the read requests to predict a type of read request; and when the type of request is predicted to be a data read request, then route the read request to a first queue. Additionally, some embodiments include when the type of request is predicted to be a control read request, then route the read request to a second queue, wherein the second queue has a higher priority than the first queue; determining which of the first queue and second queue to read; retrieving at least one of the read requests from the determined queue; and processing the retrieved read request.

Abstract: A method and a host processing device are provided for background formatting, or de-icing, an optical medium with no de-icing assistance from an optical drive upon which the optical medium is mounted. In a foreground mode, an optical medium may be initially formatted, volume structures may be recorded on the optical medium, file system information may be written thereto, and quick grow formatting may be performed to make the optical medium writable, at least sequentially. Under initiation and control of a file system, executing on a host processing device, the optical medium may be formatted, or de-iced, in a background mode with no assistance from an optical drive, upon which the optical medium is mounted. Under control of the file system, blocked input or output activity, may be allowed to access the optical medium upon pausing the formatting, or de-icing.

Abstract: The present invention provides an apparatus and method that increases the utilization by processors on shared resources. It provides the minimum latency in a multiprocessor system during usage right exchange between multi-processors on a shared resource. The apparatus provides a timed mailbox including a timer. The timed mailbox is at least associated with a first processor and a second processor. The second processor starts to utilize a shared resource to perform a task. According to a predetermined clock cycle number, the timed mailbox issues a signal in advance to notify the first processor of the availability of the shared resource to be utilized by the first processor.

Abstract: A storage device for storing data sent from a host apparatus comprises a plurality of processors sending to a cache memory controller an access instruction relating to transmission of the data, based on an access request relating to the transmission of the data, the access request being sent from the host apparatus; and an access instruction sending unit exclusively sending to the cache memory the access instruction sent from the plurality of processors, wherein the access instruction sending unit includes a plurality of storage units for storing an access instruction which requires a response, and wherein when the access instruction which requires a response is stored in all of the storage units, the access instruction sending unit sends only an access instruction which requires a response to the cache memory controller.

Abstract: A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.

Abstract: Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t?[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.

Abstract: The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access.

Abstract: In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.

Abstract: Some aspects include reception of a command from one of a chassis management module and a BIOS specifying a data region to be updated and a locking policy, determination of whether the data region is locked, implementation of the locking policy and returning of a session lock handle if it is determined that the data region is not locked, reception, from the one of the chassis management module and the BIOS, of data for updating the data region, the session lock handle, and an offset, determination that the session lock handle is associated with the data region, writing of the data to the data region at the offset, reception of a request for data of the updated data region from the other one of the chassis management module and the BIOS, determination of whether the updated data region is locked, and if it is determined that the updated data region is not locked, providing of the data of the updated data region to the other one of the chassis management module and the BIOS.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: Provided is a copy pair monitoring method which is for a storage system having at least one host computer, at least one storage subsystem, and a management computer, the storage subsystem including volumes storing data requested by the host computer to be written, the management computer being accessible to the host computer and the storage subsystem. The copy pair monitoring method is characterized by including the steps of: obtaining every piece of copy pair definition information that is stored in the host computer; removing duplicate copy pair definition information from the whole copy pair definition information obtained; and collecting the copy pair status based on the obtained copy pair definition information from which duplicate copy pair definition information has been removed.

Abstract: File system disaster recovery techniques provide automated monitoring, failure detection and multi-step failover from a primary designated target to one of a designated group of secondary designated targets. Secondary designated targets may be prioritized so that failover occurs in a prescribed sequence. Replication of information between the primary designated target and the secondary designated targets allows failover in a manner that maximizes continuity of operation. In addition, user-specified actions may be initiated on failure detection and/or on failover operations and/or on failback operations.

Abstract: A method, and corresponding system and software, is described for writing data to a plurality of queues, each portion of the data being written to a corresponding one of the queues. The method includes, without requiring concurrent locking of more than one queue, determining if a space is available in each queue for writing a corresponding portion of the data, and if available, reserving the spaces in the queues. The method includes writing each portion of the data to a corresponding one of the queues.

Abstract: A plurality of processors in a multiprocessor circuit is electrically connected to a plurality of independently addressable memory banks via a connection circuit. The connection circuit is arranged to forward addresses from a combination of the processors to addressing inputs of memory banks selected by the addresses. The connection circuit provides for a conflict resolution scheme wherein at least one of the processors is associated with one of the memory banks as an associated processor. The connection circuit guarantees the associated processor a higher minimum guaranteed access frequency to the associated memory banks than to non-associated memory banks. A defragmenter detects data associated with a task running on the associated processor that is stored on one of the memory banks and moves the data to the associated memory banks during execution of the task.

Abstract: A device and method for extracting data stored in a volatile memory are provided. In particular, a memory-data extracting device and method for ensuring integrity of data extracted from a volatile memory installed in a computer are provided. A memory-data extracting module extracts data stored in a memory. A module loader loads the memory-data extracting module in a kernel region of the memory and sets a priority of the loaded memory-data extracting module to be higher than priorities of kernel processors loaded in the memory. Task switching can be prevented in the course of extracting memory data by loading a process for extracting memory data in a kernel region and setting a priority of the loaded process to be higher than priorities of other kernel processes, thereby ensuring the integrity of data extracted from a non-volatile memory.

Abstract: Some embodiments of the invention relate to an apparatus and a method of managing a snapshot storage pool (SSP) associated with a storage unit of a distributed data storage system. According to some embodiments of the invention, the apparatus may include a logic module and a controller. The logic module may be adapted to provide a threshold corresponding to a ratio between a current amount of storage resources used for storing snapshots in the SSP and a total storage capacity defined for the SSP. The controller may be adapted to trigger an action which may be effective for managing the SSP in response to the amount of storage resources used for storing snapshots in the SSP crossing the threshold.

Abstract: A second memory stores data in units of segments. An assignment control circuit sets up a buffer space as a logical address space. A buffer space is formed as a set of at least one segment. A state storage circuit stores association between a buffer space and segments as segment assignment information. An address conversion circuit refers to segment assignment information to convert a logical address into a physical address. A segment queue stores a free segment and a buffer queue stores a free buffer. The state storage circuit includes a plurality of register groups each of which includes a plurality of segment registers. A register group is associated with one of the plurality of buffer spaces. A range number identifying a range of logical addresses in the associated buffer space is set up in a segment register.

Abstract: A method, system, and medium are provided for managing cache allocation between a primary storage and a secondary storage. The system includes a device with a primary storage, secondary storage, and cache manager. The method includes downloading a web resource, storing the web resource in the primary storage, determining the amount of time required to download the web resource, and determining the amount of time required to retrieve the web resource from the secondary storage. If the amount of time required to retrieve the web resource from the secondary storage is less than the amount of time required to download the web resource, the method stores the web resource in the secondary storage. Additionally, web resources may be moved from the secondary storage to the primary storage based on their likelihood of being utilized.

Abstract: A method of and apparatus for arbitrating a memory access conflict to a memory array. The apparatus may include selection logic coupled with a plurality of ports and a memory array to arbitrate among a plurality of contending memory access requests and to conditionally block write data from accessing the memory array when write data arrives late in time.

Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

Abstract: A storage device includes: a storage unit for writing data into a rotating storage medium via a writing head; a nonvolatile memory; a temporary storage memory for storing a plurality of writing commands temporarily; and a controller for executing the plurality of writing commands so as to selectively write data into the storage unit or the nonvolatile memory, rearranging the writing commands stored in the temporary storage memory in accordance with efficiency for executing the writing commands to write data into the storage unit, sequentially executing the rearranged writing commands in descending order, and executing in parallel at least one of the writing commands that has not been executed to write data into the nonvolatile memory until all the data to be written in accordance with the writing commands are stored in either the storage unit or the nonvolatile memory.

Abstract: A method and system for configuring a cache memory system in order to efficiently process processor requests. A group of cache elements, which include a Region Cache, a Region Coherence Array, and a lowest level cache, is configured based on a tradeoff of latency and power consumption requirements. A selected cache configuration differs from other feasible configurations in the order in which cache elements are accessed relative to each other. The Region Cache is employed in a number of configurations to reduce the power consumption, latency, and bandwidth requirements of the Region Coherence Array. The Region Cache is accessed by processor requests before (or in parallel with) the larger Region Coherence Array, providing the region coherence state and power efficiently to requests that hit in the Region Cache.

Abstract: Provided are a method, system, and article of manufacture for varying access parameters for processes to access memory addresses in response to detecting a condition related to a pattern of processes access to memory addresses. A monitored condition is detected during application execution. An instrumentation program is invoked to monitor processes accessing data at addresses in a memory device in response to detecting the monitored condition. Information is logged on processes and the addresses they access in the memory device in response to invoking the instrumentation program. The logged information on the processes and the addresses they access is forwarded to an application analysis system in response to detecting a monitored condition during application execution.

Abstract: Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally comprise identifying one or more isochronous requests among a plurality of requests which may be issued to a data storage device, assigning a completion deadline an isochronous request, and communicating the isochronous request and completion deadline information to the data storage device. Apparatus embodiments generally comprise a request identifier to identify an isochronous request, a logic module to assign a completion deadline to the isochronous request, and a communication module to communicate the isochronous request and the completion deadline to a data storage device. Alternative apparatus embodiments may include a monitor module to monitor a system process operating in the system and determine if the system process issues isochronous requests.

Abstract: Mechanisms are disclosed for detecting protocols independently of the ports used by streams associated with the protocols or applications that may send out such streams. The detecting may entail using a content filter that is hosted on a networking stack, where the content filter may be composed of a stream buffer and handlers for detecting the protocols. The handlers may be further used to modify streams incoming to a port or streams outgoing from an application. The handlers can modify the streams in a variety of ways, including reading, inserting, replacing, deleting, and completing data in the streams according to some policy criteria, such as those set by parental controls. Individual handlers may be selected from a plurality or set of handlers so that they can be matched up to the appropriate streams.

Abstract: A device, including a first storage unit configured to store a first plurality of files and a first management data corresponding to the first files; a connector configured to connect to an external storage device, the external storage being configured to store a second plurality of files and second management data corresponding to the second files; a controller configured to generate new management data by merging the first management data and the second management data, and to store the new management data in a memory; and a display unit configured to display contents of the first and second plurality of files based on the new management data without indicating to the user where the respective files are stored.

Abstract: A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device.

Abstract: A closed-loop system for dynamically distributing memory bandwidth between real-time components and non-real-time components is provided. Specifically, the present invention includes monitors for measuring a performance of each of the real-time components. Based on the measured performance, closed-loop feedback loop is communicated to a unified memory system. The feedback is used by the memory controls within the unified memory system to efficiently and dynamically distribute memory bandwidth between the real-time and the non-real-time components.

Abstract: A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.