Abstract: In general, in one aspect, the disclosure describes storing identification of one or more memory buckets associated with different, respective, queued write commands, and, based on the stored identification, determining whether at least one bucket associated with a read command is included in one or more buckets associated with at least one queued write command.

Abstract: A multiple agent system providing each of a plurality of agents, e.g., processors, to access a shared synchronous or asynchronous memory. In the case of synchronous memory, the clock signal from a super agent selected from among the plurality of agents provides a memory access clock signal to the other agents accessing the same shared memory. The other agents synchronize their respective address, data and control busses to those of the super agent, and output a representation of the same clock signal to the shared memory. In another aspect of the present invention, the shared memory is partitioned for use from among a plurality of groups of agents, each agent group comprising one or more agents. Any one of the agents may update a configuration register to flexibly reconfigure the amount of shared memory available to the agents as necessary.

Abstract: An improved descriptor system is provided in which read pointers indicate to a host and a peripheral the next location to read from a queue of descriptors, and write pointers indicate the next location to be written in a queue. The system also allows an incoming descriptor to point to a plurality of data frames for transfer to the host processor, wherein the peripheral need not read a new descriptor each time a frame is to be transferred to the host.

Abstract: Systems and methods for generating, maintaining, and using merged partitions to process requests of one or more host systems to storage partitions of one or more storage elements. Each merged partition maps to one or more storage partitions defined within one or more of the storage elements. The storage elements may be combined to form a storage complex. Each storage element of the storage complex may include one or more storage volumes, such as an array of storage volumes. A system includes a map processor and an interface controller. The map processor is configured for mapping the storage partitions of each storage element to generate one or more merged partitions. The interface controller is communicatively connected to the host systems and to the map processor for processing the requests of the host systems to the storage volumes based on the merged partitions.

Abstract: A method and system utilizing a peer mapping system call, called by a first process, to map allocated shared memory into the address space of a second process. Code for implementing the system call can reside in a server which provides services to map allocated shared memory into all the processes having access to shared memory or the code can be located in a library linked to all the processes having access to shared memory.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and fragment types. Memory space allocated may be of a predetermined size for a thread type. Memory locations within a first memory space may be interleaved with memory locations within a second memory space.

Abstract: A system and method is disclosed for synchronizing a plurality of processors in a processor array. The system and method synchronizes data communications between the processors by regulating memory access of the processors to memory bytes of an asynchronous variable memory. Each memory byte in the asynchronous variable memory is a “read full and write empty” memory byte. Except for a system processor, each processor in the process array can only write data to an empty memory byte and can only read data from a full memory byte. The processors are prevented from untimely overwriting data and from untimely reading data. This keeps the data communications between the processors properly synchronized.

Abstract: The present invention provides a method, apparatus, and system for controlling memory accesses to multiple memory zones in an isolated execution environment. A processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that stores configuration settings. The configuration settings include a plurality of subsystem memory range settings defining memory zones. The access transaction also includes access information. A multi-memory zone access checking circuit, coupled to the configuration storage, checks the access transaction using at least one of the configuration settings and the access information. The multi-memory zone access checking circuit generates an access grant signal if the access transaction is valid.

Abstract: A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

Abstract: A method is disclosed for instructing a computing system to allocate a trace array from an original cache memory, where the method includes dividing the original cache memory into a reduced-size cache memory and a trace array, permitting storage of trace signal data into the trace array, and permitting retrieval of the trace signal data from the trace array.

Abstract: In a cluster system including a plurality of operating systems operating on one computer, computer resources can be updated for and reallocated to each operating system. When the operating systems are used as active or standby operating systems, a multiple operating system management controller monitors the state of each operating system. At a failure of an active operating system, the controller allocates a larger part of computer resources to another operating system in a normal state and assigns the operating system as a new active operating system. Regardless of the failure, the computer system can be operated without changing processing capability thereof. The controller can monitor load of each operating system to allocate computer resources to the operating system according to the load.

Abstract: A memory partitioning system for memory of an embedded or auxiliary processor is described. Memory regions with different attributes are formed, having specified cacheability and visibility characteristics. A configurable table describes the memory regions required by the software running on the auxiliary processor.

Abstract: The disclosed embodiments relate to a device for generating physical addresses in a multi-processor computer system. The computer system may be adapted to support multiple physical memory partitions. Agent IDs for each of a plurality of processors may be used to correspond with a partition offset, which may be used to define a separate physical memory partition for each processor. The partition offset may be used with a virtual address to form a physical address.

Abstract: A method, system, and product are described for creating and managing affinity between memory and processors in logical partitions in a data processing system. The data processing system includes multiple processors. A memory affinity data structure is established. The memory affinity data structure identifies ones of the processors that have a close affinity with each one of multiple regions of the system memory. A memory affinity parameter is established and is utilized to determine whether memory affinity is required for each one of the logical partitions. In response to a determination that memory affinity is required for one of the logical partitions, the memory affinity data structure is utilized by a partition manager for the logical partition to allocate an optimal amount of memory that has a close affinity to ones of the processors that are assigned to the logical partition.

Abstract: The present invention relates to a method of operating a buffered crossbar switch. The proposed method reduces power dissipation in a buffered crossbar switch by reducing the number of crossbar buffer write processes.

Abstract: A method is described comprising inserting an allocation instruction within a routine if a function call instruction is found within the routine. Another method is described comprising inserting multiple allocation instructions within a routine by searching for one or more functional characteristics within the routine and inserting an allocation instruction within the routine if a functional characteristic is discovered. Another method is described comprising performing a first allocation for a first amount of register space at the entry block of a routine and then performing a second allocation for a second amount of register space for the live information within the routine at the time of the second allocation. Then, performing a function call to a second routine and performing a third allocation for a third amount of register space at the entry block of the second routine, the third amount of register space and the first amount register space having a common register.

Abstract: A network device for monitoring a memory partitioned by an identifier can include at least one port configured to receive at least one packet. The at least one packet includes an identifier relating to priority of the at least one packet. The network device can also include a buffer memory having at least one buffer configured to store the at least one packet, and a counter configured to modify a counter value therein when the buffer memory is accessed with respect to the at least one data packet, wherein the counter corresponds to the identifier with respect to the at least one packet.

Abstract: A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: In a digital data processing system having a memory component, a structure and method for managing available memory resources. Free pointers to respective free memory blocks are stored in memory blocks maintained as a linked list. In a system having a hierarchically-organized memory component, a small number of the free pointers are maintained at a relatively higher performance level of the memory and the balance of the free pointers are maintained at a relatively lower performance level of the memory.

Abstract: Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated register file to be accessed by the corresponding processor thread. In an illustrative embodiment, the register file is divided into even and odd portions, with a least significant bit or other portion of the thread identifier being used to select either the even or the odd portion for use by a given processor thread. The thread-based register file selection may be utilized in conjunction with token triggered threading and instruction pipelining. Advantageously, the invention reduces register file port requirements and thus processor power consumption, while maintaining desired levels of concurrency.

Abstract: A method and a system of cache management using spatial separation of outliers. The system includes a dynamic compiler arranged to create compiled fragments of code having dominant code blocks and outliers. Memory coupled to the dynamic compiler is managed by a compiler manager such that dominant code blocks are stored in one portion of the memory and the outliers are stored in another portion of the memory. Storing the dominant path code separate from the outliers increases efficiency of the system.

Abstract: A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, a portion (42a) of the memory is connected directly to one of the requestors, such, as a host processor (10), so that high bandwidth transfers can be performed. A portion (42b) that is not selected to be in HOM mode can be accessed by other requestors or shut down to save power. The size (S1) of the portion of memory selected for HOM mode is selected to match the requirements of a given application and can be changed by writing a size value to a register.

Abstract: An apparatus and method for identifying unused storage capacity of a number of network storage devices, and configuring at least a portion of the unused storage capacity as a logical storage device. The invention is preferably embodied in computer readable program code. The unused storage capacity may be identified by monitoring the number of network storage devices and automatically determining the unused storage capacity thereof. Alternatively, user-defined parameters may be used for identifying the unused storage capacity. At least a portion of the identified storage capacity is allocated for common use as at least one logical device. The allocated storage capacity is managed according to a management policy so that the allocated memory is not overwritten, data is not backed up to the same physical device, etc.

Abstract: An apparatus and method for sharing a boot volume among server blades. The shared boot volume may be a single drive or a RAID volume. The shared boot volume is first partitioned into boot slices. Next, individual boot slices of the shared boot volume are correlated with individual server blades, which share the shared boot volume. When a boot slice is correlated with a server blade, the boot slice is presented to the server blade, and the server blade sees the boot slice and only the boot slice, and owns the boot slice. This correlation is transparent to the OS or applications on a given server blade, because the I/O controller masks all boot slices but the one owned by that server blade. As far as OS and applications are concerned, the server blade just has a single boot slice as a dedicated local drive.

Abstract: Data object management for a range of memory. The range of memory has first and second opposite ends. A plurality of data objects are written to a first contiguous region of memory located at the first end of the range of memory. At least one of the valid data objects of the plurality of data objects are copied to a second contiguous region of memory located at the second end of the range of memory when a reclamation process is requested. The valid data objects copied from the first contiguous region of memory are marked as invalid data in the first contiguous region of memory subsequent to the valid data objects being copied to the second end of the range of memory, and the memory in which invalid data objects in the first contiguous region of memory are located is erased.

Abstract: A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to the port from a pool of un-assigned partitions. The pool of un-assigned partitions comprises of un-assigned partitions from the first group of partitions and un-assigned partitions from the second group of partitions. The un-assigned partitions from the first group of partitions are assigned to the port until a first threshold is reached. The un-assigned partitions from the second group of partitions are assigned to the port after the first threshold is reached. A second threshold is used to limit a total number of partitions assigned to the port.

Abstract: Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue and dequeue nodes that it may choose. The prior art merely provided access to the values stored in the node. In order to avoid anomalies, the queue is never allowed to become empty by requiring the presence of at least a dummy node in the queue. The ABA problem is solved by requiring that the next pointer of the tail node in each queue point to a “magic number” unique to the particular queue, such as the pointer to the queue head or the address of the queue head, for example. This obviates any need to maintain a separate count for each node.

Abstract: A method and apparatus for virtual address translation include processing that begins by receiving a memory access request that includes a virtual address. The processing continues by determining whether a physical address translation has been performed for the virtual address. Note that a physical address translation translates the virtual address into an address. The address either corresponds to physical address of memory or is further translated into another physical address of memory. The processing continues when the address, which resulted from the physical address translation or the another physical address translation, is stored in a translation look aside table (TLB). When the physical address translation or the another physical address translation has not been performed, the processing retrieves a physical page address based on a portion of the virtual address.

Abstract: A system is described for controlling access to non-volatile memory. The system can include logic configured to determine whether to delay access to the non-volatile memory.

Abstract: The pseudo-linear frame buffer mapping system and method facilitates the clearing of the frame buffer memory of a graphics display system by subdividing the region of the frame buffer which is to be cleared into a plurality of sub-regions and by initiating the clear command concurrently to each of the plurality of sub-regions.

Abstract: A distributed computer system is disclosed that allows shared memory resources to be synchronized so that accurate and uncorrupted memory contents are shared by the computer systems within the distribute computer system. The distributed computer system includes a plurality of devices, at least one memory resource shared by the plurality of devices, and a memory controller, coupled to the plurality of devices and to the shared memory resources. The memory controller synchronizes the access of shared data stored within the memory resources by the plurality devices and overrides synchronization among the plurality of devices upon notice that a prior synchronization event has occurred or the memory resource is not to be shared by other devices.

Abstract: A memory array is divided into a plurality of blocks. A plurality of mode storage units is so disposed as to correspond to the memory blocks. When a plurality of controllers outputs a mode setting instruction at the time of making of power, a setting unit 113 sets control information designated by the mode setting instruction to the corresponding mode storage unit. When different controllers gain access to a synchronous DRAM, an access operation is executed for the corresponding memory block in accordance with the control information.

Abstract: A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.

Abstract: A method and structure for balancing associative resource (e.g., cache lines or buffers) allocation with respect to load, wherein said resources are allocated/deallocated to requesting processes or “agents” based on their reference history and demand. User agents that fail to meet minimum use criteria, are forced to relinquish logically allocated resources to high demand agents. Otherwise, an agent maintains control of its resources in the presence of other high demand agents, without cross-agent thrashing for resources. An associative resource “pool” is logically divided into m partitions. A small “partition reference” counter is employed for each partition to record its usage history. A global “persistence reference” counter functions to erase the “set reference” counter history at a programmable rate. Low “partition reference” counter values imply low usage, and make partition resources available to high usage partition(s) when needed.

Abstract: A method for managing a memory pool containing memory blocks between a producer thread and a consumer thread running in parallel within a process is disclosed. The method places free memory blocks in a first group in the memory pool and allocates on demand a memory block from the first group to the producer thread. The allocated memory block is shared between the producer thread and the consumer thread. Once the allocated memory block is no longer required, the consumer thread deallocates the allocated memory block by placing the deallocated memory block in a second group of the memory pool. Deallocated memory blocks in the second group are moved to a third group only when the third group is empty. Memory blocks in the third group are moved to the first group only when the third group is non-empty. A locking mechanism is not required in such a multi-threaded environment.

Abstract: A method, system and computer program product for sharing an Integrated Device Electronics (IDE) drive among server blades in a dense server environment. By logically partitioning the IDE drive, where each logical partition is associated with a particular server blade, the IDE disk may be shared among multiple server blades in the dense server environment.

Abstract: Caching memory contents into cache partitions based on their locations is disclosed. A location of a line of memory to be cached in a cache is determined. The cache is partitioned into a number of cache sections. The section for the line of memory is determined based on the location of the line of memory as applied against a memory line location-dependent allocation policy. The line of memory is then stored in the section of the cache determined.

Abstract: A database system with multi-level partitioning is disclosed. The system includes a plurality of storage facilities with each storage facility storing data that represents rows of database tables. In each storage facility table rows corresponding to a specific table are logically ordered according to a row identifier, also called the row ID. The row ID includes a first value that is based on one or more columns of the table. The row ID also includes a second value that is based on one or more columns of the table. The row ID also includes a third value. The first value is calculated based on a single-level function. The single-level function is a combination of a plurality of functions. The single-level function produces different values for two rows when any of the plurality of functions produces different values for the two rows. The first value of the row ID is predominate in determining the order of the rows in the storage facilities.

Abstract: There is disclosed a method and architecture for establishing independent, secure, trusted sub-networks within a storage area network (SAN). These virtual private SANs allow secure, managed interconnections between an initiator host and a target storage device or a logical unit number (LUN) indicating a sub-portion of a target storage device. A table of allowable configurations along with a connections database are used to ensure proper, allowable data connections.

Abstract: In an embodiment, the present invention is directed to a system for intermediating communication, with a moveable media library, utilizing partitions, wherein the moveable media library comprises an internal controller that is, in part, operable to control a robotics subsystem in response to commands received via a control interface. Such a system comprises: a bridge unit that is operable to pass library commands to an external controller, wherein the bridge unit is operable to associate a plurality of logic units (LUNs) with the external controller. The external controller is operable to process library commands from the bridge unit, wherein the external controller associates each partition of a plurality of partitions with a respective LUN of the plurality of LUNs, and the external controller is further operable to translate received commands from the bridge unit for communication to the internal controller according to the plurality of partitions.

Abstract: A data processing system, method, and product are disclosed for debugging partition management firmware from an existing operating system debugger. The partition management firmware is also called a hypervisor. The data processing system is logically partitioned and includes an operating system debugger and hypervisor software. An operating system and the operating system debugger are stored in one of the logical partitions. Extensions are included within the operating system debugger. The extensions are then utilized by the existing operating system debugger to debug the hypervisor.

Abstract: An information recording apparatus according to the present invention manages a priority value for each host that can log in, and allocates an immediate data buffer to each host based on the priority value. The priority value changes in accordance with data transfer amount, command importance degree, etc. The information recording apparatus recalculates the priority value regularly or arbitrary, and re-performs login negotiation by requesting re-login to the hosts. The amount of buffer allocated is dynamically changed by this login negotiation, and a buffer allocation state best suited to each occasion is built. Since the present invention can dynamically determine or change the allocation amount of the immediate data buffer in accordance with the condition of each occasion, the performance of an iSCSI apparatus can be improved.

Abstract: Disclosed are a system and method of transmitting data or instructions through a data bus to a memory array associated with a core processing circuit. The memory array may be initially adapted to receive data from the data bus and store the data or instructions received from the data bus. At least a portion of the memory array comprising the stored data or instructions may then be configured as a cache memory of the core processing circuit.

Abstract: An open format storage subsystem and method are provided. The storage subsystem and method include at least one host endnode, at least one processing unit endnode, and at least one storage endnode. These endnodes are partitioned according to partition tables assigned to the ports of the endnodes and partition keys assigned to queue pairs of the ports. Based on these partition keys, partitions in the storage subsystem are designated. In this way, certain endnodes may be designated as being able to communicate with only certain other ones of the endnodes. Because of the partitioning mechanism of the present invention, an open format storage subsystem is formulated such that the types of endnodes in the storage subsystem are not limited to vendor specific units. This enhances the ability to add and remove units from the storage subsystem by removing the limitations typically found in closed storage subsystems.

Abstract: A real address range check mechanism verifies real addresses generated in a computer system which translates real addresses from effective addresses, some of the effective addresses being real addresses not requiring translation. The system has at least two operating modes. In one mode, the range checking mechanism generates an error signal responsive to detecting a real address outside a predetermined range, and in the other operating mode no error signal is generated. Preferably, the computer system's hardware resources, including real address space, is logically partitioned, partitioning being managed by an ultra-privileged process called a hypervisor. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, real address range checking error signals being disabled in the hypervisor state.

Abstract: A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node.

Abstract: A memory system having a memory controller and a memory device coupled to the memory controller. The memory controller outputs a write data value to the memory device. The memory device receives the write data value from the memory controller, and compares the write data value with a mask key value. If the write data value matches the mask key value, the memory device does not store the write data value. If the write data value does not match the mask key value, the memory device stores the write data value.

Abstract: A multiplexed addressed data bus are provided for transferring data between two microprocessors. The multiplexed address and data bus include a plurality of multiplexed lines for communicating between the two microprocessors. A read/write signal line is also provided for communicating between the two microprocessors for indicating whether a read or a write operation is to be preformed. A chip select line is provided for transitioning to an enable condition during a data transfer cycle. A data strobe line is in communication between the two microprocessors and provides a strobe signal for each sequence of a data transfer cycle.

Abstract: A method and apparatus in a data processing system for processing a request to display a pattern. A plurality of partitions is created in a memory in a graphics adapter in the data processing system, wherein each partition within the plurality of partitions has a size equal to each of the other partitions within the plurality partitions. A determination is made as to whether the pattern is present within the plurality of partitions. The pattern is displayed using the plurality of partitions if the pattern is present within the plurality of partitions. The pattern is retrieved from another location if the pattern is absent from the plurality of partitions. Responsive to retrieving the pattern from another location, the pattern is stored if the pattern is within the size.