Shared Memory Partitioning Patents (Class 711/153)
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Patent number: 7801163Abstract: A method for allocating space among a plurality of queues in a buffer includes sorting all the queues of the buffer according to size, thereby to establish a sorted order of the queues. At least one group of the queues is selected, consisting of a given number of the queues in accordance with the sorted order. A portion of the space in the buffer is allocated to the group, responsive to the number of the queues in the group. A data packet is accepted into one of the queues in the group responsive to whether the data packet will cause the space occupied in the buffer by the queues in the group to exceed the allocated portion of the space.Type: GrantFiled: April 13, 2006Date of Patent: September 21, 2010Inventors: Yishay Mansour, Alexander Kesselman
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Patent number: 7793349Abstract: Disclosed as a system and method for providing enhanced security to processes running on a data processing system. The disclosed system and method selectively revokes execute privileges from memory pages being used for stacks of susceptible processes running on the data processing system. By selectively resetting execute privileges on a per page and per process basis, the system and method maintains system performance and provides enhanced security to processes running on the data processing system.Type: GrantFiled: January 24, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventor: Roger Kenneth Abrams
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Patent number: 7788725Abstract: A method and system for probing FCode in problem state memory. A PCI device is detected from a PCI-PCI bridge node included in a device tree. A child node for the detected PCI device is created in problem state memory. The active package is switched to the child node, and the processor switches from running in privileged mode to running in problem mode. FCode of an FCode driver in the PCI device is probed. Data, properties and methods generated in response to the probe are created in problem state memory. After the probe is complete, the active package is switched to the parent node of the child node, and the processor switches back to running in privileged mode.Type: GrantFiled: January 5, 2006Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventor: Arokkia Antonisamy Rajendran
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Publication number: 20100217940Abstract: To propose a centrifugal separator that is capable of performing, easily and accurately, a condition setting operation for continuously operating the centrifugal separator under a plurality of operating conditions. In the centrifugal separator, which stores operating conditions in a plurality of memories respectively and independently or continuously calls up the operating conditions stored in these memories to perform operation control, a plurality of memory selection keys corresponding to the plurality of memories are provided, and the memories for storing the operating conditions therein and the memories for calling up the operating conditions are specified by selecting the memory selection keys.Type: ApplicationFiled: May 28, 2009Publication date: August 26, 2010Applicant: TOMY KOGYO CO., LTD.Inventor: Mizuyoshi Shibutani
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Patent number: 7783833Abstract: A storage system includes one or more host computers; and a storage controller that provides each of the one or more host computers with a plurality of logical volumes, each including a storage area for reading/writing data from/to, and also being either allocated or not allocated to one or more of the host computers, the storage controller including: an identification unit that identifies function information relating to a logical volume from among the plurality of logical volumes included in information relating to the plurality of logical volumes based on a command from a host computer from among the one or more host computers; and an execution unit that executes processing on the logical volume in accordance with an identification result of the identification unit.Type: GrantFiled: June 12, 2008Date of Patent: August 24, 2010Assignee: Hitachi, Ltd.Inventor: Atsuya Kumagai
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Patent number: 7779222Abstract: A dynamic memory work-stealing technique involves the implementation of a deque as a doubly-linked list of nodes. All, or almost all, of the nodes are memory structures that may be dynamically allocated and freed from a shared node pool accessible to a plurality of processes. When a process has exhausted its local memory resources, the process may “steal” memory resources from another process that has available memory resources.Type: GrantFiled: July 22, 2005Date of Patent: August 17, 2010Assignee: Oracle America, Inc.Inventors: Yosef Lev, Nir N. Shavit
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Patent number: 7774562Abstract: A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.Type: GrantFiled: September 17, 2004Date of Patent: August 10, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Richard W. Adkisson, Christopher Greer, Huai-ter Victor Chong
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Patent number: 7774543Abstract: The present invention provides a storage system, a method for managing the same, and a storage controller, to obtain a storage apparatus that uses iSCSI protocol, which makes it possible for each user to configure the necessary settings within the scope of their provided right.Type: GrantFiled: November 14, 2006Date of Patent: August 10, 2010Assignee: Hitachi, LtdInventor: Atsuya Kumagai
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Patent number: 7774659Abstract: The present invention relates to computers executing in time-share mode, under the control of their operating systems, a number of separate and independent application programs. The present invention relates in particular to the networks of onboard computer networks of IMA type executing application programs written independently of the hardware specifications of the computers and not permanently resident in the computers. The method of the present invention associates with the digital core of each computer of the network a monitoring state machine operating independently and in having the monitoring state machine monitor the correct observance by the associated computer of the time sequencing of the tasks and memory partition allocations. Furthermore, the monitoring state machines can be configured to execute monitoring service applications of time-out or watchdog type to which the application programs executed by the computers of the network can subscribe.Type: GrantFiled: September 4, 2006Date of Patent: August 10, 2010Assignee: ThalesInventor: Pierre Roussel
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Patent number: 7774467Abstract: In accordance with one embodiment of the present invention, there are provided methods and mechanisms for determining an allocation of resources, including hardware resources in a computing environment. With these methods and mechanisms, it is possible for computing resource allocations to satisfy one or more operational considerations, such as for example without limitation: “reduce device heat dissipation”, “avoid single point of failure in switched network” and other allocation needs are contemplated.Type: GrantFiled: September 22, 2004Date of Patent: August 10, 2010Assignee: Oracle America Inc.Inventors: Jean-Christophe Martin, Junaid Saiyed, Yulin Xu
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Patent number: 7774525Abstract: Zoned initialization of a solid state drive is provided. A solid state memory device includes a controller for controlling storage and retrieval of data to and from the device. A set of solid state memory components electrically coupled to the controller. The set is electrically divided into a first zone and a second zone, wherein the first zone is at least partially initialized independent from the second zone. An interface is coupled between the controller and the set of solid state memory components to facilitate transfer of data between the set of solid state memory components and the controller.Type: GrantFiled: March 13, 2007Date of Patent: August 10, 2010Assignee: Dell Products L.P.Inventors: Munif M. Farhan, Thomas L. Pratt
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Patent number: 7769962Abstract: A system and a method for thread creation where only copied threads share the same stack location for execution, so unrelated threads have individual stack space and can be executed concurrently in multi-processor system. Also, the copy operation of the stack frame is only necessary among the copied threads, so the speed of context switching among individual threads is fast. This operation can be a simple page table modification in the virtual memory management mechanism for further speed up.Type: GrantFiled: July 10, 2007Date of Patent: August 3, 2010Assignee: Jeda Technologies, Inc.Inventor: Atsushi Kasuya
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Patent number: 7765365Abstract: A method of partitioning storage is provided. In an exemplary embodiment, the method includes connecting at least one initiator with at least one target device. Upon connection of the at least one initiator with the at least one target device, at least one initiator-target association object may be created. The method may also include selecting at least one storage partition with the at least one initiator-target association object.Type: GrantFiled: November 18, 2005Date of Patent: July 27, 2010Assignee: LSI CorporationInventors: James A. Lynn, Kevin F. Lindgren
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Publication number: 20100185823Abstract: Techniques for enabling high-performance computing are provided. The techniques include resizing a logical partition in a non-dedicated compute cluster server to enable high-performance computing, wherein a high performance computing application is executed such that the high performance computing application is configured to complete execution of each of one or more application threads at a similar instance as a slowest thread in the cluster, and wherein the non-dedicated compute cluster comprises one or more servers and the logical partition is created by partitioning one or more server resources.Type: ApplicationFiled: January 21, 2009Publication date: July 22, 2010Applicant: International Business Machines CorporationInventors: Pradipta De, Ravi Kothari, Vijay Mann, Rajiv Sachdev
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Patent number: 7761717Abstract: A memory device containing data to be protected is integrated with a microprocessor and includes a first and a second memory portion with different accessibilities. The integration of the memory device on the same integrated circuit (IC) or chip as the microprocessor permits a combination of protective hardware and software measures that are not possible with a memory device that is on a different IC than the microprocessor. The first memory portion holds an initialization program that also serves as a boot program during decryption, and the second memory portion holds a user program, for example, a program for decrypting and/or decoding received data. Such data may be, for example, audio data encoded according to the MP3 standard and encrypted with a secret or public password against unauthorized reception.Type: GrantFiled: July 10, 2002Date of Patent: July 20, 2010Assignee: Trident Microsystems (Far East) Ltd.Inventors: Peter Möller, Zoran Mijovic, Manfred Jünke, Joachim Ritter, Steffen Zimmermann
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Patent number: 7757049Abstract: A method for processing using a shared file that includes allocating a first working buffer between the shared file and a plurality of address spaces, wherein each of the plurality of address spaces is associated with one of a plurality of processors, copying first data from the shared file to the first working buffer by a first aggregator copying the first data from the first working buffer to the plurality of address spaces by the first aggregator, processing the first data, in parallel, by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.Type: GrantFiled: November 17, 2006Date of Patent: July 13, 2010Assignee: Oracle America, Inc.Inventors: Andrew B. Hastings, Anton B. Rang, Alok N. Choudhary
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Publication number: 20100174872Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.Type: ApplicationFiled: January 6, 2009Publication date: July 8, 2010Inventors: Brent S. Baxter, Prashant Sethi, Clifford D. Hall, William H. Clifford
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Patent number: 7750952Abstract: An image data recording apparatus includes an area producing device producing a plurality of areas on a recording medium, an initialization device initializing the areas produced by the area producing device in accordance with desired forms, an area production designating device causing a user to designate a number of the areas produced by the area producing device and a recording capacity of each of the areas, and a format designating device causing the user to designate a kind of a format of each of the areas produced by the area producing device.Type: GrantFiled: May 24, 2005Date of Patent: July 6, 2010Assignee: Canon Kabushiki KaishaInventor: Shigeru Yoneda
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Patent number: 7743146Abstract: A method of controlling concurrent users of a distributed resource on a network is disclosed. In one aspect, there are one or more local lock managers executing on corresponding hosts and cooperating as a distributed lock manager. The resource is limited to a maximum number of concurrent users. A user identification for each user is associated with one host. In response to a request associated with a particular user associated with a first host, a lock is requested from a first local lock manager process executing on the first host. A related method of handling a request for a count-limited resource includes receiving a request from a client process for the computer resource. If it is determined that the request exceeds a maximum count for the resource, then it is determined whether a current time is within a retry time period of the client's first request.Type: GrantFiled: December 19, 2007Date of Patent: June 22, 2010Assignee: Cisco Technology, Inc.Inventor: Shahrokh Sadjadi
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Patent number: 7743222Abstract: Methods, systems, and media for managing dynamic memory are disclosed. Embodiments may disclose identifying nodes with having memory for dynamic storage, and reserving a portion of the memory from the identified nodes for a heap pool. After generating a heap pool, embodiments may allocate dynamic storage from the heap pool to tasks received that are associated with one of the identified nodes. More specifically, embodiments identify the node or home node associated with the task, the amount of dynamic storage requested by the task, and create a heap object in the node associated with the task to provide the requested dynamic storage. Some embodiments involve de-allocating the dynamic storage assigned to the task upon receipt of an indication that the task is complete and the dynamic storage is no longer needed for the task. Several of such embodiments return the de-allocated dynamic storage to the heap pool for reuse.Type: GrantFiled: April 8, 2008Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Kenneth Roger Allen, Richard Karl Kirkman, Patrick Joseph McCarthy, Wade Byron Ouren
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Patent number: 7743221Abstract: A memory sharing method for at least a functional module and a target module is disclosed. The functional module includes at least a static random access memory (SRAM), the memory sharing method includes the steps of calculating a memory capacity of the functional module; if a total memory capacity of a module group satisfies a memory capacity requirement of the target module, allocating the SRAM of the module group, wherein the module group comprises at least one functional module; and accessing the SRAM of the functional module of the module group by utilizing the target module.Type: GrantFiled: January 22, 2007Date of Patent: June 22, 2010Assignee: MediaTek Inc.Inventors: Chih-Ching Chen, Li-Chun Tu
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Patent number: 7739458Abstract: An image forming apparatus includes a plurality of hardware resources provided to carry out image formation. A plurality of application programs perform respective processing of the plurality of hardware resources related to the image formation. A storage device stores rewritable shared data which is used by the application programs in common. A shared-data control unit suspends one of a write-lock request or a read-lock request that is received from one of the application programs when acquisition and/or updating of the shared data is inhibited, and after the acquisition and/or updating of the shared data is allowed, inhibits the acquisition and/or updating of the shared data by other application programs in accordance with the suspended request for the one of the plurality of application programs.Type: GrantFiled: September 10, 2003Date of Patent: June 15, 2010Assignee: Ricoh Company, Ltd.Inventor: Junichi Minato
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Patent number: 7725558Abstract: A device for securely controlling communications among or within computers, computer systems, or computer networks, comprising: (a) a primary access port to which an “owner” computer program, computer, computer system, or computer network is connectable to access shared computer resources; (b) a secondary access port to which a non-owner computer program, computer, computer system, or computer network is connectable to access the shared computer resources; (c) a transfer port to which a shared computer resource is connectable to provide controlled access to that computer resource from computer programs, computers, computer systems, or computer networks connected to the access ports; and (d) a separate physical communication path to and from each access port and each transfer port, where access permissions and restrictions for each communication path are set by the owner of the device through the primary access port.Type: GrantFiled: July 26, 2001Date of Patent: May 25, 2010Inventor: David Dickenson
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Patent number: 7720957Abstract: Apparatus and storage media for auto-configuration of an internal network interface are disclosed. Embodiments may install an internal VLAN manager in a logically partitioned computer system along with network agents in each of the partitions in the logically partitioned system to facilitate configuring an internal communications network and the corresponding internal network interfaces in each participating partition. In particular, an administrator accesses internal VLAN manager, selects an internal VLAN ID, selects each of the participating partitions, and configures the communications network with global parameters and ranges. The internal VLAN manager then generates partition parameters and incorporates them into messages for each of the partitions selected to participate in the internal network.Type: GrantFiled: February 11, 2009Date of Patent: May 18, 2010Assignee: International Business Machines CorporationInventors: Charles S. Graham, Harvey G. Kiel, Chetan Mehta, Lee A. Sendelbach, Jaya Srikrishnan
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Publication number: 20100121935Abstract: A multiple computer system with hybrid replicated shared memory is disclosed. The local memory (10, 20, . . . 80) of each of the multiple computers M1, M2, . . . Mn is partitioned into a first part (11, 21, . . . 81) and a second part (12, 22, . . . 82). Each of the first parts are identical and each of the second parts are independent. The total memory available to the system is the first memory part plus n times the second memory part, n being the total number of application running multiple computers.Type: ApplicationFiled: October 5, 2007Publication date: May 13, 2010Inventor: John M. Holt
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Patent number: 7716275Abstract: Methods, systems, and apparatus can provide individual users of a computer system a means to share their quotas to resources accessible through that system. In one embodiment, this is accomplished, in part, by providing a shared quota descriptor understood by a file system and that can be manipulated by individual users. To that end, the present invention further provides individual users access to mechanisms by which to create and adjust shared quotas.Type: GrantFiled: August 31, 2004Date of Patent: May 11, 2010Assignee: Symantec Operating CorporationInventors: Sree Hari Nagaralu, Sunder Phani Kumar
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Patent number: 7711915Abstract: This invention relates to a method for overcoming system administration blockage and refers particulars, though not exclusively, to a method for overcoming system administrator blockage of a device newly connected to a computer.Type: GrantFiled: December 20, 2005Date of Patent: May 4, 2010Assignee: Trek 2000 International Ltd.Inventors: Teng Pin Poo, Henry Tan
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Publication number: 20100106918Abstract: A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination.Type: ApplicationFiled: December 31, 2009Publication date: April 29, 2010Applicant: NVIDIA CORPORATIONInventors: Ram Prabhakar, Neal Meininger, Lefan Zhong, Cahide Kiris, Ed Ahn
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Patent number: 7702663Abstract: A garbage collection system that needs to meet real-time requirements utilizes a read barrier that is implemented in an optimizing compiler. The read barrier is implemented with a forwarding pointer positioned in a header of each object. The forwarding pointer points to the object unless the object has been moved. The barrier is optimized by breaking the barrier and applying barrier sinking to sink the read barrier to its point of use and by using sub-expression elimination. A null-check for the read barrier is combined with a null-check required by the real-time application. All objects are located and moved with the collector to minimize variations in mutator utilization.Type: GrantFiled: January 5, 2004Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: David Francis Bacon, Perry Cheng, Vadakkedathu Thomas Rajan
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Patent number: 7702897Abstract: The present invention provides a system and method to quarantine in the storage operating system and configuration information in which the storage operating system is stored in a designated partition on a removable nonvolatile memory device, such as a compact flash or a personal computer (PC) card that is interfaced with a motherboard of a filer system server. By providing for separate partitions, a failure or error arising during an upgrade to the storage operating system will not corrupt the other partitions.Type: GrantFiled: June 15, 2007Date of Patent: April 20, 2010Assignee: NetApp, Inc.Inventors: John Marshal Reed, R. Guy Lauterbach, Michael J. Tuciarone
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Patent number: 7703098Abstract: By exploiting an early release facility that may be provided by certain transactional memory designs, we allow for transaction software constructs that wait on removal (or satisfaction) of a condition that would otherwise result in transaction abort. Absent exploitation of such a such a facility, the act of checking the condition would typically introduce a corresponding location into the read set of the transaction, and a subsequent modification of that location that removed (or satisfied) the condition, would result in abortion of the blocked transaction. By exploiting an early release facility such as described herein, a transaction may release the location (or locations) corresponding the condition, retry, and once the transient condition is removed (or satisfied), complete and commit. In this way, computation effort may be conserved while still employing a conceptually simple and convenient coordination facility.Type: GrantFiled: July 20, 2004Date of Patent: April 20, 2010Assignee: Sun Microsystems, Inc.Inventors: Mark S. Moir, Maurice Herlihy
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Publication number: 20100095072Abstract: A method is provided for sending and receiving data between a first processor including a first cache memory and a second processor including a second cache memory via a shared memory. The method includes classifying, by the first processor, a transfer data area that stores data transferred between the first and second processors in the shared memory as a first area filling one cache line and a second area not filling one cache line, copying, by the first processor, data in the second area into a divided data area in the shared memory, the divided data area being aligned with a cache line in the first cache memory, and processing, by the second processor, the data in the first area and the data in the divided data area as data from the first processor.Type: ApplicationFiled: October 12, 2009Publication date: April 15, 2010Applicant: CANON KABUSHIKI KAISHAInventor: Tetsuo Ido
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Patent number: 7698373Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.Type: GrantFiled: January 10, 2008Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Ravi Kumar Arimilli, Robert Alan Cargnoni, Derek Edward Williams, Kenneth Lee Wright
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Patent number: 7698704Abstract: Two methods (native and clone) are used for installing software, such as an operating system, on client system(s) booting from shared storage. The native installation method configures an interconnection network to create an exclusive communication zone between the client system and the shared storage system and installs the operating system on the client system using the exclusive communication zone. After the software is installed, the method terminates the exclusive communication zone. The clone installation method utilizes a point-in-time copy feature of the shared storage system to clone an operating system drive instantaneously. After the drive is cloned, it is logically attached to a new client and the operating system is customized for that client.Type: GrantFiled: February 17, 2005Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Bulent Abali, James W. Arendt, Mohammad Banikazemi, D. Scott Guthridge, Dan E. Poff, Ziv Rafalovich, Linda A. Riedle, Gary Valentin, Nancy M. Wei
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Patent number: 7698510Abstract: The invention provides apparatus and methods for registering shared memory objects. An exemplary embodiment of the invention is a method for registering a shared memory object are presented including: locating the shared memory object, the shared memory object having a first size and a first virtual address; finding a shared memory region associated with the shared memory object, the shared memory region having a second size and a second virtual address, the second virtual address returned as a unique identifier; and registering the shared memory object using the unique identifier. In some embodiments, the methods further include: calculating a memory offset for the shared memory region; and registering the shared memory range using the memory offset. In some embodiments, the methods further include: storing the unique identifier, the second size, and the memory offset in a persistent shared memory data structure.Type: GrantFiled: June 22, 2005Date of Patent: April 13, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventor: Srisailendra Yallapragada
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Publication number: 20100088477Abstract: Constructing to include a memory section and a share management section that divides a storage area of a storage apparatus attached to the memory section and allocates the divided areas to each plurality of information processing apparatus, thereby enabling sharing of the storage apparatus by the plurality of information processing apparatuses, carries out a memory access to the storage area on the basis of a memory access request signal from the each information processing apparatus, and generates a response signal from the memory section, thereby allowing the storage apparatus to function as an internal storage apparatus of the information processing apparatus, enables easy modification of the memory size used in an information processing apparatus by sharing memory which is provided external to the information processing apparatus among a plurality of information processing apparatuses, thereby facilitating effective use of the memory.Type: ApplicationFiled: December 10, 2009Publication date: April 8, 2010Applicant: FUJITSU LIMITEDInventor: Toshinori KATSUMATA
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Patent number: 7693920Abstract: A recycle-free directory entry system and method thereof applicable in a file system are provided. The file system uses one or more directory entries to record a unique file/directory name. The recycle-free directory entry method consists of plural directory entries stored in a storage device with a plurality of sectors, each sector only recording all directory entries corresponding to a unique file/directory. Each directory entry has a directory name field, a directory attribute field and a reserve field. The directory name field records a filename of a related file/directory. The directory attribute field records an attribute of the related file/directory. The reserve field records an identity byte, which indicates that all directory entries corresponding to the related file/directory are exclusively recorded in a single sector.Type: GrantFiled: January 17, 2007Date of Patent: April 6, 2010Assignee: Sunplus Technology Co., LtdInventor: Mong-Ling Chiao
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Patent number: 7694076Abstract: A method and system for dynamic distributed data caching is presented. The method includes providing a cache community comprising at least one peer. Each peer has an associated first content portion indicating content to be cached by the respective peer. A client may be allowed to join the cache community. A peer list associated with the cache community is updated to include the client. The peer list indicates the peers in the cache community. A respective second content portion is associated with each peer based on the addition of the client.Type: GrantFiled: March 2, 2007Date of Patent: April 6, 2010Assignee: Parallel Networks, LLCInventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters
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Patent number: 7689783Abstract: A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.Type: GrantFiled: August 17, 2007Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle
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Patent number: 7689782Abstract: An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in the determination. The determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access. The determination is based at least in part on more than one of the following: a group of one or more marker bits included in the first address value, a matrix entry located at least in part using one or more bits of the first address value, a Translation Look-aside Buffer entry associated with the first address value, whether the first address value is associated with stack allocated memory, and whether the first address value includes a null value.Type: GrantFiled: December 6, 2005Date of Patent: March 30, 2010Assignee: Azul Systems, Inc.Inventors: Jack Choquette, Gil Tene, Michael A. Wolf
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Patent number: 7685280Abstract: A method, system and computer program product for communicating requests to multiple destinations in a business transaction are disclosed. A mass request is communicated to a processing center, the mass request including an identification portion and a content portion. The identification portion is used to obtain a parent attribute common to requests to all destinations. The content portion is parsed to generate multiple content strings corresponding to the multiple destinations. The parent attribute and each content string is combined to generate an individual request to a respective destination.Type: GrantFiled: April 23, 2007Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Charles F. Berry, James D. Episale, Judy J. Kogut-O'Connell, Luella A. Korsky, Amy J. Snavely
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Patent number: 7685375Abstract: A portable storage system for connecting to a host, the portable storage system includes a storage device for storing information and a switch. The switch includes a get mode wherein the host sees only the free space in the storage device and not the part storing the information. Optionally, the portable storage system includes a give mode wherein the storage medium shows an empty space to the host and any file or directory is marked as shared and wherein the host sees a file-system whose size equals the amount of empty storage space on the storage device and an owner mode showing all of the stored information to the host and enabling the owner of the system to uncheck a shared flag on a storage device that received from another user that added files.Type: GrantFiled: June 6, 2006Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Chandrasekhar Narayanaswami, Mandayam Thondanur Raghunath
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Patent number: 7660960Abstract: The updating of only some memory locations in a multiple computer environment in which at least one applications program (50) executes simultaneously on a plurality of computers M1, M2. . . . Mn each of which has a local memory, is disclosed. Memory locations (A, B, D, E, X) in said local memory are categorized into two groups. The first group of memory locations (X1, X2, . . . Xn, A1, A2, . . . An) are each accessible by other computers. The second group of memory locations (B, E) are each accessible only by the computer having the local memory including the memory location. Changes to the values of memory locations in the first group only are transmitted to all other computers. A promotion mechanism is disclosed to promote memory locations in the second group into the first group in the event that application program execution means that a memory location in said second group is referred to by a memory location in the first group (ie the first group location now points to the second group location).Type: GrantFiled: October 18, 2006Date of Patent: February 9, 2010Assignee: Waratek Pty, Ltd.Inventor: John Matthew Holt
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Patent number: 7653909Abstract: An operating system in a shared processor logical partitioned data processing system is given a target percentage. The hypervisor assigns the target processor percentage to the operating system. The operating system also has a predetermined time slice to allot to threads in a multitasking environment. The operating system adjusts the time slice based on a per-virtual-processor percentage.Type: GrantFiled: January 22, 2008Date of Patent: January 26, 2010Assignee: International Business Machines CorporationInventor: Larry Bert Brenner
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Patent number: 7650386Abstract: A computing device having partitions, and a method of communicating between partitions, are disclosed wherein each partition comprises at least one address area readable but not writable from the other of the at least two partitions. In one embodiment one partition sends to the other partition a request for information, which information is in the other partition in an address area not accessible to the one partition, the other partition copies the information to an address area accessible to the one partition, and the one partition reads the information from the accessible address area. In another embodiment the at least one accessible address area of each partition includes a data area and a consumer pointer indicating the position to which that partition has read the data area in another partition.Type: GrantFiled: July 29, 2004Date of Patent: January 19, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Larry N. McMahan, Gary Belgrave Gostin, Joe P. Cowan, Michael R. Krause
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Patent number: 7650466Abstract: A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.Type: GrantFiled: September 21, 2005Date of Patent: January 19, 2010Assignee: QUALCOMM IncorporatedInventors: Brian Michael Stempel, James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius, Rodney Wayne Smith, Robert Douglas Clancy, Victor Roberts Augsburg
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Patent number: 7647471Abstract: A method for processing using a shared file that includes creating a plurality of mmaps between a shared file and a plurality of address spaces, wherein each of the plurality of mmaps maps at least a portion of the shared file to one of the plurality of address spaces, and wherein each of the plurality of address spaces is associated with one of a plurality of processors, transferring, in parallel, data between the shared file and the address spaces using the plurality of mmaps associated with the plurality of address spaces, processing the data in parallel by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.Type: GrantFiled: November 17, 2006Date of Patent: January 12, 2010Assignee: Sun Microsystems, Inc.Inventors: Andrew B. Hastings, Alok N. Choudhary, Harriet G. Coverston
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Patent number: 7644433Abstract: An interactive client-server authentication system and method are based on Random Partial Pattern Recognition algorithm (RPPR). In RPPR, an ordered set of data fields is stored for a client to be authenticated in secure memory. An authentication server presents a clue to the client via a communication medium, such positions in the ordered set of a random subset of data fields from the ordered set. The client enters input data in multiple fields according to the clue, and the server accepts the input data from the client via a data communication medium. The input data corresponds to the field contents for the data fields at the identified positions of the random subset of data fields. The server then determines whether the input data matches the field contents of corresponding data fields in a random subset.Type: GrantFiled: December 23, 2002Date of Patent: January 5, 2010Assignee: Authernative, Inc.Inventor: Len L. Mizrah
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Patent number: 7644092Abstract: A file management system comprises a free-cluster queue describing cluster information indicating a cluster of a memory device in which “data has not been deleted yet but a file will be written preferentially only when a file write request is received”; means deleting, via a preferential input/output request queue in a driver, management information of data according to a deletion request for a file; means selecting either a non-preferential input/output request queue or the free-cluster queue to which the cluster information of the cluster in which the file whose management information has been deleted; means setting the cluster information of the data to which the deletion request is given, to either the non-preferential input/output request queue or the free-cluster queue, depending on selected results; and means providing the cluster information set in the free-cluster queue to a preferential input/output request queue of the driver, when a predetermined event occurs.Type: GrantFiled: May 3, 2005Date of Patent: January 5, 2010Assignees: Kabushiki Kaisha Toshiba, Toshiba TEC Kabushiki KaishaInventor: Yasunori Sato
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Patent number: 7644252Abstract: A multiprocessor system includes a plurality of microprocessors configured to operate on a plurality of operating systems, respectively, and a memory section configured to have a plurality of memory spaces respectively allocated to the plurality of microprocessors. Each of the plurality of microprocessors may include a translation look-aside buffer (TLB) and a page table register. The TLB stores a copy of at least a part of data of one of the plurality of memory spaces corresponding to the microprocessor, and the copy includes a relation of each of virtual addresses of a virtual address space and a corresponding physical address of a physical address space as the memory space. The page table register refers to the TLB in response to an execution virtual address generated based on an application program to be executed by the microprocessor to determine an execution physical address corresponding to the execution virtual address.Type: GrantFiled: October 31, 2007Date of Patent: January 5, 2010Assignee: NEC CorporationInventor: Eiichiro Kawaguchi