Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

Abstract: A method for reconfigurable caching is disclosed. The method includes receiving a workload including a plurality of requests, classifying a first request of the plurality of requests in a first class, classifying the workload in a second class based on the first class, assigning a priority to the first request based on the first class and the second class, and storing the first request in a cache memory including a plurality of blocks responsive to the first request satisfying a caching condition, the cache memory satisfying a validation condition, and the priority satisfying a priority condition.

Abstract: A method of approximate address shuffling of an array includes receiving an array having an array size and non-null elements located in initial locations. The method includes receiving a pseudo-random function (PRF) key and initializing an output array to null. The method includes shuffling the non-null elements to generate shuffled locations for the non-null elements. The shuffling may include determining an intermediate shuffled location for a first non-null element. If a location in the output array corresponding to the intermediate shuffled location is null, the shuffling may include outputting a shuffled location as the intermediate shuffled location. If not, the shuffling may include generating an updated intermediate shuffled location. The method includes returning the output array having the first non-null element the location in the output array corresponding to the shuffled location.

Abstract: Techniques to manage the transfer of a large number of large files, such as image files, to a centralized location in a reliable fashion, sufficient to enable an object recognition based horticultural feedback loop are disclosed. An image capture device is generally assigned to each plant, where images of each plant are captured frequently and periodically. Image files may be sent directly from an image capture function or via an intermediate server to a cloud based server. On the image capture side, a transfer manager software component determines scheduling image file transfers, fallback routines if a transfer is not imminent, and a notification system reports errors and violations of service level agreements. Alternatively, on the cloud based server side, a transfer manager software component manages file transfers based on available bandwidth, and provides a notification system reporting errors and violations of service level agreements.

Abstract: Methods, computer program products, and systems are presented. The methods include, for instance: obtaining a query for a search result and identifying at least one entity in the query, discovering a facet-entity mapping corresponding to the entity from a knowledgebase. A facet in the facet-entity mapping is a property configured in the knowledgebase and an entity is an instance of the facet. The facet-entity mapping is displayed for the user and the query is searched from content, and the search result presented based on the facet and the entity from the facet-entity mapping.

Abstract: A memory module, such as an NVDIMM receives access requests from a master device at a memory port requesting information from a volatile memory of the memory module. In response to receiving a save operation command at a command port, such as during a power failure, the memory module transfers the information stored at the volatile memory to a nonvolatile memory of the memory module based upon a programmable transfer rate.

Abstract: A memory controller uses a history of the rows accessed by commands from a command queue in a command queue circuit to predict whether a second access performed immediately after the command queue becomes empty will be to a same row as a first access performed immediately before the command queue became empty. When the second access is predicted to be to a different row, the row corresponding to the first access is closed in response to the command queue becoming empty. When the second access is predicted to be to the same row, the row corresponding to the first access is not closed in response to the command queue becoming empty.

Abstract: A memory control method uses a memory including a plurality of bank groups each having a plurality of banks. The memory control method includes masking write control data and read control data based on an inside-bank group constraint period that is a command to command interval during which a processing is restricted inside an identical bank group and an inter-bank group constraint period that is a command to command interval during which a processing is restricted inside different bank groups, and storing an unmasked command in an arbitration queue. An arbitration raises a priority order of control data requesting a processing on the bank group that has been accessed last among the plurality of bank groups.

Abstract: Embodiments of the present disclosure provide a method, an apparatus and a computer program product for managing an input/output (I/O). The method comprises, in response to receiving a first I/O request of a first type for a storage device, determining whether there exists at least one credit available to the first type of I/O requests. Each of the at least one credit indicates I/O processing capability reserved by the storage device for the first type of I/O requests. The method further comprises allocating a first credit to the first I/O request based on a result of the determining. The method further comprises performing, by using the first credit, an I/O operation requested by the first I/O request on the storage device. Moreover, the method further comprises, in response to completion of the I/O operation, recycling the first credit for use by a subsequent I/O request. Embodiments of the present disclosure can implement dynamic allocation of I/O processing capability for different types of I/Os.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include a memory device configured to perform read operations and write operations, and a controller configured to control the memory device such that tasks received from a host are queued based on priorities thereof, and the read operations or the write operations corresponding to the tasks are executed according to a sequence of the queued tasks. The controller may divide the plurality of tasks into a plurality of types, assign different aging weights to the queued tasks depending on the respective types, accumulate an aging weight of an executed task of the queued tasks to a starvation state determination value of each of residual tasks of the queued tasks, and determine whether each of the residual tasks is in a starvation state using the corresponding starvation state determination value.

Abstract: A method for improving write throughput of a storage device includes receiving a data access command targeting an LBA extent and determining that logical execution of the data access command includes reading or writing data logically across an identified high-performance-cost boundary. Responsive to the determination, the data access command is split into two or more separate data access commands that are separately queued in memory for execution.

Abstract: Method and apparatus for stopping completions using stop codes in an instruction completion table are provided by during a first clock cycle, in response to determining that a given entry in an Instruction Completion Table (ICT) is finalized and is associated with a stop code, completing, according to a program order, instructions included in one or more finalized entries of the ICT located in the ICT before the given entry; during a second clock cycle, after completing the instructions, performing exception processing for a special instruction included in the given entry; and during a third clock cycle, after processing the special instruction, completing, according to the program order, additional instructions in one or more finalized entries located in the ICT after the given entry.

Abstract: The present disclosure is directed to accelerator circuitry useful in a network applications, such as cloud-based radio access networks. The accelerator circuitry includes interface circuitry that couples the accelerator circuitry to each of a plurality of processor circuits and to system memory circuitry. The accelerator circuitry also includes queue management circuitry, local storage circuitry, direct memory access (DMA) circuitry, and a plurality of accelerator circuits. In operation, the processor circuit communicates a message to the queue management circuitry. The message includes pointer data and prioritized data. The queue management circuitry enqueues the message in one of a plurality of queues. The DMA circuitry receives the message and locates a descriptor at the address designed by the pointer. The DMA circuitry retrieves input data, selects an accelerator circuit, and provides the input data to the selected accelerator circuit.

Abstract: A data processing system archives local snapshots of a primary storage object to cloud storage by dividing an address space of the snapshots into sequential chunks, and organizing the cloud storage into archived snapshots including sets of cloud objects created from respective modified chunks of local snapshots. The archived snapshots are organized into families each having a full snapshot and incremental snapshots. A new family is started by creating a synthesized full snapshot from the archived snapshots of a preceding family, which includes (1) for chunks whose data is contained within one cloud object of the preceding family, logically incorporating the cloud object into the synthesized full snapshot, and (2) for chunks whose data is contained within multiple cloud objects of the preceding family, coalescing the data of the cloud objects into a new cloud object and logically incorporating the new cloud object into the synthesized full snapshot.

Abstract: Technologies for prioritized execution of storage commands by a data storage device include determining a priority of storage commands issued by a host and adding the storage commands to a queue of the data storage device based on the determined priority of the storage command. For example, the storage command issued by the host may be divided into sub-commands and added to a storage sub-command queue of the data storage device based on the determined priority of the storage command. The priority of the storage commands may be determined based on any suitable criteria including, for example, the host storage command queue storing the storage command, metadata associated with the storage command, the type or size of the storage command, and/or other aspects of the storage command, the host, and/or the data storage device.

Abstract: The disclosure provides a processor, comprising at least one core. The core comprises an input buffer, a logic unit having an input and an output, wherein the input is in communication with the input buffer, and a memory unit in communication with the output of the logic unit. The processor also comprises a CU (Control Unit) configured to direct the operation of the core and a communication bus configured to interconnect the core and the CU. The CU is configured to direct the operation of the core by providing: an instruction to the core, wherein the instruction is loaded into the logic unit and writing to the input buffer a value stored in the memory unit of one of the cores; and an output of the instruction based at least partially on the value in the input buffer, and writing the output of the instruction to the memory unit.

Abstract: Disclosed is a memory controller including a command decoder suitable for generating a data identifier of read data by decoding a read command, an update unit suitable for updating information of the read data in response to the data identifier of the read data, and a data output control unit suitable for storing data read from a memory device according to the read command, and selectively outputting the stored data as the read data based on the updated information.

Abstract: A memory system may include: a memory device; and a controller suitable for: receiving a plurality of commands from a host; performing command operations corresponding to the commands to the memory device; providing operation results of the command operations to the host; and performing processing results including processing receptions of the commands, requests for performing the command operations and operation results for the command operations at a regular time duration interval.

Abstract: A data management method and a storage controller are provided. The method includes: receiving write sectors corresponding to a write command and transmitting the write sectors to a partial block buffer or a full block buffer; when the write sectors corresponding to a first block are transmitted to the partial block buffer, starting a timer corresponding to the first block; when the partial block buffer receives first write sectors corresponding to the first block and the first write sectors and the write sectors corresponding to the first block in the partial block buffer form a full first block, the first block is transmitted to the full block buffer before or when the timer is expired; and when the timer is expired and the full first block is not yet formed in the partial block buffer, performing a read-modify-write operation according to the write sectors corresponding to the first block.

Abstract: A method includes maintaining, by a storage unit, a plurality of source name based addressing maps regarding encoding data slice storage by a plurality of storage units. The method further includes receiving, by the storage unit, an access request for an encoded data slice having a source name corresponding to a DSN address. The method further includes accessing, by the storage unit, the source name based address maps to determine whether the encoded data slice is effected by the DAP redistribution operation. The method further includes, when the encoded data slice is effected by the DAP redistribution operation, determining, by the storage unit, to execute the access request, proxy the access request, or deny the access request. The method further includes, when the determination is to execute the access request, executing, by the storage unit, the access request for the encoded data slice.

Abstract: A storage control device includes circuitry configured to acquire status information indicating a load status and a response status of each of one or more storage devices from the one or more storage devices which are accessed in response to a request transmitted from a host device, detect a first storage device having a load no more than a first threshold value and a response time no less than a second threshold value from the one or more storage devices on the basis of the acquired status information, and execute redundant copy of the detected first storage device.

Abstract: A computer program product, system, and method for determining a list of objects, within source storage, to migrate; generating a chunk layout for the objects to migrate; and for each unencoded chunk within the chunk layout: retrieving objects from source storage specified by the unencoded chunk within the chunk layout; generating data and coded fragments for the unencoded chunk using the retrieved objects; and storing the data and coded fragments to primary storage.

Abstract: A device including an address extraction for a data burst associated with a host processor and to map the data burst to a memory according to a rotation is provided. The device includes a splitter to separate a first command that associates the data burst with a first round in the rotation, and a selection logic to select, from the first round in the rotation, a first bank group at the address in the memory to execute the first command, and execution logic to receive the data burst and the address in the memory to activate the first bank group at the address in the memory, and to schedule an execution of the first command based on an availability of a second bank group from the first round in the rotation. A system and a non-transitory computer readable medium storing instructions to use the device are also provided.

Abstract: A data storage device includes a storage medium including a plurality of logical units; and a controller suitable for accessing the storage medium by logical unit, the controller comprising: a first processor suitable for aligning tasks corresponding to at least one logical unit among the plurality of logical units, depending on a priority; and a second processor suitable for accessing other logical units among the plurality of logical units, wherein the first processor entrusts a task alignment operation for the other logical units, to the second processor, based on workloads of the first and second processors.

Abstract: A system includes processing nodes and shared memory. Each processing node includes a processor and local memory. The local memory of each processing node stores at least a partial copy of the immutable data stage of a dataset. The shared memory is accessible by each processing node and stores a sole copy of the mutable data stage of the dataset and a master copy of the immutable data stage of a dataset.

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

Abstract: A register clock driver for a DDR5 memory is presented. A register clock driver (RCD) can include a logic having one or more input channels, each of the one or more input channels receiving input signals; and a plurality of ranked output ports associated with each of the one or more input channels, the logic providing the input signals received on each of the one or more input channels to the associated plurality of ranked output ports according to control signals. The RCD can operate in a default mode, wherein input signals from the input channels are output to both of the output ports associated with that channel, or can operate in a non-default mode where input signals from the input channels are sent to the appropriate ranked output port associated with that channel. In either case, unused signaling on the output ports is held high.

Abstract: Prioritizing items based on user activity includes determining a user interest based on a current user activity and prioritizing items in a list presented in a display based on the user interest.

Abstract: Scheduling memory operations using bank groups including receiving, by a sequencing engine in a memory controller, a set of operations targeting locations in a memory device, wherein the memory device comprises a plurality of bank groups; determining, by the sequencing engine, a targeted bank group of each of the set of operations; selecting, by the sequencing engine, one of the set of operations based on the targeted bank group of each of the set of operations and a bank group of a previously sent operation; and sending, by the sequencing engine, the selected one of the set of operations to the memory device.

Abstract: Non-volatile memory block management. A method according to one embodiment includes calculating an error count margin threshold for each of the at least some non-volatile memory blocks of a plurality of non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded.

Abstract: Aspects of the disclosure provide methods and apparatus that monitor and mitigate Read Disturb errors in non-volatile memory (NVM) devices such as NAND flash memories. The disclosed methods and apparatus determine which logical block addresses (LBAs) in the NVM device are frequently accessed by a host, rather than looking a physical address accesses. The potential Read Disturb errors may then be mitigated by triggering Read Disturb mitigation when the numbers of access of one or more of the frequently accessed LBAs exceeds a predefined number of accesses.

Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit. Accordingly, waste of system resource in the data merging procedure may be reduced.

Abstract: Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein. A memory controller can receive instructions from a host device, determine an initial priority for each instruction using QoS parameters, and allocate the received instructions to the number of memory dies using the initial priority. The memory controller can maintain separate schedules for each of the number or memory dies, update the initial priority for each instruction with the separate schedules, and maintain each of the separate schedules using the updated priority for each instruction in the respective separate schedule.

Abstract: Systems and methods for fast execution of in-capsule commands are disclosed. NVM Express (NVMe) over fabrics is a standard in which a host device sends commands in a command capsule to a memory device. The memory device then saves the command capsule as an entry to a submission queue, and thereafter fetches the command capsule from the submission queue for execution. In certain instances, such as when the command capsule includes a write command, the memory device may decide to by-pass the submission queue and instead begin execution of the command without fetching the command from the submission queue. In these instances of bypassing, the memory device may instead insert a no-operation entry in the submission queue. Further, the memory device may send a response capsule prior to beginning execution of the command.

Abstract: A communication device includes a reception unit configured to receive data transmitted from another communication device in response to a notification indicating an amount of data allowed to be transmitted, a storage unit configured to store the received data in a storage area, a determination unit configured to determine whether or not another buffer can be secured, in addition to a reception buffer having a capacity reserved upon establishment of a logical communication path between the communication device and the another communication device, the another buffer being configured to store data that cannot be stored in the reception buffer among the received data, a decision unit configured to decide the amount of data allowed to be transmitted from the another communication device based on a result of the determination, and a notification unit configured to send, to the other communication device, a notification indicating the decided amount of data.

Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.

Abstract: A processor includes a decode unit to decode a memory copy instruction that indicates a start of a source memory operand, a start of a destination memory operand, and an initial amount of data to be copied from the source memory operand to the destination memory operand. An execution unit, in response to the memory copy instruction, is to copy a first portion of data from the source memory operand to the destination memory operand before an interruption. A descending copy direction is to be used when the source and destination memory operands overlap. In response to the interruption, when the descending copy direction is used, the execution unit is to store a remaining amount of data to be copied, but is not to indicate a different start of the source memory operand, and is not to indicate a different start of the destination memory operand.

Abstract: A method of operating a storage controller, for controlling a garbage collection operation so that blocks included in a non-volatile memory satisfy reuse constraints, includes determining whether the number of free blocks among the blocks is smaller than a first reference value for triggering a garbage collection operation and performing the garbage collection operation on the blocks until the number of free blocks is equal to a second reference value larger than the first reference value according to a result of the determination.

Abstract: Embodiments of the invention include a machine-readable medium having stored thereon instructions, which if performed by a machine causes the machine to perform a method that includes assigning an urgency of requests based on a priority level for incoming requests and associated entries in at least one priority queue, assigning an urgency delta for anti-starvation that indicates urgency promotion to prevent starvation for the incoming requests in the at least one priority queue, determining conflict information including whether an incoming request is dependent on any request already present in the at least one queue, determining all contending requests within the at least one priority queue during a cycle, and sending a selected contending request to a memory controller for accessing memory.

Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.

Abstract: A memory device and associated techniques for optimizing the channel boosting level in an unselected NAND string during a read operation for a selected NAND string. A tracking circuit tracks an indicator of a floating voltage of unselected word lines of a block. For example, this can include tracking a time since a last sensing operation, and determining whether a power on event has occurred without a subsequent sensing operation. In response to a read command, the indicator is used to set parameters in the read operation which can reduce disturbs. This can include setting a duration and/or a magnitude of a select gate voltage pulse during the increase of the voltage of the unselected word lines. The duration and/or a magnitude of the control gate voltage pulse can also be set based on a temperature.

Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.

Abstract: The present invention discloses a distributed system and a data operation method thereof. The system comprises a client, a master node, a plurality of storage nodes and a plurality of computing nodes. The client is configured to send a data operation request to the master node. The master node is configured to respond to the client's request, acquire a storage node list, and then send the storage node list to the client. The plurality of storage nodes are configured to store data requested by the client for operation. The plurality of computing nodes are configured to execute a computing task allocated by the master node based on the client's data operation request. For acquiring the storage node list, the master node employs a copy location selection policy to select a storage node corresponding to a data copy.

Abstract: Apparatus, for performing decoding tasks in a NAND Flash memory controller, includes a first task queue for queuing decoding tasks of a first priority, a second task queue for queuing decoding tasks of a second priority higher than the first priority, and control circuitry that, on receipt of portions of data for a plurality of decoding tasks, releases, from the first and second task queues, respective decoding tasks to operate on respective portions of data, according to priorities of the decoding tasks. First and second decoders operate under first and second decoding schemes that differ in speed or complexity. Input switching circuitry controllably connects each data channel to the first or second decoder. Decoder-done control circuitry selects output of the first or second decoder upon receipt of a decoder-done signal from the first or second decoder. Completed decoding tasks are queued in first and second task-done queues according to priority.

Abstract: Provided are techniques for code load processing. While performing code load processing of a set of modules of a same module type, it is determined that a first module in the set of modules is not in an operational state. It is determined that a second module is a redundant module for the first module. In response to determining that the second module is in an operational state and has already completed code update, the code load processing is continued. In response to determining that the second module is in an operational state and has not already completed code update, it is determined whether there is a third redundant module that is in an operational state. In response to determining that there is a third redundant module that is in an operational state, the code load processing is continued.

Abstract: A system includes a memory, a cache including multiple cache lines; and a processor. The processor may be configured to retrieve, from a first cache line, a first instruction to store data in a memory location at an address in the memory. The processor may be configured to retrieve, from a second cache line, a second instruction to read the memory location at the address in the memory. The second instruction may be retrieved after the first instruction. The processor may be configured to execute the second instruction at a first time dependent upon a value of a first entry in a table, wherein the first entry is selected dependent upon a value in the second cache line. The processor may be configured to execute the first instruction at a second time, after the first time, and invalidate the second instruction at a third time, after the second time.

Abstract: In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed.

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

Abstract: A method, a computer, and an apparatus for migrating memory data, where after receiving a first trigger instruction, a processor may exit an operating system and execute a memory data migration instruction of a basic input/output system, where the memory data migration instruction of the basic input/output system enables the processor to determine a source memory card of to-be-migrated memory data, determine a backup memory card for the source memory card, and instruct a memory controller of the source memory card to migrate the memory data in order to enable the memory controller of the source memory card to read the memory data of the source memory card and write the read memory data of the source memory card into the backup memory card according to an instruction of the processor.

Abstract: A method for rendering a scene across N number of processors is provided. The method includes evaluating performance statistics for each of the processors and establishing load rendering boundaries for each of the processors, the boundaries defining a respective portion of the scene. The method also includes dynamically adjusting the boundaries based upon the establishing and the evaluating.