Prioritizing Patents (Class 711/158)
  • Patent number: 9122506
    Abstract: A virtualization apparatus and a method for controlling the same. In a method for controlling a virtualization apparatus including a plurality of domains, a sub domain transmits an input/output (IO) request for a hardware device to a main domain, and the main domain controls whether or not the IO request accesses the hardware device according to a resource needed to perform the IO request.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: September 1, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-min Lee, Bok-deuk Jeong, Sang-bum Suh
  • Patent number: 9116814
    Abstract: A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: August 25, 2015
    Assignee: Juniper Networks, Inc.
    Inventors: Jianhui Huang, Sharada Yeluri, Jean-Marc Frailong, Jeffrey G. Libby, Anurag P. Gupta, Paul Coelho
  • Patent number: 9104336
    Abstract: Systems capable of transformation of logical data objects for storage and methods of operating thereof are provided. One method includes identifying among a plurality of requests addressed to the storage device two or more “write” requests addressed to the same logical data object, deriving data chunks corresponding to identified “write” requests and transforming the derived data chunks, grouping the transformed data chunks in accordance with the order the requests have been received and in accordance with a predefined criteria, generating a grouped “write” request to the storage device, and providing mapping in a manner facilitating one-to-one relationship between the data in the obtained data chunks and the data to be read from the transformed logical object. The method further includes obtaining an acknowledging response from the storage device, multiplying the obtained acknowledging response, and sending respective acknowledgements to each source that initiated each respective “write” request.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ori Shalev, Jonathan Amit
  • Patent number: 9104888
    Abstract: Methods and systems for obscuring the location of critical system files are provided. In particular, the locations of files stored within a file system are selected by applying various inputs to a hash algorithm. For system files, the inputs applied to the hash algorithm can include a user name and password. For data files, the information provided to the hash algorithm can include the file name. In addition to providing random file locations, a file system in accordance with embodiments of the present invention can homogenize other information, including file names, sizes and creation dates.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: August 11, 2015
    Assignee: ABSIO CORPORATION
    Inventors: James Robert Oltmans, Benjamin E. Zweber
  • Patent number: 9098419
    Abstract: A data storage system can automatically improve the layout of data blocks on a mass storage subsystem by collecting optimization information during both read and write activities, then processing the optimization information to limit the impact of optimization activities on the system's response to client requests. Processing read-path optimization information and write-path optimization information through shared rate-limiting logic simplifies system administration and promotes phased implementation, which can reduce the difficulty of developing a self-optimizing storage server.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: August 4, 2015
    Assignee: NetApp, Inc.
    Inventor: Robert L. Fair
  • Patent number: 9098208
    Abstract: Systems capable of transformation of logical data objects for storage and methods of operating thereof are provided. One method includes identifying among a plurality of requests addressed to the storage device two or more “write” requests addressed to the same logical data object, deriving data chunks corresponding to identified “write” requests and transforming the derived data chunks, grouping the transformed data chunks in accordance with the order the requests have been received and in accordance with a predefined criteria, generating a grouped “write” request to the storage device, and providing mapping in a manner facilitating one-to-one relationship between the data in the obtained data chunks and the data to be read from the transformed logical object. The method further includes obtaining an acknowledging response from the storage device, multiplying the obtained acknowledging response, and sending respective acknowledgements to each source that initiated each respective “write” request.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: August 4, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ori Shalev, Jonathan Amit
  • Patent number: 9098520
    Abstract: The subject matter discloses a method for handling a data object. The method comprises the steps of storing a pointer to a physical location of the data object in a first data repository; associating, in the first data repository, the pointer with a logical location of the data object; receiving an event indicating a blocking of a user access to the data object; retrieving the pointer from the first data repository as a result of the receiving of the event; accessing the physical location by using the retrieved pointer; and copying the data object from the physical location to a second data repository, thereby enabling the restoring of said data object.
    Type: Grant
    Filed: January 20, 2013
    Date of Patent: August 4, 2015
    Assignee: BALOOTA APPLICATIONS LTD.
    Inventors: Shahar Levinshtein, Alexander Hochner
  • Patent number: 9092305
    Abstract: In one embodiment, a circuit for communicating with a memory is provided. The circuit includes a sorting circuit configured to receive a plurality of read and write transactions. The sorting circuit sorts the write transactions according to respective sizes of data to be written to the memory, and sorts the read transactions according to respective sizes of data to be read from the memory. A selection circuit is configured to select transactions for transmission to the memory, from the sorted read and write transactions, in an order that balances a quantity of data to be written to the memory over a first serial data link with a quantity of data to be read from the memory over a second serial data link. A transmitter is coupled to the selection circuit and is configured to transmit the selected transactions to the memory device on a serial data link.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: July 28, 2015
    Assignee: XILINX, INC.
    Inventors: Michaela Blott, Hamish T. Fallside
  • Patent number: 9075538
    Abstract: A data storage device may generally be directed to a buffer that stores a plurality of command requests pending for a data storage medium and a processor that is configured to skip a first command request and execute a second command request in response to the second command request having an access latency within a first predetermined performance impact range and a power consumption within a second predetermined power savings range compared to the first command request.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 7, 2015
    Assignee: Seagate Technology LLC
    Inventors: Christopher Ryan Fulkerson, Lingzhi Yang, Kenneth Lawrence Barham
  • Patent number: 9043512
    Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: May 26, 2015
    Assignee: Google Inc.
    Inventor: Arif Merchant
  • Patent number: 9043530
    Abstract: Among other things, one or more techniques and/or systems are provided for storing data within a hybrid storage aggregate comprising a lower-latency storage tier and a higher-latency storage tier. In particular, frequently accessed data, randomly accessed data, and/or short lived data may be stored (e.g., read caching and/or write caching) within the lower-latency storage tier. Infrequently accessed data and/or sequentially accessed data may be stored within the higher-latency storage tier. Because the hybrid storage aggregate may comprise a single logical container derived from the higher-latency storage tier and the lower-latency storage tier, additional storage and/or file system functionality may be implemented across the storage tiers. For example, deduplication functionality, caching functionality, backup/restore functionality, and/or other functionality may be provided through a single file system (or other type of arrangement) and/or a cache map implemented within the hybrid storage aggregate.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: May 26, 2015
    Assignee: NetApp, Inc.
    Inventors: Rajesh Sundaram, Douglas Paul Doucette, David Grunwald, Jeffrey S. Kimmel, Ashish Prakash
  • Patent number: 9037827
    Abstract: A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, John Hayes, Bo Hong, Feng Wang, Ethan Miller, Craig Harmer
  • Patent number: 9032155
    Abstract: A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: May 12, 2015
    Assignee: Parallel Networks, LLC
    Inventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters
  • Patent number: 9032156
    Abstract: For each access request received at a shared cache of the data processing device, a memory access pattern (MAP) monitor predicts which of the memory banks, and corresponding row buffers, would be accessed by the access request if the requesting thread were the only thread executing at the data processing device. By recording predicted accesses over time for a number of access requests, the MAP monitor develops a pattern of predicted memory accesses by executing threads. The pattern can be employed to assign resources at the shared cache, thereby managing memory more efficiently.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jaewoong Chung, Shekhar Srikantaiah, Lisa Hsu
  • Patent number: 9026748
    Abstract: A method of storage access scheduling for a memory device for a workload of different priority access requests including access requests having a real-time priority. The method includes characterizing the memory device including determining a balanced number (N) of concurrent access requests associated with a concurrent access maximum throughput associated with the memory device. The method also includes characterizing the workload. The method also includes receiving a real-time access request associated with an access request storage location value. The method also includes processing the real-time access request, utilizing a processor, based on the access request storage location value and the values obtained from characterizing the memory device and the workload.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: May 5, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Carl Staelin, Gidi Amir, Ram Dagan, David Ben Ovadia, Michael Melamed, David Edward Staas
  • Publication number: 20150121020
    Abstract: A storage apparatus includes a processor. The processor calculates an upper limit of an input/output processing amount, which is determined based on priority levels set to a plurality of storage devices, for each storage device. The processor schedules an execution sequence of processes relating to input/output requests received from information processing apparatuses based on processing amounts relating to the input/output requests and the upper limits. The processor executes the processes relating to the input/output requests in the scheduled execution sequence. The processor is configured to determine, for each storage device, whether or not a processing amount of the storage device exceeds a processing bandwidth of the each storage device for a first predetermined time. The processor changes the upper limit for each storage device in a predetermined bandwidth accommodation unit in a case where the processing amount for each storage device is determined to exceed the processing bandwidth.
    Type: Application
    Filed: September 23, 2014
    Publication date: April 30, 2015
    Inventor: Joichi Bita
  • Patent number: 9021178
    Abstract: Embodiments of solid-state storage system are provided herein which reduce processing delays for performance-sensitive commands. These performance-sensitive commands are typically read-write commands which can be transferred to the storage media by a high performance path to optimize responsiveness to the host. This high performance path can be enabled and disabled to prevent conflicts with commands processed via a low performance path.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: April 28, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventor: Chandra M. Guda
  • Patent number: 9020490
    Abstract: A method and caching server for enabling caching of a portion of a media file in a User Equipment (UE) in a mobile telecommunications network. The caching server selects the media file and determines a size of the portion to be cached in the UE. The size may be determined depending on radio network conditions for the UE and/or characteristics of the media file. The caching server sends an instruction to the UE to cache the determined size of the portion of the media file in the UE.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: April 28, 2015
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventors: Andras Valkó, Catalin Meirosu, Zoltán Turányi
  • Patent number: 9021219
    Abstract: Embodiments of the invention relate to cluster-centric tiered storage with a flexible tier definition to support performance of transactions. Object data is distributed in a multi-tiered shared-nothing cluster. Hierarchical tiers of data storage are assigned different roles within the hierarchy. The tiers are managed globally across the cluster and objects are placed in tiers according to a flexible tier definition. The probability of object access is computed for objects, and objects are moved to different tiers responsive to the computation to minimize system runtime. The location of an object is further optimized in response to an access request.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Karan Gupta, Himabindu Pucha, Prasenjit Sarkar
  • Patent number: 9015422
    Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetcher in which patterns may include wild cards for some cache blocks. The wild card may match any access for the corresponding cache block (e.g. no access, demand access, prefetch, successful prefetch, etc.). Furthermore, patterns with irregular strides and/or irregular access patterns may be included in the matching patterns and may be detected for prefetch generation. In an embodiment, the AMPM prefetcher may implement a chained access map for large streaming prefetches. If a stream is detected, the AMPM prefetcher may allocate a pair of map entries for the stream and may reuse the pair for subsequent access map regions within the stream. In some embodiments, a quality factor may be associated with each access map and may control the rate of prefetch generation.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: April 21, 2015
    Assignee: Apple Inc.
    Inventors: Stephan G. Meier, Gerard R. Williams, III, Hari S. Kannan, Pavlos Konas
  • Publication number: 20150106578
    Abstract: Systems, methods and devices for monitoring data transactions in a data storage system, the data storage system being in network communication with a plurality of storage resources and comprising at least a data analysis module and a logging module, and receiving at the data analysis module at least one data transaction for data in the data storage system, each data transaction having at least one data-related characteristic; storing in the logging module the at least one data-related characteristic and a data transaction identifier that relates the data transaction to the associated at least one data-related characteristic in the logging module; analyzing at the data analysis module at least one data-related characteristic related to a first data transaction to determine if the first data transaction shares at least one data-related characteristic with other data transactions; and, in cases where the first data transaction shares at least one data-related characteristic with at least one other data transacti
    Type: Application
    Filed: October 15, 2014
    Publication date: April 16, 2015
    Inventors: Andrew Warfield, Jacob Taylor Wires, Stephen Frowe Ingram
  • Patent number: 9003135
    Abstract: Embodiments of the inventions relate to granular management of data storage blocks in a data storage system. In one aspect, status values are employed to track “used”, “free”, and “claimed free” storage blocks. A storage block having stored data is identified as used, a storage block available to store data is identified as free, and a storage block having previously stored data removed that has not been reclaimed is identified as claimed free. These values are maintained on a map to track each data block within the data storage system. Available claimed free data blocks are prioritized for data block allocation over available free data blocks for efficient storage, including enabling efficient reclamation of data blocks and minimizing data movement needed for reclamation-oriented de-fragmentation.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Leo S. Luan, Frank B. Schmuck
  • Patent number: 8996789
    Abstract: Modified tracks for write requests to a sequential access storage medium in a sequential access storage device are cached in a non-volatile storage, which is a faster access device than the sequential access storage medium. A request queue includes destage requests to destage the modified tracks in the non-volatile storage device to the sequential access storage medium and read requests to access read requested tracks from the sequential access storage medium. A comparison is made of a current position of a read/write mechanism with respect to physical locations on the sequential access storage medium of the tracks subject to the destage requests indicated in the request queue. A determination is made of one of the destage requests to process based on the comparison. The modified track for the determined destage request is written from the non-volatile storage device to the sequential access storage medium.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Lokesh M. Gupta
  • Patent number: 8996824
    Abstract: A method for controlling memory refresh operations in dynamic random access memories. The method includes determining a count of deferred memory refresh operations for a first memory rank. Responsive to the count approaching a high priority threshold, issuing an early high priority refresh notification for the first memory rank, which indicates the pre-determined time for performing a high priority memory refresh operation at the first memory rank. Responsive to the early high priority refresh notification, the behavior of a read reorder queue is dynamically modified to give priority scheduling to at least one read command targeting the first memory rank, and one or more of the at least one read command is executed on the first memory rank according to the priority scheduling. Priority scheduling removes these commands from the re-order queue before the refresh operation is initiated at the first memory rank.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Brittain, John S. Dodson, Stephen Powell, Eric E. Retter, Jeffrey A. Stuecheli
  • Patent number: 8996815
    Abstract: An integrated circuit (IC) may include a cache memory, and a cache memory controller coupled to the cache memory. The cache memory controller may be configured to receive a cache miss associated with a memory location, issue pre-fetch requests, each pre-fetch request having a quality of service (QoS), and determine if a pre-fetch request has issued for the memory location associated with the cache miss.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 31, 2015
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Andrew Michael Jones, Stuart Ryan
  • Patent number: 8996759
    Abstract: A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoiju Chung
  • Patent number: 8990523
    Abstract: A storage apparatus has a controller for controlling data input to and output from a plurality of storage devices composed of flash memories and the controller manages the number of times data are written to each storage device on the basis of each storage device, wherein when the controller receives a write command from an access requestor and if any of the storage devices is a storage device whose number of times of data write exceeds a threshold value, the controller determines that the data write mode is an intensive mode, selects the storage device, whose number of times of data write exceeds the threshold value, as a specified storage device and writes data, which are to be processed for the write command, intensively to the selected specified storage device.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: March 24, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yuri Nozaki, Masanobu Ikeda, Hitoshi Fukuguchi
  • Patent number: 8990522
    Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: March 24, 2015
    Assignee: Imagination Technologies Limited
    Inventors: Adrian J. Anderson, Gary C. Wass, Gareth J. Davies
  • Patent number: 8990521
    Abstract: According to an embodiment, an information processing device that includes a first storage unit and a second storage unit having power consumption different from that of the first storage unit. The information processing device also includes a control unit configured to make a control to determine a priority of information that is to be stored in the first storage unit or the second storage unit. The control unit is configured to store the information into the first storage unit or into the second storage unit based on the determined priority.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Ishihara, Yoshimichi Tanizawa, Kotaro Ise
  • Patent number: 8990498
    Abstract: Embodiments of the present invention provide a system for scheduling memory accesses for one or more memory devices. This system includes a set of queues configured to store memory access requests, wherein each queue is associated with at least one memory bank or memory device in the one or more memory devices. The system also includes a set of hierarchical levels configured to select memory access requests from the set of queues to send to the one or more memory devices, wherein each level in the set of hierarchical levels is configured to perform a different selection operation.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 24, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Vitaly Sukonik, Sarig Livne, Bengt Werdin
  • Patent number: 8990534
    Abstract: A method for resource management of a data processing system is described herein. According to one embodiment, a token is periodically pushed into a memory usage queue, where the token includes a timestamp indicating time entering the memory usage queue. The memory usage queue stores a plurality of memory page identifiers (IDs) identifying a plurality of memory pages currently allocated to a plurality of programs running within the data processing system. In response to a request to reduce memory usage, a token is popped from the memory usage queue. A timestamp of the popped token is then compared with current time to determine whether a memory usage reduction action should be performed.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: March 24, 2015
    Assignee: Apple Inc.
    Inventors: Lionel D. Desai, Neil G. Crane, Damien P. Sorresso, Joseph Sokol, Jr.
  • Publication number: 20150081990
    Abstract: Multiple memory devices, such as hard drives, can be combined and logical partitions can be formed between the drives to allow a user to control regions on the drives that will be used for storing content, and also to provide redundancy of stored content in the event that one of the drives fails. Priority levels can be assigned to content recordings such that higher value content can be stored in more locations and easily accessible locations within the utilized drives. Users can control and organize how recorded content is stored between the drives such that an external drive may be removed from a first gateway device and attached to a second gateway device without losing the ability to access the recorded content from the first gateway device at a later time. In this manner, a user is provided with the ability to transport an external drive containing stored content recordings between multiple different gateway devices such that the recordings may be accessed at different locations or user premises.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 19, 2015
    Inventor: Ross Gilson
  • Patent number: 8984229
    Abstract: A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: March 17, 2015
    Assignee: Parallel Networks, LLC
    Inventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters
  • Patent number: 8984240
    Abstract: Page faults during partition migration from a source computing system to a destination computing system are reduced by assigning each page used by a process as being hot or cold according to their frequency of use by the process. During a live partition migration, the cold or coldest (least frequently used) pages are copied to the destination server first, followed copying the warmer (less frequently used) and concluded by copying the hottest (most frequently used) pages. After all dirtied pages have been refreshed, cutover from the instance on the source server to the destination server is made. By transferring the warm and hot pages last (or later) in the migration process, the number of dirtied pages is reduced, thereby reducing page faults subsequent to the cutover.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Adekunle Bello, Brian W. Hart
  • Publication number: 20150074360
    Abstract: A scheduler controls execution in a memory of operation requests received in an input request set (IRS) by providing a corresponding output request set (ORS). The scheduler includes zone standby units having a one-to-one relationship with corresponding zones such that each zone standby unit stores an operation request. The scheduler also includes an output processing unit that determines a processing sequence for the operation requests stored in the zone standby units to provide the ORS.
    Type: Application
    Filed: November 14, 2014
    Publication date: March 12, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: CHUL LEE
  • Publication number: 20150074359
    Abstract: An electronic apparatus includes: a main storage unit; a first storage unit that stores multiple pieces of first setting information for the main storage unit; a second storage unit that stores second setting information, the second setting information being setting information for the main storage unit and corresponding to at least some of the multiple pieces of first setting information; a setting unit that sets the second setting information with a higher priority than the first setting information; and a control unit that controls the main storage unit based on information set by the setting unit.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 12, 2015
    Applicant: RICOH COMPANY, LIMITED
    Inventor: Yuuki SUNAGAWA
  • Patent number: 8977811
    Abstract: Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a memory device in an optimal fashion, e.g., to maximize bandwidth and/or reduce latency. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: March 10, 2015
    Assignee: Intel Corporation
    Inventors: Philip Abraham, Stanley S. Kulick, Randy B. Osborne
  • Patent number: 8977833
    Abstract: According to one embodiment, a memory system has a data transfer device which includes a first command generating unit, a second command generating unit, a first storage unit, a second storage unit, and a nonvolatile memory managing unit. The first command generator generates a first command for reading out data from a nonvolatile memory to a host apparatus. The second command generator generates a second command for internal processing of the memory system associated with a temporary memory and the nonvolatile memory. The first memory has a queue structure configured to store the first command. The second memory has a queue structure configured to store the second command. The memory manager is configured to read out the first command stored in the first memory in priority to the second command stored in the second memory and to transmit read-out command to the nonvolatile memory.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Kazui, Norikazu Yoshida
  • Publication number: 20150067282
    Abstract: A copy control apparatus includes a processor. The processor is configured to record, in update location information, an update count for each of sectional areas obtained by sectioning a copy-source area. The update count indicates a number of updates of data in a sectional area. The update count is indicative of more than two values. The processor is configured to perform first copy of copying data in the copy-source area to a copy-destination area based on the update location information. The processor is configured to deter the first copy for data in a sectional area for which an update count indicating more than a predetermined number is recorded in the update location information.
    Type: Application
    Filed: July 16, 2014
    Publication date: March 5, 2015
    Applicant: Fujitsu Limited
    Inventor: Naoki Kobayashi
  • Patent number: 8972358
    Abstract: A file storage apparatus comprises: duplication determination unit that determines whether file supplied from client apparatus and file stored in storage unit coincide with each other in same format, and stores the file supplied from client apparatus in the storage unit if the files do not coincide in the same format; and storage management unit that associates, if duplication determination unit determines that the files coincide in the same format, format of the file supplied from the client apparatus with the file stored in the storage unit, reads file stored in the storage unit in response to file read request from client apparatus, converts, if format associated with the read file exists, the read file into the format, and provides the converted file.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: March 3, 2015
    Assignee: NEC Corporation
    Inventor: Satoshi Yamakawa
  • Patent number: 8972647
    Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to a hypervisor; allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Keerthi B. Kumar, Shailaja Mallya
  • Patent number: 8972676
    Abstract: Provided are a computer program product, system, and method for assigning device adaptors and background tasks to use to copy source extents to target extents in a copy relationship. A relation is provided of a plurality of source extents in source ranks to copy to a plurality of target extents in target ranks in the storage system. One target rank in the relation is used to determine an order in which the target ranks in the relation are selected to register for copying. For each selected target rank in the relation selected according to the determined order, an iteration of a registration operation is performed to register the selected target rank and a selected source rank copied to the selected target rank in the relation.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Theresa M. Brown, Lokesh M. Gupta, Carol S. Mellgren
  • Publication number: 20150058582
    Abstract: According to one embodiment, a method includes determining, using a processor, which physical blocks are priority physical blocks based on at least one of: a number of application blocks referencing the physical block, and a number of accesses to the physical block, creating a reference to each priority physical block, and outputting the reference. According to another embodiment, a method includes receiving a reference to one or more priority physical blocks in a storage pool, and adjusting an amount of redundancy parity encoding for each of the one or more priority physical blocks based on the reference.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Duane M. Baldwin, John T. Olson, Sandeep R. Patil, Riyazahamad M. Shiraguppi
  • Patent number: 8966175
    Abstract: The present invention provides an approach for automatic storage planning and provisioning within a clustered computing environment (e.g., a cloud computing environment). The present invention will receive planning input for a set of storage area network volume controllers (SVCs), the planning input indicating a potential load on the SVCs and its associated components. Configuration data for a set of storage components (i.e., the set of SVCs, a set of managed disk (Mdisk) groups associated with the set of SVCs, and a set of backend storage systems) will also be collected. Based on this configuration data, the set of storage components will be filtered to identify candidate storage components capable of addressing the potential load. Then, performance data for the candidate storage components will be analyzed to identify an SVC and an Mdisk group to address the potential load.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kavita Chavda, David P. Goodman, Sandeep Gopisetty, Larry S. McGimsey, James E. Olson, Aameek Singh
  • Publication number: 20150052318
    Abstract: Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 19, 2015
    Inventor: ROBERT M. WALKER
  • Publication number: 20150046665
    Abstract: Systems, methods and/or devices are used to enable a stale data mechanism. In one aspect, the method includes (1) receiving a write command specifying a logical address to which to write, (2) determining whether a stale flag corresponding to the logical address is set, (3) in accordance with a determination that the stale flag is not set, setting the stale flag and releasing the write command to be processed, and (4) in accordance with a determination that the stale flag is set, detecting an overlap, wherein the overlap indicates two or more outstanding write commands are operating on the same memory space.
    Type: Application
    Filed: July 15, 2014
    Publication date: February 12, 2015
    Inventors: James M. Higgins, Theron W. Virgin
  • Patent number: 8954679
    Abstract: A social data aggregator generates entries of action data describing actions taken by users. A portion of the entries are stored in an action cache to expedite retrieval. To store more recent or relevant entries in the action cache, entries are removed from the action cache based on engagement scores associated with the entries. An engagement score indicates a likelihood of a user requesting content interacting with a notification based on an entry. Entries having the lowest engagement scores or having engagement scores below a threshold are removed from the action cache.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: February 10, 2015
    Assignee: Facebook, Inc.
    Inventors: Sriya Santhanam, Varun Kacholia, Li Zhang
  • Patent number: 8949535
    Abstract: Technology is described for performing cache data invalidations. The method may include identifying cache update information at a first cache. The cache update information may identify a cache entry (e.g., a trending cache entry). A second cache may be selected to receive the cache update information from the first cache. The cache update information identifying the cache entry may be sent from the first cache to the second cache. For example, the second cache may be populated by adding the trending cache entry into the second cache.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Amazon Technologies, Inc.
    Inventor: Jamie Hunter
  • Patent number: 8949566
    Abstract: Methods, apparatuses, and computer program products are provided for locking access to data storage shared by a plurality of compute nodes. Embodiments include maintaining, by a compute node, a queue of requests from requesting compute nodes of the plurality of compute nodes for access to the data storage, wherein possession of the queue represents possession of a mutual-exclusion lock on the data storage, the mutual-exclusion lock indicating exclusive permission for access to the data storage; and conveying, based on the order of requests in the queue, possession of the queue from the compute node to a next requesting compute node when the compute node no longer requires exclusive access to the data storage.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Madhusudanan Kandasamy, Vidya Ranganathan, Murali Vaddagiri
  • Patent number: 8949489
    Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Google Inc.
    Inventor: Arif Merchant