Prioritizing Patents (Class 711/158)
  • Patent number: 8954679
    Abstract: A social data aggregator generates entries of action data describing actions taken by users. A portion of the entries are stored in an action cache to expedite retrieval. To store more recent or relevant entries in the action cache, entries are removed from the action cache based on engagement scores associated with the entries. An engagement score indicates a likelihood of a user requesting content interacting with a notification based on an entry. Entries having the lowest engagement scores or having engagement scores below a threshold are removed from the action cache.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: February 10, 2015
    Assignee: Facebook, Inc.
    Inventors: Sriya Santhanam, Varun Kacholia, Li Zhang
  • Patent number: 8949535
    Abstract: Technology is described for performing cache data invalidations. The method may include identifying cache update information at a first cache. The cache update information may identify a cache entry (e.g., a trending cache entry). A second cache may be selected to receive the cache update information from the first cache. The cache update information identifying the cache entry may be sent from the first cache to the second cache. For example, the second cache may be populated by adding the trending cache entry into the second cache.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Amazon Technologies, Inc.
    Inventor: Jamie Hunter
  • Patent number: 8949566
    Abstract: Methods, apparatuses, and computer program products are provided for locking access to data storage shared by a plurality of compute nodes. Embodiments include maintaining, by a compute node, a queue of requests from requesting compute nodes of the plurality of compute nodes for access to the data storage, wherein possession of the queue represents possession of a mutual-exclusion lock on the data storage, the mutual-exclusion lock indicating exclusive permission for access to the data storage; and conveying, based on the order of requests in the queue, possession of the queue from the compute node to a next requesting compute node when the compute node no longer requires exclusive access to the data storage.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Madhusudanan Kandasamy, Vidya Ranganathan, Murali Vaddagiri
  • Patent number: 8949489
    Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Google Inc.
    Inventor: Arif Merchant
  • Patent number: 8949555
    Abstract: In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Shibabrata Mondal, Ajith Kumar
  • Patent number: 8949845
    Abstract: A resource controller that includes a first buffer configured to store requests of a first predefined category having a first priority. In addition, the resource controller includes at least a second buffer configured to store requests of a second predefined category having a second priority where the first priority is set such that processing requests of the first category has priority over processing the requests of the second category. Also, the resource controller includes a mechanism configured to block the requests of the first category when a predefined condition is met.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: February 3, 2015
    Assignee: Synopsys, Inc.
    Inventors: Elisabeth Francisca Maria Steffens, Tomas Henriksson
  • Publication number: 20150032936
    Abstract: Examples are disclosed for identifying read/write access collisions for a storage medium. In some examples, a plurality of write access requests for access to a storage medium may be received at a controller for a storage medium. The plurality of write access requests may be associated with separate logical block address (LBA) ranges. The separate write LBA ranges may be stored to sets of first registers. A read access request to the storage medium may also be received and a read LBA range associated with the read access request may be stored to a set of second registers. The separate stored write LBA ranges may then be compared to the read LBA range to identify overlapping ranges that may indicate read/write access collisions to the storage medium. Other examples are described and claimed.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Inventors: Jason K. Yu, Jawad B. Khan, Joerg Hartung, Richard P. Mangold
  • Patent number: 8935491
    Abstract: Invented hardware logic based methods and systems enable dynamically allocating and assigning an array of processing cores among instances of software programs, based on at least in part on indications of which instances of the programs are ready-to-execute, wherein such an indication for any given program instance is based at least in part on whether its fast-access memory contents are ready for it to execute without it needing at that time access to memories other than its fast-access memory. The invention also provides hardware logic based mechanisms for automating the updating of the fast-access memories for instances of the programs dynamically sharing the array of cores according to control by the program instances via their associated hardware device registers, including while a given program instance whose fast-access memory contents are being updated is not assigned for execution on any of the cores.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: January 13, 2015
    Assignee: Throughputer, Inc.
    Inventor: Mark Henrik Sandstrom
  • Patent number: 8935490
    Abstract: Providing quality of service levels to a plurality of sources that perform access requests to a disk resource includes providing a disk resource queue containing access requests for the disk resource, providing a source queue for each of the sources containing access requests generated by a corresponding one of the sources, determining if a new access request from a particular source is urgent according to a specified number of I/O operations per second for the particular source and a time since a previous access request from the particular source, adding the new access request to the disk resource queue if the new access request is urgent, and adding the new access request the source queue of the particular source if the new access request is not urgent and the length of the disk resource queue is greater than a predetermined queue depth value.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: January 13, 2015
    Assignee: EMC Corporation
    Inventors: Amnon Naamad, Sachin More
  • Patent number: 8935475
    Abstract: Embodiments of the present invention provides for the execution of threads and/or workitems on multiple processors of a heterogeneous computing system in a manner that they can share data correctly and efficiently. Disclosed method, system, and article of manufacture embodiments include, responsive to an instruction from a sequence of instructions of a work-item, determining an ordering of visibility to other work-items of one or more other data items in relation to a particular data item, and performing at least one cache operation upon at least one of the particular data item or the other data items present in any one or more cache memories in accordance with the determined ordering. The semantics of the instruction includes a memory operation upon the particular data item.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: January 13, 2015
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel, Norman Rubin, Mark Fowler
  • Publication number: 20150006832
    Abstract: Embodiments of the disclosure are directed toward a method, a system, and a computer program product for managing virtual storage access method (VSAM) data sets on performance tiers. The method can be used with VSAM data sets. The method can include determining a usage metric for a particular control area from the plurality of control areas. The method can also include prioritizing the particular control areas based on a determined usage metric. The method can also include assigning a prioritized control area to a performance tier of the plurality of tiers as a function of a prioritization of the particular control area and a performance criteria for the performance tier by moving the prioritized control area to the performance tier and updating an index record that associates the prioritized control area to the performance tier.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Neal E. Bohling, David B. LeGendre, David C. Reed, Max D. Smith
  • Patent number: 8924661
    Abstract: A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.
    Type: Grant
    Filed: January 17, 2010
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Michael Shachar, Barak Rotbard, Oren Golov, Uri Perlmutter, Dotan Sokolov, Julian Vlaiko, Yair Schwartz
  • Patent number: 8924677
    Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: December 30, 2014
    Assignee: Microsoft Corporation
    Inventors: Steve Pronovost, Maxwell Abernethy, Rudolph Balaz, Ameet Chitre
  • Patent number: 8918588
    Abstract: Techniques for replacing one or more blocks in a cache, the one or more blocks being associated with a plurality of data streams, are provided. The one or more blocks in the cache are grouped into one or more groups, each corresponding to one of the plurality of data streams. One or more incoming blocks are received. To free space, the one or more blocks of the one or more groups in the cache are invalidated in accordance with at least one of an inactivity of a given data stream corresponding to the one or more groups and a length of the one or more groups. The one or more incoming blocks are stored in the cache. A number of data streams maintained within the cache is maximized.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian Bass, Giora Biran, Hubertus Franke, Amit Golander, Hao Yu
  • Patent number: 8918596
    Abstract: The systems and methods described herein may be used to implement scalable statistics counters suitable for use in systems that employ a NUMA style memory architecture. The counters may be implemented as data structures that include a count value portion and a node identifier portion. The counters may be accessible within transactions. The node identifier portion may identify a node on which a thread that most recently incremented the counter was executing or one on which a thread that has requested priority to increment the shared counter was executing. Threads executing on identified nodes may have higher priority to increment the counter than other threads. Threads executing on other nodes may delay their attempts to increment the counter, thus encouraging consecutive updates from threads on a single node. Impatient threads may attempt to update the node identifier portion or may update an anti-starvation variable to indicate a request for priority.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 23, 2014
    Assignee: Oracle International Corporation
    Inventors: David Dice, Yosef Lev, Mark S. Moir
  • Patent number: 8918583
    Abstract: An embodiment is a technique to adapt behavior of a solid-state drive (SSD) to extend lifespan of the SSD. Real environmental information is received from an environmental processor. The real environmental information corresponds to an environment of the SSD. A behavior model is selected based on a real environmental model and an internal data usage model. If a new behavior model is selected, the environmental processor is informed about the new behavior model. The environmental processor sends control commands to a power management module to apply new power policy to the SSD. Information on the new behavior model is made available for query. If current behavior model is selected, the current behavior model is maintained.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 23, 2014
    Assignee: Virtium Technology, Inc.
    Inventors: Pho Hoang, Jian Chen
  • Patent number: 8918613
    Abstract: Provided are a storage apparatus and data management method with which the usage ratio of each of the storage tiers is determined beforehand for each virtual volume and data can be managed by being migrated between storage tiers within a range of predetermined usage ratios. A storage apparatus 5, comprising storage devices 30 of a plurality of types of varying performance; and a controller 31 which manages each of storage areas provided by the storage devices 30 of a plurality of types by means of storage tiers ST of a plurality of different types respectively, and which assigns the storage areas in page units to virtual volumes VVOL from any storage tier among the storage tiers ST of a plurality of types, the controller 31 managing usage ratios of the storage tiers ST of a plurality of types and assigning the storage areas in page units to the virtual volumes VVOL based on the usage ratio managed.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: December 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyuki Kato, Masami Maeda, Yutaka Takata
  • Publication number: 20140372715
    Abstract: A memory is made up of multiple pages, and different pages can have different priority levels. A set of memory pages having at least similar priority levels are identified and compressed into an additional set of memory pages having at least similar priority levels. The additional set of memory pages are classified as being the same type of page as the set of memory pages that was compressed (e.g., as memory pages that can be repurposed). Thus, a particular set of memory pages can be compressed into a different set of memory pages of the same type and corresponding to at least similar priority levels. However, due to the compression, the quantity of memory pages into which the set of memory pages is compressed is reduced, thus increasing the amount of data that can be stored in the memory.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Inventors: Yevgeniy M. Bak, Mehmet Iyigun, Landy Wang
  • Patent number: 8914594
    Abstract: A method may be performed in a data storage device that includes a controller, a non-volatile memory, and a volatile memory. The method includes loading a first portion of stored data from the non-volatile memory to the volatile memory according to one or more load priority indicators accessible to the controller. The method further includes, in response to completion of the loading of the first portion of the stored data to the volatile memory and prior to completion of loading a second portion of the stored data to the volatile memory, sending a signal to indicate to a host device operatively coupled to the data storage device that the volatile memory is ready for use by the host device.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 16, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Daniel Zvi Yerushalmi, Yaniv Iarovici
  • Patent number: 8914583
    Abstract: A method, computer program product, and computing system for compartmentalizing a LUN into a plurality of portions that are each assigned to one or more hosts. An ownership tracking structure is maintained for the LUN, wherein the ownership tracking structure includes a data entry associated with each of the plurality of portions within the LUN. One or more properties of the ownership tracking structure are monitored to determine if the ownership tracking structure needs to be compressed. If the ownership tracking structure needs to be compressed, one or more actions are taken to reduce the size of the ownership tracking structure.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: December 16, 2014
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Randall H. Shain
  • Patent number: 8914584
    Abstract: A method for receiving a Mode Select command concerning a LUN from a host. The Mode Select command defines control information and host identifier information concerning the host associated with the Mode Select command. The Mode Select command is processed to determine if the control information included within the Mode Select command signifies an intent by the host to relinquish control of the LUN. If the control information signifies an intent to relinquish control of the LUN, the host identifier information included within the Mode Select command is processed to confirm that it matches LUN control identifier information that defines the host that currently controls the LUN. If the host identifier information matches the LUN control identifier information, at least the control information included within the Mode Select command is written to a buffer associated with the LUN. The buffer includes a control field and a GUID field.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: December 16, 2014
    Assignee: EMC Corporation
    Inventors: Philip Derbeko, Constantine Antonovich, Alexandr Veprinsky, Arieh Don, Kevin Martin
  • Patent number: 8914591
    Abstract: An information processing apparatus processes data to be processed while accessing data to be processed that is stored in a memory or a HDD. The information processing apparatus determines the process content and calculates the access number to the HDD based on the determined process content and the content of data to be processed. The information processing apparatus also decides to store data to be processed in the memory when the access number is more than or equal to a threshold value. The information processing apparatus decides to store data to be processed in the HDD when the access number is less than the threshold value.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: December 16, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiromasa Kawasaki
  • Patent number: 8909874
    Abstract: A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Brittain, John S. Dodson, Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli
  • Patent number: 8909886
    Abstract: A method, computer program product, and computing system for compartmentalizing a LUN into a plurality of portions that are each assigned to one or more hosts. The occurrence of a migration event in which an application being executed on a first host is being migrated to second host may be detected. Any portions within the LUN that are assigned to the application being executed on the first host may be identified, thus generating one or more identified portions. The one or more identified portions may be reassigned to the second host.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: December 9, 2014
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Randall H. Shain
  • Patent number: 8909861
    Abstract: The invention is directed towards a system and method that utilizes external memory devices to cache sectors from a rotating storage device (e.g., a hard drive) to improve system performance. When an external memory device (EMD) is plugged into the computing device or onto a network in which the computing device is connected, the system recognizes the EMD and populates the EMD with disk sectors. The system routes I/O read requests directed to the disk sector to the EMD cache instead of the actual disk sector. The use of EMDs increases performance and productivity on the computing device systems for a fraction of the cost of adding memory to the computing device.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: December 9, 2014
    Assignee: Microsoft Corporation
    Inventors: Alexander Kirshenbaum, Cenk Ergan, Michael R. Fortin, Robert L. Reinauer
  • Patent number: 8903736
    Abstract: A system for serving advertisements determines the frequency of occurrence for each parameter of a plurality of parameters associated with a plurality of search queries. The plurality of parameters are associated with one or more advertisements. The system stores at least some parameters to a first storage based on the frequency of occurrence of the parameters. The system stores the other parameters to a second storage that has a higher latency than the first storage. When serving advertisements, the system ranks advertisements for delivery based on the parameters stored in the first storage device and the second storage.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: December 2, 2014
    Assignee: Yahoo! Inc.
    Inventors: Arun Kejariwal, Amir Behroozi, Sapan Panigrahi
  • Patent number: 8886899
    Abstract: Managing access to an external memory in a computing system comprising one or more cores includes: receiving memory requests to access a memory at a memory controller coupled to at least one of the cores; assigning, by the memory controller, respective priorities to the memory requests, the priorities being based on priority configuration information; providing access, by the memory controller, to the memory based on the memory requests according to the assigned priorities. Messages are received at the memory controller to modify the priority configuration information.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: November 11, 2014
    Assignee: Tilera Corporation
    Inventor: Liewei Bao
  • Patent number: 8880819
    Abstract: Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: November 4, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Robert M. Walker
  • Publication number: 20140325166
    Abstract: A hybrid drive includes multiple parts: a performance part (e.g., a flash memory device) and a base part (e.g., a magnetic or other rotational disk drive). A drive access system, which is typically part of an operating system of a computing device, issues input/output (I/O) commands to the hybrid drive to store data to and retrieve data from the hybrid drive. The drive access system supports multiple priority levels and obtains priority levels for groups of data identified by logical block addresses (LBAs). The LBAs read while the device is operating in a power saving mode are assigned a priority level that is at least the lowest of the multiple priority levels supported by the device, increasing the likelihood that LBAs read while the device is operating in the power saving mode are stored in the performance part of the hybrid drive.
    Type: Application
    Filed: April 24, 2013
    Publication date: October 30, 2014
    Applicant: MICROSOFT CORPORATION
    Inventors: Mehmet Iyigun, Yevgeniy M. Bak, Eric M. Bluestein, Robin A. Alexander, Andrew M. Herron, Xiaozhong Xing
  • Patent number: 8874822
    Abstract: Described herein are method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: October 28, 2014
    Assignee: NetApp, Inc.
    Inventors: George Totolos, Jr., Nhiem T. Nguyen
  • Patent number: 8874857
    Abstract: A method, computer program product, and computing system for compartmentalizing a LUN into a plurality of portions that are each assigned to one or more hosts. An ownership tracking structure is maintained for the LUN, wherein the ownership tracking structure includes a data entry associated with each of the plurality of portions within the LUN. One or more properties of the ownership tracking structure are monitored to determine if the ownership tracking structure needs to be compressed. If the ownership tracking structure needs to be compressed, one or more actions are taken to reduce the size of the ownership tracking structure.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: October 28, 2014
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Randall H. Shain
  • Patent number: 8874826
    Abstract: Provided are a method and apparatus for programming a buffer cache in a Solid State Disk (SSD) system. The buffer cache programming apparatus in the SSD system may include a buffer cache unit to store pages, a memory unit including a plurality of memory chips, and a control unit to select at least one of the page as a victim page, based on a delay occurring when a page is stored in at least one target memory chip among the plurality of memory chips.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: October 28, 2014
    Assignee: OCZ Storage Solutions, Inc.
    Inventors: Jin-Ho Seol, Seung-Ryoul Maeng, Jin-Soo Kim, Jae-Geuk Kim, Hyo-Taek Shim, Han-Mook Park
  • Patent number: 8874810
    Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a plurality of storage nodes and a master controller. The storage nodes store information. The storage node includes an upstream communication buffer which is locally controlled at the storage node to facilitate resolution of conflicts in upstream communications. The master controller controlls the flow of traffic to the node based upon constraints of the upstream communication buffer. In one embodiment, communication between the master controller and the node has a determined maximum latency. The storage node can be coupled to the master controller in accordance with a chain memory configuration.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: October 28, 2014
    Assignee: Spansion LLC
    Inventors: Roger Dwain Isaac, Seiji Miura
  • Patent number: 8868855
    Abstract: A request management system includes a request priority queue module prioritizing requests to be placed in queues based on priorities, and a request priority rule module setting an order of placement of the requests in the queues. The request management system further includes a computerized request monitoring and management module dynamically managing processing of a request from the prioritized requests based on a request processing statistic, the priorities and the order of placement.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: October 21, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Biren Narendra Shah, Scott Friedheim
  • Patent number: 8868861
    Abstract: In an information recording apparatus, when it is determined to perform a copy process, a copy processor copies content data cached in a first storage section to an information recording medium as copy destination. A process-result sender sends, to a copy-count management server, a result of the copy process. A cached-data abandoning unit abandons the content data cached in the first storage section if information regarding an allowable number of copies on which the result of the copy process has been reflected represents that a next copy process is disallowed.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: October 21, 2014
    Assignee: Pioneer Corporation
    Inventors: Yuji Shimizu, Takeshi Koda
  • Publication number: 20140310485
    Abstract: A field for which a first priority level that has been set is the same as a second priority level that is stored in a priority level storage portion is specified as an update field from among a plurality of fields that have been defined in a content that is stored in a data storage portion. At least one character that is contained in the update field is updated in the specified order. A level of the second priority level is lowering by one level in a case where a character rollover has occurred during the updating of the at least one character. Printable data for the content in which the at least one character has been updated is created in a case where the character rollover has not occurred during the updating of the at least one character. The update field is specified every time the second priority level that is stored in the priority level storage portion is lowered.
    Type: Application
    Filed: March 19, 2014
    Publication date: October 16, 2014
    Applicant: Brother Kogyo Kabushiki Kaisha
    Inventor: Junya Kawai
  • Patent number: 8862840
    Abstract: A distributed storage management apparatus includes a monitoring unit configured to monitor a request pattern of each storage node of a plurality of storage nodes configured to distributively store data and at least one replica of the data; a group setting unit configured to receive a request and classify the plurality of storage nodes into a safe group and an unsafe group based on the monitored request pattern of each storage node; and a request transfer unit configured to transfer the received request to the safe group.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju-Pyung Lee
  • Patent number: 8856468
    Abstract: According to one embodiment, a memory device includes a memory unit, a first storage unit, a second storage unit, a third storage unit, a data move unit, and a controller. The first storage unit stores a logical address and an intermediate address. The second storage unit stores the intermediate address and the physical address corresponding to the intermediate address. The third storage unit stores a flag corresponding to the logical address and the intermediate address. The flag represents whether read of latest data by a read operation has succeeded. When the flag stored in the third storage unit represents a success of the read of the latest data, the controller determines whether write has been done for the same logical address of the memory unit during the data move processing, and if the write has been done, invalidates the data move processing.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Fukuda
  • Patent number: 8856439
    Abstract: A method for selectively storing data identified by a software application in higher performance media may include executing control programming for an operating system and a software application hosted by the operating system. The software application assigns a first importance level to a first portion of data and a second importance level to a second portion of data. A first portion of data having the first importance level assigned by the software application is stored in a first storage medium at the instruction of the operating system. A second portion of data having the second importance level assigned by the software application is stored in a second storage medium at the instruction of the operating system. The second storage medium has at least one performance, reliability, or security characteristic different from the first storage medium.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: October 7, 2014
    Assignee: LSI Corporation
    Inventors: Bret S. Weber, Jeremy Pinson, Mark Nossokoff, Brian McKean
  • Patent number: 8854852
    Abstract: A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Zvi Regev
  • Patent number: 8850600
    Abstract: A data storage device protecting security code stored therein and a data storage system including same are disclosed. The data storage device efficiently prevents unauthorized access to the security code by allowing command descriptor block (CDB) information to be read using only a read-only memory (ROM).
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: September 30, 2014
    Assignee: Seagate Technology International
    Inventors: Jun Seok Shim, Young Sun Park
  • Patent number: 8850108
    Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. The chassis includes power distribution, a high speed communication bus and the ability to install one or more storage nodes which may use the power distribution and communication bus. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: September 30, 2014
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, John Colgrove, Robert Lee, Peter Vajgel, Par Botes
  • Patent number: 8850557
    Abstract: Disclosed are a processor and processing method that provide non-hierarchical computer security enhancements for context states. The processor can comprise a context control unit that uses context identifier tags associated with corresponding contexts to control access by the contexts to context information (i.e., context states) contained in the processor's non-stackable and/or stackable registers. For example, in response to an access request, the context control unit can grant a specific context access to a register only when that register is tagged with a specific context identifier tag. If the register is tagged with another context identifier tag, the contents of the specific register are saved in a context save area of memory and the previous context states of the specific context are restored to the specific register before access can be granted.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Richard H. Boivie, William E. Hall, Guerney D. H. Hunt, Suzanne K. McIntosh, Mark F. Mergen, Marcel C. Rosu, David R. Safford, David C. Toll, Carl Lynn C. Karger
  • Patent number: 8849351
    Abstract: The present invention provides a method involving at least one mobile unit having at least one first session with a base station router. The method includes vacating at least one first session associated with the at least one mobile unit.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: September 30, 2014
    Assignee: Alcatel Lucent
    Inventors: John K. Burgess, Ken Del Signore, David Vollman, David Welch
  • Patent number: 8843707
    Abstract: A mechanism is provided for dynamic cache allocation using bandwidth. A bandwidth between a higher level cache and a lower level cache is monitored. Responsive to bandwidth usage between the higher level cache and the lower level cache being below a predetermined low bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a first allocation policy. Responsive to bandwidth usage between the higher level cache and the lower level cache being above a predetermined high bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a second allocation policy.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: David M. Daly, Benjiman L. Goodman, Stephen J. Powell, Aaron C. Sawdey, Jeffrey A. Stuecheli
  • Patent number: 8838094
    Abstract: According to various embodiments, there is provided a method of acquiring information from volatile memory of a mobile device, the method including: accessing the volatile memory of the mobile device used by an application operating on the mobile device to store communicated information with a communication device; acquiring a copy of data present in the volatile memory; and analyzing the copy of data to extract the communicated information.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: September 16, 2014
    Assignee: Agency for Science, Technology and Research
    Inventor: Ling Ling Vrizlynn Thing
  • Patent number: 8838916
    Abstract: A method uses a record of I/O priorities in a determination of a storage medium of a hybrid storage system in which to store a file. The method maintains the record of I/O priorities by assigning an I/O temperature value to each request for access to the file based upon an I/O priority level of the process making the request. The method marks the file as hot if the file temperature value is greater than a threshold value. The method stores files marked as hot in a lower latency storage medium of the hybrid storage medium.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mingming Cao, Ben Chociej, Scott R. Conor, Steven M. French, Matthew R. Lupfer, Steven L. Pratt
  • Publication number: 20140258649
    Abstract: The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Robert Walker
  • Patent number: 8825952
    Abstract: Provided are a computer program product, system, and method for handling high priority requests in a sequential access storage device. Received modified tracks for write requests are cached in a non-volatile storage device integrated with the sequential access storage device. A destage request is added to a request queue for a received write request having modified tracks for the sequential access storage medium cached in the non-volatile storage device. A read request indicting a priority is received. A determination is made of a priority of the read request as having a first priority or a second priority. The read request is added to the request queue in response to determining that the determined priority is the first priority. The read request is processed at a higher priority than the read and destage requests in the request queue in response to determining that the determined priority is the second priority.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Lokesh M. Gupta
  • Patent number: 8826023
    Abstract: Various methods and systems for securing access to hash-based storage systems are disclosed. One method involves receiving information to be stored in a storage system from a storage system client and then generating a key. The key identifies the information to be stored. The value of the key is dependent upon a secret value, which is associated with the storage system. The key is generated, at least in part, by applying a hash algorithm to the information to be stored. The key can then be returned the key to the storage system client. The storage system client can then use the key to retrieve the stored information.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 2, 2014
    Assignee: Symantec Operating Corporation
    Inventor: Craig K. Harmer